On Sat 14 Mar 00:51 PDT 2020, Wesley Cheng wrote:
> From: Jack Pham <[email protected]>
>
> Add device nodes for the USB3 controller, QMP SS PHY and
> SNPS HS PHY.
>
> Signed-off-by: Jack Pham <[email protected]>
> Signed-off-by: Wesley Cheng <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 17 ++++++
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 92 +++++++++++++++++++++++++++++++++
> 2 files changed, 109 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> index 8ab1661..edf0abc 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> @@ -408,3 +408,20 @@
> vdda-pll-supply = <&vreg_l3c_1p2>;
> vdda-pll-max-microamp = <19000>;
> };
> +
> +&usb_1_hsphy {
> + status = "okay";
> + vdda-pll-supply = <&vdd_usb_hs_core>;
> + vdda33-supply = <&vdda_usb_hs_3p1>;
> + vdda18-supply = <&vdda_usb_hs_1p8>;
> +};
> +
> +&usb_1_qmpphy {
> + status = "okay";
> + vdda-phy-supply = <&vreg_l3c_1p2>;
> + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
> +};
> +
> +&usb_1 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 141c21d..cf58fb7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -855,6 +855,98 @@
>
> #freq-domain-cells = <1>;
> };
> +
> + usb_1_hsphy: phy@88e2000 {
Please sort these nodes by address, i.e. this should come right after
the cdsp remoteproc node.
Apart from that this looks good, thank you!
Regards,
Bjorn
> + compatible = "qcom,usb-snps-hs-7nm-phy",
> + "qcom,sm8150-usb-hs-phy";
> + reg = <0 0x088e2000 0 0x400>;
> + status = "disabled";
> + #phy-cells = <0>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> + };
> +
> + usb_1_qmpphy: phy@88e9000 {
> + compatible = "qcom,sm8150-qmp-usb3-phy";
> + reg = <0 0x088e9000 0 0x18c>,
> + <0 0x088e8000 0 0x10>;
> + reg-names = "reg-base", "dp_com";
> + status = "disabled";
> + #clock-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> + clock-names = "aux", "ref_clk_src", "ref", "com_aux";
> +
> + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_PHY_PRIM_BCR>;
> + reset-names = "phy", "common";
> +
> + usb_1_ssphy: lanes@88e9200 {
> + reg = <0 0x088e9200 0 0x200>,
> + <0 0x088e9400 0 0x200>,
> + <0 0x088e9c00 0 0x218>,
> + <0 0x088e9600 0 0x200>,
> + <0 0x088e9800 0 0x200>,
> + <0 0x088e9a00 0 0x100>;
> + #phy-cells = <0>;
> + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "usb3_phy_pipe_clk_src";
> + };
> + };
> +
> + usb_1: usb@a6f8800 {
> + compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
> + reg = <0 0x0a6f8800 0 0x400>;
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;
> + clock-names = "cfg_noc", "core", "iface", "mock_utmi",
> + "sleep", "xo";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <150000000>;
> +
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hs_phy_irq", "ss_phy_irq",
> + "dm_hs_phy_irq", "dp_hs_phy_irq";
> +
> + power-domains = <&gcc USB30_PRIM_GDSC>;
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> + usb_1_dwc3: dwc3@a600000 {
> + compatible = "snps,dwc3";
> + reg = <0 0x0a600000 0 0xcd00>;
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> + phy-names = "usb2-phy", "usb3-phy";
> + };
> + };
> };
>
> timer {
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
On 3/16/2020 3:24 PM, Bjorn Andersson wrote:
> On Sat 14 Mar 00:51 PDT 2020, Wesley Cheng wrote:
>
>> From: Jack Pham <[email protected]>
>>
>> Add device nodes for the USB3 controller, QMP SS PHY and
>> SNPS HS PHY.
>>
>> Signed-off-by: Jack Pham <[email protected]>
>> Signed-off-by: Wesley Cheng <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 17 ++++++
>> arch/arm64/boot/dts/qcom/sm8150.dtsi | 92 +++++++++++++++++++++++++++++++++
>> 2 files changed, 109 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
>> index 8ab1661..edf0abc 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
>> @@ -408,3 +408,20 @@
>> vdda-pll-supply = <&vreg_l3c_1p2>;
>> vdda-pll-max-microamp = <19000>;
>> };
>> +
>> +&usb_1_hsphy {
>> + status = "okay";
>> + vdda-pll-supply = <&vdd_usb_hs_core>;
>> + vdda33-supply = <&vdda_usb_hs_3p1>;
>> + vdda18-supply = <&vdda_usb_hs_1p8>;
>> +};
>> +
>> +&usb_1_qmpphy {
>> + status = "okay";
>> + vdda-phy-supply = <&vreg_l3c_1p2>;
>> + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
>> +};
>> +
>> +&usb_1 {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> index 141c21d..cf58fb7 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> @@ -855,6 +855,98 @@
>>
>> #freq-domain-cells = <1>;
>> };
>> +
>> + usb_1_hsphy: phy@88e2000 {
>
> Please sort these nodes by address, i.e. this should come right after
> the cdsp remoteproc node.
>
>
> Apart from that this looks good, thank you!
>
> Regards,
> Bjorn
>
Hi Bjorn,
Thanks for the update, will remember this for future changes as well!
Will update this in the next patch series.
>> + compatible = "qcom,usb-snps-hs-7nm-phy",
>> + "qcom,sm8150-usb-hs-phy";
>> + reg = <0 0x088e2000 0 0x400>;
>> + status = "disabled";
>> + #phy-cells = <0>;
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "ref";
>> +
>> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
>> + };
>> +
>> + usb_1_qmpphy: phy@88e9000 {
>> + compatible = "qcom,sm8150-qmp-usb3-phy";
>> + reg = <0 0x088e9000 0 0x18c>,
>> + <0 0x088e8000 0 0x10>;
>> + reg-names = "reg-base", "dp_com";
>> + status = "disabled";
>> + #clock-cells = <1>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
>> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
>> + clock-names = "aux", "ref_clk_src", "ref", "com_aux";
>> +
>> + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
>> + <&gcc GCC_USB3_PHY_PRIM_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + usb_1_ssphy: lanes@88e9200 {
>> + reg = <0 0x088e9200 0 0x200>,
>> + <0 0x088e9400 0 0x200>,
>> + <0 0x088e9c00 0 0x218>,
>> + <0 0x088e9600 0 0x200>,
>> + <0 0x088e9800 0 0x200>,
>> + <0 0x088e9a00 0 0x100>;
>> + #phy-cells = <0>;
>> + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "usb3_phy_pipe_clk_src";
>> + };
>> + };
>> +
>> + usb_1: usb@a6f8800 {
>> + compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
>> + reg = <0 0x0a6f8800 0 0x400>;
>> + status = "disabled";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + dma-ranges;
>> +
>> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
>> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
>> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
>> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
>> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;
>> + clock-names = "cfg_noc", "core", "iface", "mock_utmi",
>> + "sleep", "xo";
>> +
>> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
>> + assigned-clock-rates = <19200000>, <150000000>;
>> +
>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hs_phy_irq", "ss_phy_irq",
>> + "dm_hs_phy_irq", "dp_hs_phy_irq";
>> +
>> + power-domains = <&gcc USB30_PRIM_GDSC>;
>> +
>> + resets = <&gcc GCC_USB30_PRIM_BCR>;
>> +
>> + usb_1_dwc3: dwc3@a600000 {
>> + compatible = "snps,dwc3";
>> + reg = <0 0x0a600000 0 0xcd00>;
>> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + snps,dis_u2_susphy_quirk;
>> + snps,dis_enblslpm_quirk;
>> + phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
>> + phy-names = "usb2-phy", "usb3-phy";
>> + };
>> + };
>> };
>>
>> timer {
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>> a Linux Foundation Collaborative Project
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project