2006-08-01 13:04:47

by Sergio Monteiro Basto

[permalink] [raw]
Subject: Re: [PATCH for 2.6.18] [2/8] x86_64: On Intel systems when CPU has C3 don't use TSC

On Sat, 2006-07-29 at 21:42 +0200, Andi Kleen wrote:
> On Intel systems generally the TSC stops in C3 or deeper,
> so don't use it there. Follows similar logic on i386.
>
> This should fix problems on Meroms.
>
> Signed-off-by: Andi Kleen <[email protected]>
>
...
> + /* Most intel systems have synchronized TSCs except for
> + multi node systems */
> + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
> +#ifdef CONFIG_ACPI
> + /* But TSC doesn't tick in C3 so don't use it there */
> + if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 100)
> + return 1;
> +#endif
> + return 0;
> + }
> +
> /* Assume multi socket systems are not synchronized */
> return num_present_cpus() > 1;
> }

Hi,

I had some faith in this patch , but this just enable boot parameter
notsc (which I already use). And "just" disable tsc don't solve all the
problems.

After "Using ACPI (MADT) for SMP configuration information"
my acpi_fadt.length is great than 0
acpi_fadt.plvl3_lat is 1001

On BIOS 1.40 update description of ASRock, claims this VIA chipset have
C1 stepping support.

this is a Pentium Dual Core on a 775Dual-880Pro
http://www.asrock.com/product/775Dual-880Pro.htm
http://bugme.osdl.org/show_bug.cgi?id=6419

Thanks,
Sérgio M. B.


2006-08-01 17:26:29

by Andi Kleen

[permalink] [raw]
Subject: Re: [discuss] Re: [PATCH for 2.6.18] [2/8] x86_64: On Intel systems when CPU has C3 don't use TSC


> I had some faith in this patch , but this just enable boot parameter
> notsc (which I already use). And "just" disable tsc don't solve all the
> problems.

What problems do you have?

>
>
> After "Using ACPI (MADT) for SMP configuration information"
> my acpi_fadt.length is great than 0
> acpi_fadt.plvl3_lat is 1001

You don't have C3 support so the patch doesn't apply to you.

> On BIOS 1.40 update description of ASRock, claims this VIA chipset have
> C1 stepping support.

C1 stepping is a processor revision; it has nothing to do with
ACPI C* power states.

-Andi

2006-08-01 21:57:57

by Andi Kleen

[permalink] [raw]
Subject: Re: [discuss] Re: [PATCH for 2.6.18] [2/8] x86_64: On Intel systems when CPU has C3 don't use TSC

On Tuesday 01 August 2006 23:40, Sergio Monteiro Basto wrote:
> On Tue, 2006-08-01 at 19:10 +0200, Andi Kleen wrote:
> > > I had some faith in this patch , but this just enable boot parameter
> > > notsc (which I already use). And "just" disable tsc don't solve all
> > the
> > > problems.
> >
> > What problems do you have?
> >
> Hi Andi ,
> if I boot without notsc , I have many lost timer tickets.

Lost timer ticks print a rip. Do you have some samples?

Anyways, for a single socket Intel dual core TSCs should be definitely
synced so I don't know what could be wrong on your system.
Please post full boot.msg at least.

-Andi

2006-08-01 21:40:27

by Sergio Monteiro Basto

[permalink] [raw]
Subject: Re: [discuss] Re: [PATCH for 2.6.18] [2/8] x86_64: On Intel systems when CPU has C3 don't use TSC

On Tue, 2006-08-01 at 19:10 +0200, Andi Kleen wrote:
> > I had some faith in this patch , but this just enable boot parameter
> > notsc (which I already use). And "just" disable tsc don't solve all
> the
> > problems.
>
> What problems do you have?
>
Hi Andi ,
if I boot without notsc , I have many lost timer tickets.
if I boot with notsc , I have,at begging, a few lost timer ticket, and
after some stress usb modem I got
uhci_hcd 0000:00:10.1: host controller process error, something bad
happened!
uhci_hcd 0000:00:10.1: host controller halted, very bad!
uhci_hcd 0000:00:10.1: HC died; cleaning up
usb 3-2: USB disconnect, address 2


Thanks for your reply
--
S?rgio M. B.


Attachments:
smime.p7s (2.12 kB)