2008-10-25 00:21:36

by Alok Kataria

Subject: [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition

Hi,

These patches define a framework for hypervisor detection and setting of
hypervisor feature bits. We define a X86_FEATURE_TSC_RELIABLE bit which
is a synthetic bit. This is set when running under VMware. This feature
bit is used to skip TSC checks which can fail on virtualization platform
due to timing differences when running on virtual cpus.

Thanks,
Alok

2008-10-27 11:02:31

by Ingo Molnar

Subject: Re: [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition

* Alok Kataria <[email protected]> wrote:

> Hi,
>
> These patches define a framework for hypervisor detection and
> setting of hypervisor feature bits. We define a
> X86_FEATURE_TSC_RELIABLE bit which is a synthetic bit. This is set
> when running under VMware. This feature bit is used to skip TSC
> checks which can fail on virtualization platform due to timing
> differences when running on virtual cpus.

okay, this looks a lot better structurally - the DMI angle and the
synthetic CPU flag, and the clocksource smarts are all a clean
approach. Peter, any objections?

Ingo