The Tegra's i2c controller required two clock sources for proper
operation named as div-clk and fast-clk.
Adding support to make sure that driver will get these clocks and
enable before any transfer and disable after transfer completed.
Patch 1 add the entry of fast clock in clock table.
Patch 2 modify i2c driver to get the div and fast clock.
Patch 3 name the connection of the clock entry.
Patch 4 removes non-required entry from tegra20 clock table.
Laxman Dewangan (4):
ARM: tegra: clock: add i2c fast clock entry in clock table
i2c: tegra: pass proper name for getting clock
ARM: tegra: clock: add connection name in i2c clock entry
ARM: tegra: clock: remove unused clock entry for i2c
arch/arm/mach-tegra/tegra20_clocks_data.c | 20 +++++-------
arch/arm/mach-tegra/tegra30_clocks_data.c | 15 ++++++---
drivers/i2c/busses/i2c-tegra.c | 46 ++++++++++++++--------------
3 files changed, 41 insertions(+), 40 deletions(-)
Add connection name "div-clk" for the i2c clock entry.
Signed-off-by: Laxman Dewangan <[email protected]>
---
arch/arm/mach-tegra/tegra20_clocks_data.c | 8 ++++----
arch/arm/mach-tegra/tegra30_clocks_data.c | 10 +++++-----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 7312ecd..c1318c2 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -889,10 +889,10 @@ PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX
PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
-PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
-PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
-PERIPH_CLK(dvc, "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
+PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
+PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
+PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
+PERIPH_CLK(dvc, "tegra-i2c.3", "div-clk", 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
PERIPH_CLK(i2c1_i2c, "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
PERIPH_CLK(i2c2_i2c, "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
PERIPH_CLK(i2c3_i2c, "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index eae85b7..45da437 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1070,11 +1070,11 @@ PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX
PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
-PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c4, "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c5, "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c4, "tegra-i2c.3", "div-clk", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c5, "tegra-i2c.4", "div-clk", 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
--
1.7.1.1
Tegra's i2c controller require two clock sources named as
div-clk and fast-clk for proper operation.
Currently, the entry of fast-clk is missing in tegra30
clock table and it is incorrectly named in the tegra20
clock table.
Adds aliases to enable lookups for "fast-clk" to succeed.
A later patch will remove the incorrectly named clock,
once the driver is modified to use the new name.
Signed-off-by: Laxman Dewangan <[email protected]>
---
arch/arm/mach-tegra/tegra20_clocks_data.c | 4 ++++
arch/arm/mach-tegra/tegra30_clocks_data.c | 5 +++++
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index b5c518e..7312ecd 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -1028,6 +1028,10 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
CLK_DUPLICATE("cop", "tegra-avp", "cop"),
CLK_DUPLICATE("vde", "tegra-aes", "vde"),
CLK_DUPLICATE("cclk", NULL, "cpu"),
+ CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
+ CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
+ CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
+ CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
};
#define CLK(dev, con, ck) \
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index c924240..eae85b7 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1287,6 +1287,11 @@ struct clk_duplicate tegra_clk_duplicates[] = {
CLK_DUPLICATE("dam1", NULL, "dam1"),
CLK_DUPLICATE("dam2", NULL, "dam2"),
CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
+ CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
+ CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
+ CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
+ CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
+ CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
};
struct clk *tegra_ptr_clks[] = {
--
1.7.1.1
Tegra20 clock table have the entry for clock (tegra_i2c.x, "i2c")
which is no more require as driver acquire clock with name of
"div-clk" and "fast-clk".
Remove these entries from table.
Signed-off-by: Laxman Dewangan <[email protected]>
---
arch/arm/mach-tegra/tegra20_clocks_data.c | 8 --------
1 files changed, 0 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index c1318c2..6516beb 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -893,10 +893,6 @@ PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_pllc_
PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
PERIPH_CLK(dvc, "tegra-i2c.3", "div-clk", 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
-PERIPH_CLK(i2c1_i2c, "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
-PERIPH_CLK(i2c2_i2c, "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
-PERIPH_CLK(i2c3_i2c, "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
-PERIPH_CLK(dvc_i2c, "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
@@ -962,10 +958,6 @@ static struct clk *tegra_list_clks[] = {
&tegra_i2c2,
&tegra_i2c3,
&tegra_dvc,
- &tegra_i2c1_i2c,
- &tegra_i2c2_i2c,
- &tegra_i2c3_i2c,
- &tegra_dvc_i2c,
&tegra_uarta,
&tegra_uartb,
&tegra_uartc,
--
1.7.1.1
Tegra's i2c controller require two clock sources named as
div_clk and fast_clk.
This change make sure that driver pass the correct clock's
name when it acquires clock handle. Also change the
variable name to reflect the correct clock handles.
Signed-off-by: Laxman Dewangan <[email protected]>
---
drivers/i2c/busses/i2c-tegra.c | 46 ++++++++++++++++++++--------------------
1 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 66eb53f..7149625 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -117,8 +117,8 @@ enum msg_end_type {
* struct tegra_i2c_dev - per device i2c context
* @dev: device reference for power management
* @adapter: core i2c layer adapter information
- * @clk: clock reference for i2c controller
- * @i2c_clk: clock reference for i2c bus
+ * @div_clk: clock reference for div clock of i2c controller.
+ * @fast_clk: clock reference for fast clock of i2c controller.
* @base: ioremapped registers cookie
* @cont_id: i2c controller id, used for for packet header
* @irq: irq number of transfer complete interrupt
@@ -134,8 +134,8 @@ enum msg_end_type {
struct tegra_i2c_dev {
struct device *dev;
struct i2c_adapter adapter;
- struct clk *clk;
- struct clk *i2c_clk;
+ struct clk *div_clk;
+ struct clk *fast_clk;
void __iomem *base;
int cont_id;
int irq;
@@ -356,11 +356,11 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
u32 val;
int err = 0;
- clk_prepare_enable(i2c_dev->clk);
+ clk_prepare_enable(i2c_dev->div_clk);
- tegra_periph_reset_assert(i2c_dev->clk);
+ tegra_periph_reset_assert(i2c_dev->div_clk);
udelay(2);
- tegra_periph_reset_deassert(i2c_dev->clk);
+ tegra_periph_reset_deassert(i2c_dev->div_clk);
if (i2c_dev->is_dvc)
tegra_dvc_init(i2c_dev);
@@ -369,7 +369,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
(0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
i2c_writel(i2c_dev, val, I2C_CNFG);
i2c_writel(i2c_dev, 0, I2C_INT_MASK);
- clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
+ clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * 8);
if (!i2c_dev->is_dvc) {
u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
@@ -387,7 +387,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
if (tegra_i2c_flush_fifos(i2c_dev))
err = -ETIMEDOUT;
- clk_disable_unprepare(i2c_dev->clk);
+ clk_disable_unprepare(i2c_dev->div_clk);
if (i2c_dev->irq_disabled) {
i2c_dev->irq_disabled = 0;
@@ -563,7 +563,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
if (i2c_dev->is_suspended)
return -EBUSY;
- clk_prepare_enable(i2c_dev->clk);
+ clk_prepare_enable(i2c_dev->div_clk);
for (i = 0; i < num; i++) {
enum msg_end_type end_type = MSG_END_STOP;
if (i < (num - 1)) {
@@ -576,7 +576,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
if (ret)
break;
}
- clk_disable_unprepare(i2c_dev->clk);
+ clk_disable_unprepare(i2c_dev->div_clk);
return ret ?: i;
}
@@ -596,8 +596,8 @@ static int __devinit tegra_i2c_probe(struct platform_device *pdev)
struct tegra_i2c_dev *i2c_dev;
struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
struct resource *res;
- struct clk *clk;
- struct clk *i2c_clk;
+ struct clk *div_clk;
+ struct clk *fast_clk;
const unsigned int *prop;
void __iomem *base;
int irq;
@@ -622,16 +622,16 @@ static int __devinit tegra_i2c_probe(struct platform_device *pdev)
}
irq = res->start;
- clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(clk)) {
+ div_clk = devm_clk_get(&pdev->dev, "div-clk");
+ if (IS_ERR(div_clk)) {
dev_err(&pdev->dev, "missing controller clock");
- return PTR_ERR(clk);
+ return PTR_ERR(div_clk);
}
- i2c_clk = devm_clk_get(&pdev->dev, "i2c");
- if (IS_ERR(i2c_clk)) {
+ fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
+ if (IS_ERR(fast_clk)) {
dev_err(&pdev->dev, "missing bus clock");
- return PTR_ERR(i2c_clk);
+ return PTR_ERR(fast_clk);
}
i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
@@ -641,8 +641,8 @@ static int __devinit tegra_i2c_probe(struct platform_device *pdev)
}
i2c_dev->base = base;
- i2c_dev->clk = clk;
- i2c_dev->i2c_clk = i2c_clk;
+ i2c_dev->div_clk = div_clk;
+ i2c_dev->fast_clk = fast_clk;
i2c_dev->adapter.algo = &tegra_i2c_algo;
i2c_dev->irq = irq;
i2c_dev->cont_id = pdev->id;
@@ -681,7 +681,7 @@ static int __devinit tegra_i2c_probe(struct platform_device *pdev)
return ret;
}
- clk_prepare_enable(i2c_dev->i2c_clk);
+ clk_prepare_enable(i2c_dev->fast_clk);
i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
i2c_dev->adapter.owner = THIS_MODULE;
@@ -696,7 +696,7 @@ static int __devinit tegra_i2c_probe(struct platform_device *pdev)
ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
if (ret) {
dev_err(&pdev->dev, "Failed to add I2C adapter\n");
- clk_disable_unprepare(i2c_dev->i2c_clk);
+ clk_disable_unprepare(i2c_dev->fast_clk);
return ret;
}
--
1.7.1.1
On Wednesday 08 August 2012 01:21 PM, Laxman Dewangan wrote:
> The Tegra's i2c controller required two clock sources for proper
> operation named as div-clk and fast-clk.
>
> Adding support to make sure that driver will get these clocks and
> enable before any transfer and disable after transfer completed.
>
> Patch 1 add the entry of fast clock in clock table.
> Patch 2 modify i2c driver to get the div and fast clock.
> Patch 3 name the connection of the clock entry.
> Patch 4 removes non-required entry from tegra20 clock table.
Hi Wolfram/Stephen,
This patch series very much depends on the common clock changes happens
on Tegra tree and I think it should go in Tegra common clock tree.
Thanks,
Laxman
On 08/08/2012 01:51 AM, Laxman Dewangan wrote:
> The Tegra's i2c controller required two clock sources for proper
> operation named as div-clk and fast-clk.
>
> Adding support to make sure that driver will get these clocks and
> enable before any transfer and disable after transfer completed.
This works fine on Cardhu and Ventana for me. I'll apply it once I get
an ack from Wolfram to take the I2C driver patch through the Tegra tree.
On 08/08/2012 11:57 AM, Stephen Warren wrote:
> On 08/08/2012 01:51 AM, Laxman Dewangan wrote:
>> The Tegra's i2c controller required two clock sources for proper
>> operation named as div-clk and fast-clk.
>>
>> Adding support to make sure that driver will get these clocks and
>> enable before any transfer and disable after transfer completed.
>
> This works fine on Cardhu and Ventana for me. I'll apply it once I get
> an ack from Wolfram to take the I2C driver patch through the Tegra tree.
I haven't heard from Wolfram, but since the I2C driver patch is pretty
trivial, and pretty much has to go through the Tegra tree due to
dependencies on other Tegra patches, I went ahead and applied this
series to Tegra's for-3.7/clock branch.
On Wed, Aug 15, 2012 at 10:58:04AM -0600, Stephen Warren wrote:
> On 08/08/2012 11:57 AM, Stephen Warren wrote:
> > On 08/08/2012 01:51 AM, Laxman Dewangan wrote:
> >> The Tegra's i2c controller required two clock sources for proper
> >> operation named as div-clk and fast-clk.
> >>
> >> Adding support to make sure that driver will get these clocks and
> >> enable before any transfer and disable after transfer completed.
> >
> > This works fine on Cardhu and Ventana for me. I'll apply it once I get
> > an ack from Wolfram to take the I2C driver patch through the Tegra tree.
>
> I haven't heard from Wolfram, but since the I2C driver patch is pretty
> trivial, and pretty much has to go through the Tegra tree due to
> dependencies on other Tegra patches, I went ahead and applied this
> series to Tegra's for-3.7/clock branch.
For the I2C subsystem:
Acked-by: Wolfram Sang <[email protected]>
--
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