2014-10-21 09:00:13

by Sebastian Hesselbarth

[permalink] [raw]
Subject: [PATCH 0/9] Marvell PXA168 libphy handling and Berlin Ethernet

This patch series deals with a removing a IP feature that can be found
on all currently supported Marvell Ethernet IP (pxa168_eth, mv643xx_eth,
mvneta). The MAC IP allows to automatically perform PHY auto-negotiation
without software interaction.

However, this feature (a) fundamentally clashes with the way libphy works
and (b) is unable to deal with quirky PHYs that require special treatment.
In this series, pxa168_eth driver is rewritten to completely disable that
feature and properly deal with libphy provided PHYs.

This is the real patch set after an RFT sent earlier. Unfortunately, there
was no testing from MMP/gplug but there was for BG2Q. However, it still
would be great to get a Tested-by on gplug. Also, this patch set is now
rebased on v3.18-rc1. As usual, a branch on top of v3.18-rc1 can be found at

git://git.infradead.org/users/hesselba/linux-berlin.git devel/bg2-bg2cd-eth-v1

Patches 1-5 should go through David's net tree, I'll pick up the DT patches
6-9.

Compared to the RFT, there have been some changes:
- added phy-connection-type property to BG2Q PHY DT node
- bail out from pxa168_eth_adjust_link when there is no change in
PHY parameters. Also, add a call to phy_print_status.

Patch 1 adds support for Marvell 88E3016 FastEthernet PHY that is also
integrated in Marvell Berlin BG2/BG2CD SoCs.

Patch 2 allows to pass phy_interface_t on pxa168_eth platform_data that
is only used by mach-mmp/gplug. From the board setup, I guessed gplug's
PHY is connected via RMII. The patch still isn't even compile tested.

Patches 3-5 prepare proper libphy handling and finally remove all in-driver
PHY mangling related to the feature explained above.

Patches 6-9 add corresponding ethernet DT nodes to BG2, BG2CD, add a
phy-connection-type property to BG2Q and enable ethernet on BG2-based Sony
NSZ-GS7. I have tested all this on GS7 successfully with ip=dhcp on 100M FD.

Antoine Ténart (1):
ARM: berlin: Add phy-connection-type to BG2Q PHY

Sebastian Hesselbarth (8):
phy: marvell: Add support for 88E3016 FastEthernet PHY
net: pxa168_eth: Provide phy_interface mode on platform_data
net: pxa168_eth: Prepare proper libphy handling
net: pxa168_eth: Remove HW auto-negotiaion
net: pxa168_eth: Remove in-driver PHY mangling
ARM: berlin: Add BG2 ethernet DT nodes
ARM: berlin: Add BG2CD ethernet DT nodes
ARM: berlin: Enable ethernet on Sony NSZ-GS7

arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 2 +
arch/arm/boot/dts/berlin2.dtsi | 36 +++++
arch/arm/boot/dts/berlin2cd.dtsi | 36 +++++
arch/arm/boot/dts/berlin2q.dtsi | 1 +
arch/arm/mach-mmp/gplugd.c | 2 +
drivers/net/ethernet/marvell/pxa168_eth.c | 248 ++++++++++++-----------------
drivers/net/phy/marvell.c | 46 ++++++
include/linux/marvell_phy.h | 1 +
include/linux/pxa168_eth.h | 1 +
9 files changed, 225 insertions(+), 148 deletions(-)

---
Cc: "David S. Miller" <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Eric Miao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
--
2.1.1


2014-10-21 08:54:01

by Sebastian Hesselbarth

[permalink] [raw]
Subject: [PATCH 1/9] phy: marvell: Add support for 88E3016 FastEthernet PHY

Marvell 88E3016 is a FastEthernet PHY that also can be found in Marvell
Berlin SoCs as integrated PHY.

Tested-by: Antoine Ténart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: "David S. Miller" <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/net/phy/marvell.c | 46 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/marvell_phy.h | 1 +
2 files changed, 47 insertions(+)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index bd37e45c89c0..d2b2f2f795d5 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -118,6 +118,9 @@

#define MII_M1116R_CONTROL_REG_MAC 21

+#define MII_88E3016_PHY_SPEC_CTRL 0x10
+#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
+#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030

MODULE_DESCRIPTION("Marvell PHY driver");
MODULE_AUTHOR("Andy Fleming");
@@ -434,6 +437,25 @@ static int m88e1116r_config_init(struct phy_device *phydev)
return 0;
}

+static int m88e3016_config_init(struct phy_device *phydev)
+{
+ int reg;
+
+ /* Enable Scrambler and Auto-Crossover */
+ reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
+ if (reg < 0)
+ return reg;
+
+ reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
+ reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
+
+ reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
+ if (reg < 0)
+ return reg;
+
+ return 0;
+}
+
static int m88e1111_config_init(struct phy_device *phydev)
{
int err;
@@ -770,6 +792,12 @@ static int marvell_read_status(struct phy_device *phydev)
return 0;
}

+static int marvell_aneg_done(struct phy_device *phydev)
+{
+ int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
+ return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
+}
+
static int m88e1121_did_interrupt(struct phy_device *phydev)
{
int imask;
@@ -1050,6 +1078,23 @@ static struct phy_driver marvell_drivers[] = {
.suspend = &genphy_suspend,
.driver = { .owner = THIS_MODULE },
},
+ {
+ .phy_id = MARVELL_PHY_ID_88E3016,
+ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = "Marvell 88E3016",
+ .features = PHY_BASIC_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_aneg = &genphy_config_aneg,
+ .config_init = &m88e3016_config_init,
+ .aneg_done = &marvell_aneg_done,
+ .read_status = &marvell_read_status,
+ .ack_interrupt = &marvell_ack_interrupt,
+ .config_intr = &marvell_config_intr,
+ .did_interrupt = &m88e1121_did_interrupt,
+ .resume = &genphy_resume,
+ .suspend = &genphy_suspend,
+ .driver = { .owner = THIS_MODULE },
+ },
};

static int __init marvell_init(void)
@@ -1079,6 +1124,7 @@ static struct mdio_device_id __maybe_unused marvell_tbl[] = {
{ MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
{ }
};

diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
index 8e9a029e093d..e6982ac3200d 100644
--- a/include/linux/marvell_phy.h
+++ b/include/linux/marvell_phy.h
@@ -16,6 +16,7 @@
#define MARVELL_PHY_ID_88E1318S 0x01410e90
#define MARVELL_PHY_ID_88E1116R 0x01410e40
#define MARVELL_PHY_ID_88E1510 0x01410dd0
+#define MARVELL_PHY_ID_88E3016 0x01410e60

/* struct phy_device dev_flags definitions */
#define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x00000001
--
2.1.1

2014-10-21 08:54:20

by Sebastian Hesselbarth

[permalink] [raw]
Subject: [PATCH 8/9] ARM: berlin: Add phy-connection-type to BG2Q PHY

From: Antoine Ténart <[email protected]>

Internal FastEthernet PHY on BG2Q is connected via MII, add a
corresponding phy-connection-type property.

Tested-by: Antoine Ténart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: "David S. Miller" <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Eric Miao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/berlin2q.dtsi | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 891d56b03922..6dbc520bddc1 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -127,6 +127,7 @@
status = "disabled";

ethphy0: ethernet-phy@0 {
+ phy-connection-type = "mii";
reg = <0>;
};
};
--
2.1.1

2014-10-21 08:54:16

by Sebastian Hesselbarth

[permalink] [raw]
Subject: [PATCH 7/9] ARM: berlin: Add BG2CD ethernet DT nodes

Marvell BG2CD has two fast ethernet controllers with internal PHY,
add the corresponding nodes to SoC dtsi.

Tested-by: Antoine Ténart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: "David S. Miller" <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Eric Miao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/berlin2cd.dtsi | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index cc1df65da504..8ce73a0a23a3 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -66,6 +66,42 @@
clocks = <&chip CLKID_TWD>;
};

+ eth1: ethernet@b90000 {
+ compatible = "marvell,pxa168-eth";
+ reg = <0xb90000 0x10000>;
+ clocks = <&chip CLKID_GETH1>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ /* set by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-handle = <&ethphy1>;
+ status = "disabled";
+
+ ethphy1: ethernet-phy@0 {
+ phy-connection-type = "mii";
+ reg = <0>;
+ };
+ };
+
+ eth0: ethernet@e50000 {
+ compatible = "marvell,pxa168-eth";
+ reg = <0xe50000 0x10000>;
+ clocks = <&chip CLKID_GETH0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ /* set by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-handle = <&ethphy0>;
+ status = "disabled";
+
+ ethphy0: ethernet-phy@0 {
+ phy-connection-type = "mii";
+ reg = <0>;
+ };
+ };
+
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
--
2.1.1

2014-10-21 08:54:14

by Sebastian Hesselbarth

[permalink] [raw]
Subject: [PATCH 6/9] ARM: berlin: Add BG2 ethernet DT nodes

Marvell BG2 has two fast ethernet controllers with internal PHY,
add the corresponding nodes to SoC dtsi.

Tested-by: Antoine Ténart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: "David S. Miller" <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Eric Miao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/berlin2.dtsi | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 9d7c810ebd0b..31d5922263d7 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -79,11 +79,47 @@
clocks = <&chip CLKID_TWD>;
};

+ eth1: ethernet@b90000 {
+ compatible = "marvell,pxa168-eth";
+ reg = <0xb90000 0x10000>;
+ clocks = <&chip CLKID_GETH1>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ /* set by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-handle = <&ethphy1>;
+ status = "disabled";
+
+ ethphy1: ethernet-phy@0 {
+ phy-connection-type = "mii";
+ reg = <0>;
+ };
+ };
+
cpu-ctrl@dd0000 {
compatible = "marvell,berlin-cpu-ctrl";
reg = <0xdd0000 0x10000>;
};

+ eth0: ethernet@e50000 {
+ compatible = "marvell,pxa168-eth";
+ reg = <0xe50000 0x10000>;
+ clocks = <&chip CLKID_GETH0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ /* set by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-handle = <&ethphy0>;
+ status = "disabled";
+
+ ethphy0: ethernet-phy@0 {
+ phy-connection-type = "mii";
+ reg = <0>;
+ };
+ };
+
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
--
2.1.1

2014-10-21 08:54:12

by Sebastian Hesselbarth

[permalink] [raw]
Subject: [PATCH 9/9] ARM: berlin: Enable ethernet on Sony NSZ-GS7

Marvell Berlin BG2 based Sony NSZ-GS7 has one ethernet controller
connected to rear RJ45 jack. Enable it by default.

Tested-by: Antoine Ténart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: "David S. Miller" <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Eric Miao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
index c72bfd468d10..27f2f0ad7562 100644
--- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -26,4 +26,6 @@
};
};

+&eth1 { status = "okay"; };
+
&uart0 { status = "okay"; };
--
2.1.1

2014-10-21 08:57:51

by Sebastian Hesselbarth

[permalink] [raw]
Subject: [PATCH 5/9] net: pxa168_eth: Remove in-driver PHY mangling

With properly using libphy PHYs now, remove the in-driver PHY
mangling.

Tested-by: Antoine Ténart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: "David S. Miller" <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Eric Miao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/net/ethernet/marvell/pxa168_eth.c | 126 ------------------------------
1 file changed, 126 deletions(-)

diff --git a/drivers/net/ethernet/marvell/pxa168_eth.c b/drivers/net/ethernet/marvell/pxa168_eth.c
index 6d671f70e484..0374eac76fdf 100644
--- a/drivers/net/ethernet/marvell/pxa168_eth.c
+++ b/drivers/net/ethernet/marvell/pxa168_eth.c
@@ -177,7 +177,6 @@
#define LINK_UP (1 << 3)

/* Bit definitions for work to be done */
-#define WORK_LINK (1 << 0)
#define WORK_TX_DONE (1 << 1)

/*
@@ -284,7 +283,6 @@ static void eth_port_reset(struct net_device *dev);
static void eth_port_start(struct net_device *dev);
static int pxa168_eth_open(struct net_device *dev);
static int pxa168_eth_stop(struct net_device *dev);
-static int ethernet_phy_setup(struct net_device *dev);

static inline u32 rdl(struct pxa168_eth_private *pep, int offset)
{
@@ -316,26 +314,6 @@ static void abort_dma(struct pxa168_eth_private *pep)
netdev_err(pep->dev, "%s : DMA Stuck\n", __func__);
}

-static int ethernet_phy_get(struct pxa168_eth_private *pep)
-{
- unsigned int reg_data;
-
- reg_data = rdl(pep, PHY_ADDRESS);
-
- return (reg_data >> (5 * pep->port_num)) & 0x1f;
-}
-
-static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr)
-{
- u32 reg_data;
- int addr_shift = 5 * pep->port_num;
-
- reg_data = rdl(pep, PHY_ADDRESS);
- reg_data &= ~(0x1f << addr_shift);
- reg_data |= (phy_addr & 0x1f) << addr_shift;
- wrl(pep, PHY_ADDRESS, reg_data);
-}
-
static void rxq_refill(struct net_device *dev)
{
struct pxa168_eth_private *pep = netdev_priv(dev);
@@ -890,43 +868,9 @@ static int pxa168_eth_collect_events(struct pxa168_eth_private *pep,
}
if (icr & ICR_RXBUF)
ret = 1;
- if (icr & ICR_MII_CH) {
- pep->work_todo |= WORK_LINK;
- ret = 1;
- }
return ret;
}

-static void handle_link_event(struct pxa168_eth_private *pep)
-{
- struct net_device *dev = pep->dev;
- u32 port_status;
- int speed;
- int duplex;
- int fc;
-
- port_status = rdl(pep, PORT_STATUS);
- if (!(port_status & LINK_UP)) {
- if (netif_carrier_ok(dev)) {
- netdev_info(dev, "link down\n");
- netif_carrier_off(dev);
- txq_reclaim(dev, 1);
- }
- return;
- }
- if (port_status & PORT_SPEED_100)
- speed = 100;
- else
- speed = 10;
-
- duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
- fc = (port_status & FLOW_CONTROL_DISABLED) ? 0 : 1;
- netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
- speed, duplex ? "full" : "half", fc ? "en" : "dis");
- if (!netif_carrier_ok(dev))
- netif_carrier_on(dev);
-}
-
static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id)
{
struct net_device *dev = (struct net_device *)dev_id;
@@ -1307,10 +1251,6 @@ static int pxa168_rx_poll(struct napi_struct *napi, int budget)
struct net_device *dev = pep->dev;
int work_done = 0;

- if (unlikely(pep->work_todo & WORK_LINK)) {
- pep->work_todo &= ~(WORK_LINK);
- handle_link_event(pep);
- }
/*
* We call txq_reclaim every time since in NAPI interupts are disabled
* and due to this we miss the TX_DONE interrupt,which is not updated in
@@ -1433,72 +1373,6 @@ static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr,
return -EOPNOTSUPP;
}

-static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr)
-{
- struct mii_bus *bus = pep->smi_bus;
- struct phy_device *phydev;
- int start;
- int num;
- int i;
-
- if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) {
- /* Scan entire range */
- start = ethernet_phy_get(pep);
- num = 32;
- } else {
- /* Use phy addr specific to platform */
- start = phy_addr & 0x1f;
- num = 1;
- }
- phydev = NULL;
- for (i = 0; i < num; i++) {
- int addr = (start + i) & 0x1f;
- if (bus->phy_map[addr] == NULL)
- mdiobus_scan(bus, addr);
-
- if (phydev == NULL) {
- phydev = bus->phy_map[addr];
- if (phydev != NULL)
- ethernet_phy_set_addr(pep, addr);
- }
- }
-
- return phydev;
-}
-
-static void phy_init(struct pxa168_eth_private *pep)
-{
- struct phy_device *phy = pep->phy;
-
- phy_attach(pep->dev, dev_name(&phy->dev), pep->phy_intf);
-
- phy->speed = pep->phy_speed;
- phy->duplex = pep->phy_duplex;
- phy->autoneg = AUTONEG_ENABLE;
- phy->supported &= PHY_BASIC_FEATURES;
- phy->advertising = phy->supported | ADVERTISED_Autoneg;
-
- if (pep->phy_speed != 0) {
- phy->autoneg = AUTONEG_DISABLE;
- phy->advertising = 0;
- }
-
- phy_start_aneg(phy);
-}
-
-static int ethernet_phy_setup(struct net_device *dev)
-{
- struct pxa168_eth_private *pep = netdev_priv(dev);
-
- pep->phy = phy_scan(pep, pep->phy_addr & 0x1f);
- if (pep->phy != NULL)
- phy_init(pep);
-
- update_hash_table_mac_address(pep, NULL, dev->dev_addr);
-
- return 0;
-}
-
static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct pxa168_eth_private *pep = netdev_priv(dev);
--
2.1.1

2014-10-21 08:57:49

by Sebastian Hesselbarth

[permalink] [raw]
Subject: [PATCH 3/9] net: pxa168_eth: Prepare proper libphy handling

Current libphy handling in pxa168_eth lacks proper phy_connect. Prepare
to fix this by first moving phy properties from platform_data to private
driver data.

Tested-by: Antoine Ténart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: "David S. Miller" <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Eric Miao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/net/ethernet/marvell/pxa168_eth.c | 38 +++++++++++++++++++------------
1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/marvell/pxa168_eth.c b/drivers/net/ethernet/marvell/pxa168_eth.c
index c3b209cd0660..332700144d81 100644
--- a/drivers/net/ethernet/marvell/pxa168_eth.c
+++ b/drivers/net/ethernet/marvell/pxa168_eth.c
@@ -197,6 +197,9 @@ struct tx_desc {
struct pxa168_eth_private {
int port_num; /* User Ethernet port number */
int phy_addr;
+ int phy_speed;
+ int phy_duplex;
+ phy_interface_t phy_intf;

int rx_resource_err; /* Rx ring resource error flag */

@@ -1394,19 +1397,17 @@ static void phy_init(struct pxa168_eth_private *pep)
{
struct phy_device *phy = pep->phy;

- phy_attach(pep->dev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII);
+ phy_attach(pep->dev, dev_name(&phy->dev), pep->phy_intf);

- if (pep->pd && pep->pd->speed != 0) {
+ phy->speed = pep->phy_speed;
+ phy->duplex = pep->phy_duplex;
+ phy->autoneg = AUTONEG_ENABLE;
+ phy->supported &= PHY_BASIC_FEATURES;
+ phy->advertising = phy->supported | ADVERTISED_Autoneg;
+
+ if (pep->phy_speed != 0) {
phy->autoneg = AUTONEG_DISABLE;
phy->advertising = 0;
- phy->speed = pep->pd->speed;
- phy->duplex = pep->pd->duplex;
- } else {
- phy->autoneg = AUTONEG_ENABLE;
- phy->speed = 0;
- phy->duplex = 0;
- phy->supported &= PHY_BASIC_FEATURES;
- phy->advertising = phy->supported | ADVERTISED_Autoneg;
}

phy_start_aneg(phy);
@@ -1416,9 +1417,6 @@ static int ethernet_phy_setup(struct net_device *dev)
{
struct pxa168_eth_private *pep = netdev_priv(dev);

- if (pep->pd && pep->pd->init)
- pep->pd->init();
-
pep->phy = phy_scan(pep, pep->phy_addr & 0x1f);
if (pep->phy != NULL)
phy_init(pep);
@@ -1552,13 +1550,23 @@ static int pxa168_eth_probe(struct platform_device *pdev)

pep->port_num = pep->pd->port_number;
pep->phy_addr = pep->pd->phy_addr;
+ pep->phy_speed = pep->pd->speed;
+ pep->phy_duplex = pep->pd->duplex;
+ pep->phy_intf = pep->pd->intf;
+
+ if (pep->pd->init)
+ pep->pd->init();
} else if (pdev->dev.of_node) {
of_property_read_u32(pdev->dev.of_node, "port-id",
&pep->port_num);

np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
- if (np)
- of_property_read_u32(np, "reg", &pep->phy_addr);
+ if (!np) {
+ dev_err(&pdev->dev, "missing phy-handle\n");
+ return -EINVAL;
+ }
+ of_property_read_u32(np, "reg", &pep->phy_addr);
+ pep->phy_intf = of_get_phy_mode(np);
}

/* Hardware supports only 3 ports */
--
2.1.1

2014-10-21 09:00:16

by Sebastian Hesselbarth

[permalink] [raw]
Subject: [PATCH 4/9] net: pxa168_eth: Remove HW auto-negotiaion

Marvell Ethernet IP supports PHY negotiation driven by HW. This
fundamentally clashes with libphy (software) driven negotiation and
also cannot cope with quirky PHYs. Therefore, always disable any HW
negotiation features and properly use libphy's phy_device.

Tested-by: Antoine Ténart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: "David S. Miller" <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Eric Miao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/net/ethernet/marvell/pxa168_eth.c | 100 +++++++++++++++++++++++++-----
1 file changed, 85 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/marvell/pxa168_eth.c b/drivers/net/ethernet/marvell/pxa168_eth.c
index 332700144d81..6d671f70e484 100644
--- a/drivers/net/ethernet/marvell/pxa168_eth.c
+++ b/drivers/net/ethernet/marvell/pxa168_eth.c
@@ -106,6 +106,7 @@
#define SDMA_CMD_ERD (1 << 7)

/* Bit definitions of the Port Config Reg */
+#define PCR_DUPLEX_FULL (1 << 15)
#define PCR_HS (1 << 12)
#define PCR_EN (1 << 7)
#define PCR_PM (1 << 0)
@@ -113,11 +114,17 @@
/* Bit definitions of the Port Config Extend Reg */
#define PCXR_2BSM (1 << 28)
#define PCXR_DSCP_EN (1 << 21)
+#define PCXR_RMII_EN (1 << 20)
+#define PCXR_AN_SPEED_DIS (1 << 19)
+#define PCXR_SPEED_100 (1 << 18)
#define PCXR_MFL_1518 (0 << 14)
#define PCXR_MFL_1536 (1 << 14)
#define PCXR_MFL_2048 (2 << 14)
#define PCXR_MFL_64K (3 << 14)
+#define PCXR_FLOWCTL_DIS (1 << 12)
#define PCXR_FLP (1 << 11)
+#define PCXR_AN_FLOWCTL_DIS (1 << 10)
+#define PCXR_AN_DUPLEX_DIS (1 << 9)
#define PCXR_PRIO_TX_OFF 3
#define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF)

@@ -272,6 +279,7 @@ enum hash_table_entry {
static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd);
static int pxa168_init_hw(struct pxa168_eth_private *pep);
+static int pxa168_init_phy(struct net_device *dev);
static void eth_port_reset(struct net_device *dev);
static void eth_port_start(struct net_device *dev);
static int pxa168_eth_open(struct net_device *dev);
@@ -658,14 +666,7 @@ static void eth_port_start(struct net_device *dev)
struct pxa168_eth_private *pep = netdev_priv(dev);
int tx_curr_desc, rx_curr_desc;

- /* Perform PHY reset, if there is a PHY. */
- if (pep->phy != NULL) {
- struct ethtool_cmd cmd;
-
- pxa168_get_settings(pep->dev, &cmd);
- phy_init_hw(pep->phy);
- pxa168_set_settings(pep->dev, &cmd);
- }
+ phy_start(pep->phy);

/* Assignment of Tx CTRP of given queue */
tx_curr_desc = pep->tx_curr_desc_q;
@@ -720,6 +721,8 @@ static void eth_port_reset(struct net_device *dev)
val = rdl(pep, PORT_CONFIG);
val &= ~PCR_EN;
wrl(pep, PORT_CONFIG, val);
+
+ phy_stop(pep->phy);
}

/*
@@ -981,8 +984,11 @@ static int set_port_config_ext(struct pxa168_eth_private *pep)
skb_size = PCXR_MFL_64K;

/* Extended Port Configuration */
- wrl(pep,
- PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */
+ wrl(pep, PORT_CONFIG_EXT,
+ PCXR_AN_SPEED_DIS | /* Disable HW AN */
+ PCXR_AN_DUPLEX_DIS |
+ PCXR_AN_FLOWCTL_DIS |
+ PCXR_2BSM | /* Two byte prefix aligns IP hdr */
PCXR_DSCP_EN | /* Enable DSCP in IP */
skb_size | PCXR_FLP | /* do not force link pass */
PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */
@@ -990,6 +996,69 @@ static int set_port_config_ext(struct pxa168_eth_private *pep)
return 0;
}

+static void pxa168_eth_adjust_link(struct net_device *dev)
+{
+ struct pxa168_eth_private *pep = netdev_priv(dev);
+ struct phy_device *phy = pep->phy;
+ u32 cfg, cfg_o = rdl(pep, PORT_CONFIG);
+ u32 cfgext, cfgext_o = rdl(pep, PORT_CONFIG_EXT);
+
+ cfg = cfg_o & ~PCR_DUPLEX_FULL;
+ cfgext = cfgext_o & ~(PCXR_SPEED_100 | PCXR_FLOWCTL_DIS | PCXR_RMII_EN);
+
+ if (phy->interface == PHY_INTERFACE_MODE_RMII)
+ cfgext |= PCXR_RMII_EN;
+ if (phy->speed == SPEED_100)
+ cfgext |= PCXR_SPEED_100;
+ if (phy->duplex)
+ cfg |= PCR_DUPLEX_FULL;
+ if (!phy->pause)
+ cfgext |= PCXR_FLOWCTL_DIS;
+
+ /* Bail out if there has nothing changed */
+ if (cfg == cfg_o && cfgext == cfgext_o)
+ return;
+
+ wrl(pep, PORT_CONFIG, cfg);
+ wrl(pep, PORT_CONFIG_EXT, cfgext);
+
+ phy_print_status(phy);
+}
+
+static int pxa168_init_phy(struct net_device *dev)
+{
+ struct pxa168_eth_private *pep = netdev_priv(dev);
+ struct ethtool_cmd cmd;
+ int err;
+
+ if (pep->phy)
+ return 0;
+
+ pep->phy = mdiobus_scan(pep->smi_bus, pep->phy_addr);
+ if (!pep->phy)
+ return -ENODEV;
+
+ err = phy_connect_direct(dev, pep->phy, pxa168_eth_adjust_link,
+ pep->phy_intf);
+ if (err)
+ return err;
+
+ err = pxa168_get_settings(dev, &cmd);
+ if (err)
+ return err;
+
+ cmd.phy_address = pep->phy_addr;
+ cmd.speed = pep->phy_speed;
+ cmd.duplex = pep->phy_duplex;
+ cmd.advertising = PHY_BASIC_FEATURES;
+ cmd.autoneg = AUTONEG_ENABLE;
+
+ if (cmd.speed != 0)
+ cmd.autoneg = AUTONEG_DISABLE;
+
+ return pxa168_set_settings(dev, &cmd);
+}
+
static int pxa168_init_hw(struct pxa168_eth_private *pep)
{
int err = 0;
@@ -1136,6 +1205,10 @@ static int pxa168_eth_open(struct net_device *dev)
struct pxa168_eth_private *pep = netdev_priv(dev);
int err;

+ err = pxa168_init_phy(dev);
+ if (err)
+ return err;
+
err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev);
if (err) {
dev_err(&dev->dev, "can't assign irq\n");
@@ -1596,9 +1669,6 @@ static int pxa168_eth_probe(struct platform_device *pdev)
goto err_free_mdio;

pxa168_init_hw(pep);
- err = ethernet_phy_setup(dev);
- if (err)
- goto err_mdiobus;
SET_NETDEV_DEV(dev, &pdev->dev);
err = register_netdev(dev);
if (err)
@@ -1629,13 +1699,13 @@ static int pxa168_eth_remove(struct platform_device *pdev)
pep->htpr, pep->htpr_dma);
pep->htpr = NULL;
}
+ if (pep->phy)
+ phy_disconnect(pep->phy);
if (pep->clk) {
clk_disable(pep->clk);
clk_put(pep->clk);
pep->clk = NULL;
}
- if (pep->phy != NULL)
- phy_detach(pep->phy);

iounmap(pep->base);
pep->base = NULL;
--
2.1.1

2014-10-21 09:00:11

by Sebastian Hesselbarth

[permalink] [raw]
Subject: [PATCH 2/9] net: pxa168_eth: Provide phy_interface mode on platform_data

The PXA168 Ethernet IP support MII and RMII connection to its PHY.
Currently, pxa168 platform_data does not provide a way to pass that
and there is one user of pxa168 platform_data (mach-mmp/gplug).
Given the pinctrl settings of gplug it uses RMII, so add and pass
a corresponding phy_interface_t.

Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: "David S. Miller" <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Eric Miao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/mach-mmp/gplugd.c | 2 ++
include/linux/pxa168_eth.h | 1 +
2 files changed, 3 insertions(+)

diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index d81b2475e67e..3b5794cd0357 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -12,6 +12,7 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
+#include <linux/phy.h>

#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@@ -158,6 +159,7 @@ struct pxa168_eth_platform_data gplugd_eth_platform_data = {
.port_number = 0,
.phy_addr = 0,
.speed = 0, /* Autonagotiation */
+ .intf = PHY_INTERFACE_MODE_RMII,
.init = gplugd_eth_init,
};

diff --git a/include/linux/pxa168_eth.h b/include/linux/pxa168_eth.h
index 18d75e795606..37c381120bc8 100644
--- a/include/linux/pxa168_eth.h
+++ b/include/linux/pxa168_eth.h
@@ -13,6 +13,7 @@ struct pxa168_eth_platform_data {
*/
int speed; /* 0, SPEED_10, SPEED_100 */
int duplex; /* DUPLEX_HALF or DUPLEX_FULL */
+ phy_interface_t intf;

/*
* Override default RX/TX queue sizes if nonzero.
--
2.1.1

2014-10-21 11:31:19

by Sergei Shtylyov

[permalink] [raw]
Subject: Re: [PATCH 8/9] ARM: berlin: Add phy-connection-type to BG2Q PHY

Hello.

On 10/21/2014 12:53 PM, Sebastian Hesselbarth wrote:

> From: Antoine Ténart <[email protected]>

> Internal FastEthernet PHY on BG2Q is connected via MII, add a
> corresponding phy-connection-type property.

> Tested-by: Antoine Ténart <[email protected]>
> Signed-off-by: Sebastian Hesselbarth <[email protected]>
> ---
> Cc: "David S. Miller" <[email protected]>
> Cc: "Antoine Ténart" <[email protected]>
> Cc: Florian Fainelli <[email protected]>
> Cc: Eric Miao <[email protected]>
> Cc: Haojian Zhuang <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> arch/arm/boot/dts/berlin2q.dtsi | 1 +
> 1 file changed, 1 insertion(+)

> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 891d56b03922..6dbc520bddc1 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -127,6 +127,7 @@
> status = "disabled";
>
> ethphy0: ethernet-phy@0 {
> + phy-connection-type = "mii";

You're adding this prop to the PHY node? That's very weird... normally,
it's a property of a MDIO bus node.

[...]

WBR, Sergei

2014-10-21 11:46:40

by Sebastian Hesselbarth

[permalink] [raw]
Subject: Re: [PATCH 8/9] ARM: berlin: Add phy-connection-type to BG2Q PHY

On 21.10.2014 13:31, Sergei Shtylyov wrote:
> Hello.
>
> On 10/21/2014 12:53 PM, Sebastian Hesselbarth wrote:
>
>> From: Antoine Ténart <[email protected]>
>
>> Internal FastEthernet PHY on BG2Q is connected via MII, add a
>> corresponding phy-connection-type property.
>
>> Tested-by: Antoine Ténart <[email protected]>
>> Signed-off-by: Sebastian Hesselbarth <[email protected]>
>> ---
>> Cc: "David S. Miller" <[email protected]>
>> Cc: "Antoine Ténart" <[email protected]>
>> Cc: Florian Fainelli <[email protected]>
>> Cc: Eric Miao <[email protected]>
>> Cc: Haojian Zhuang <[email protected]>
>> Cc: [email protected]
>> Cc: [email protected]
>> Cc: [email protected]
>> Cc: [email protected]
>> ---
>> arch/arm/boot/dts/berlin2q.dtsi | 1 +
>> 1 file changed, 1 insertion(+)
>
>> diff --git a/arch/arm/boot/dts/berlin2q.dtsi
>> b/arch/arm/boot/dts/berlin2q.dtsi
>> index 891d56b03922..6dbc520bddc1 100644
>> --- a/arch/arm/boot/dts/berlin2q.dtsi
>> +++ b/arch/arm/boot/dts/berlin2q.dtsi
>> @@ -127,6 +127,7 @@
>> status = "disabled";
>>
>> ethphy0: ethernet-phy@0 {
>> + phy-connection-type = "mii";
>
> You're adding this prop to the PHY node? That's very weird...
> normally, it's a property of a MDIO bus node.

Sergei,

How can this be a property of the MDIO bus node? Just think of an MDIO
bus with two PHYs where one is connected via GMII and the other via
RGMII? How should this work?

But you are right that the property should not be part of the PHY node
but the controller node instead. I'll rework and send an update, thanks
for the hint.

Sebastian

2014-10-21 12:08:45

by Sergei Shtylyov

[permalink] [raw]
Subject: Re: [PATCH 8/9] ARM: berlin: Add phy-connection-type to BG2Q PHY

On 10/21/2014 3:46 PM, Sebastian Hesselbarth wrote:

>>> From: Antoine Ténart <[email protected]>

>>> Internal FastEthernet PHY on BG2Q is connected via MII, add a
>>> corresponding phy-connection-type property.

>>> Tested-by: Antoine Ténart <[email protected]>
>>> Signed-off-by: Sebastian Hesselbarth <[email protected]>
>>> ---
>>> Cc: "David S. Miller" <[email protected]>
>>> Cc: "Antoine Ténart" <[email protected]>
>>> Cc: Florian Fainelli <[email protected]>
>>> Cc: Eric Miao <[email protected]>
>>> Cc: Haojian Zhuang <[email protected]>
>>> Cc: [email protected]
>>> Cc: [email protected]
>>> Cc: [email protected]
>>> Cc: [email protected]
>>> ---
>>> arch/arm/boot/dts/berlin2q.dtsi | 1 +
>>> 1 file changed, 1 insertion(+)

>>> diff --git a/arch/arm/boot/dts/berlin2q.dtsi
>>> b/arch/arm/boot/dts/berlin2q.dtsi
>>> index 891d56b03922..6dbc520bddc1 100644
>>> --- a/arch/arm/boot/dts/berlin2q.dtsi
>>> +++ b/arch/arm/boot/dts/berlin2q.dtsi
>>> @@ -127,6 +127,7 @@
>>> status = "disabled";
>>>
>>> ethphy0: ethernet-phy@0 {
>>> + phy-connection-type = "mii";

>> You're adding this prop to the PHY node? That's very weird...
>> normally, it's a property of a MDIO bus node.

> Sergei,

> How can this be a property of the MDIO bus node? Just think of an MDIO
> bus with two PHYs where one is connected via GMII and the other via
> RGMII? How should this work?

Hm, this is an unexpected case...

> But you are right that the property should not be part of the PHY node
> but the controller node instead. I'll rework and send an update, thanks
> for the hint.

Oh, not at all. :-)

> Sebastian

WBR, Sergei

2014-10-21 22:03:55

by Florian Fainelli

[permalink] [raw]
Subject: Re: [PATCH 0/9] Marvell PXA168 libphy handling and Berlin Ethernet

Hi Sebastian,

On 10/21/2014 01:53 AM, Sebastian Hesselbarth wrote:
> This patch series deals with a removing a IP feature that can be found
> on all currently supported Marvell Ethernet IP (pxa168_eth, mv643xx_eth,
> mvneta). The MAC IP allows to automatically perform PHY auto-negotiation
> without software interaction.
>
> However, this feature (a) fundamentally clashes with the way libphy works
> and (b) is unable to deal with quirky PHYs that require special treatment.
> In this series, pxa168_eth driver is rewritten to completely disable that
> feature and properly deal with libphy provided PHYs.
>
> This is the real patch set after an RFT sent earlier. Unfortunately, there
> was no testing from MMP/gplug but there was for BG2Q. However, it still
> would be great to get a Tested-by on gplug. Also, this patch set is now
> rebased on v3.18-rc1. As usual, a branch on top of v3.18-rc1 can be found at
>
> git://git.infradead.org/users/hesselba/linux-berlin.git devel/bg2-bg2cd-eth-v1
>
> Patches 1-5 should go through David's net tree, I'll pick up the DT patches
> 6-9.
>
> Compared to the RFT, there have been some changes:
> - added phy-connection-type property to BG2Q PHY DT node
> - bail out from pxa168_eth_adjust_link when there is no change in
> PHY parameters. Also, add a call to phy_print_status.
>
> Patch 1 adds support for Marvell 88E3016 FastEthernet PHY that is also
> integrated in Marvell Berlin BG2/BG2CD SoCs.
>
> Patch 2 allows to pass phy_interface_t on pxa168_eth platform_data that
> is only used by mach-mmp/gplug. From the board setup, I guessed gplug's
> PHY is connected via RMII. The patch still isn't even compile tested.
>
> Patches 3-5 prepare proper libphy handling and finally remove all in-driver
> PHY mangling related to the feature explained above.
>
> Patches 6-9 add corresponding ethernet DT nodes to BG2, BG2CD, add a
> phy-connection-type property to BG2Q and enable ethernet on BG2-based Sony
> NSZ-GS7. I have tested all this on GS7 successfully with ip=dhcp on 100M FD.

Besides the misplacement of the 'phy-connection-type' as reported by
Sergei, this looks good to me:

Reviewed-by: Florian Fainelli <[email protected]>

Thanks!

>
> Antoine Ténart (1):
> ARM: berlin: Add phy-connection-type to BG2Q PHY
>
> Sebastian Hesselbarth (8):
> phy: marvell: Add support for 88E3016 FastEthernet PHY
> net: pxa168_eth: Provide phy_interface mode on platform_data
> net: pxa168_eth: Prepare proper libphy handling
> net: pxa168_eth: Remove HW auto-negotiaion
> net: pxa168_eth: Remove in-driver PHY mangling
> ARM: berlin: Add BG2 ethernet DT nodes
> ARM: berlin: Add BG2CD ethernet DT nodes
> ARM: berlin: Enable ethernet on Sony NSZ-GS7
>
> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 2 +
> arch/arm/boot/dts/berlin2.dtsi | 36 +++++
> arch/arm/boot/dts/berlin2cd.dtsi | 36 +++++
> arch/arm/boot/dts/berlin2q.dtsi | 1 +
> arch/arm/mach-mmp/gplugd.c | 2 +
> drivers/net/ethernet/marvell/pxa168_eth.c | 248 ++++++++++++-----------------
> drivers/net/phy/marvell.c | 46 ++++++
> include/linux/marvell_phy.h | 1 +
> include/linux/pxa168_eth.h | 1 +
> 9 files changed, 225 insertions(+), 148 deletions(-)
>
> ---
> Cc: "David S. Miller" <[email protected]>
> Cc: "Antoine Ténart" <[email protected]>
> Cc: Florian Fainelli <[email protected]>
> Cc: Eric Miao <[email protected]>
> Cc: Haojian Zhuang <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
>