This series adds support for the MediaTek SCPSYS unit.
The SCPSYS unit handles several power management related tasks such
as thermal measurement, DVFS, interrupt filter and low level sleep
control.
The initial support only contains the generic power domain handling.
This is needed to turn on power to the different power domains.
The driver is quite straight forward now. Due to the lack of a better
place I have put it to drivers/soc/mediatek. As the SCPSYS unit has
several other tasks that also do not fit into some specific subsystem
this probably is a good place for this driver.
Please review, any input welcome.
Sascha
changes since v1:
- make MFG_ASYNC a subdomain of MFG_2D and MFG_2D a subdomain of MFG
- Add (now hopefully properly) infracfg register handling again
- Add clock handling
- Fix on/off mixup in error message
- Make readonly data const
- Fix MODULE_LICENSE to GPL v2
changes since RFC:
- add a commit log to driver patch
- drop manipulating infracfg registers for now, can be added (properly)
later
- Add warning messages when errors occur
- add NULL pointer check for kmalloc
- Enable all power domains when PM is disabled to allow consumers to work
This adds documentation for the MediaTek SCPSYS unit found in MT8173 SoCs.
Signed-off-by: Sascha Hauer <[email protected]>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
new file mode 100644
index 0000000..4764a03
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -0,0 +1,32 @@
+MediaTek SCPSYS
+===============
+
+The System Control Processor System (SCPSYS) has several power management
+related tasks in the system. The tasks include thermal measurement, dynamic
+voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
+The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power
+domain control.
+
+The driver implements the Generic PM domain bindings described in
+power/power_domain.txt. It provides the power domains defined in
+include/dt-bindings/power/mt8173-power.h.
+
+Required properties:
+- compatible: Must be "mediatek,mt8173-scpsys"
+- #power-domain-cells: Must be 1
+- reg: Address range of the SCPSYS unit
+
+Example:
+
+ scpsys: scpsys@10006000 {
+ #power-domain-cells = <1>;
+ compatible = "mediatek,mt8173-scpsys";
+ reg = <0 0x10006000 0 0x1000>;
+ };
+
+Example consumer:
+
+ afe: mt8173-afe-pcm@11220000 {
+ compatible = "mediatek,mt8173-afe-pcm";
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
+ };
--
2.1.4
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.
For now this driver only adds power domain support, the more
advanced features are not yet supported. The driver implements
the generic PM domain device tree bindings, the first user will
most likely be the Mediatek AFE audio driver.
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/soc/mediatek/Kconfig | 6 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-scpsys.c | 345 +++++++++++++++++++++++++++++++
include/dt-bindings/power/mt8173-power.h | 15 ++
4 files changed, 367 insertions(+)
create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
create mode 100644 include/dt-bindings/power/mt8173-power.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index bcdb22d..1d34819 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -9,3 +9,9 @@ config MTK_PMIC_WRAP
Say yes here to add support for MediaTek PMIC Wrapper found
on different MediaTek SoCs. The PMIC wrapper is a proprietary
hardware to connect the PMIC.
+
+config MTK_SCPSYS
+ tristate "MediaTek SCPSYS Support"
+ help
+ Say yes here to add support for the MediaTek SCPSYS power domain
+ driver.
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index ecaf4de..ce88693 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
+obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
new file mode 100644
index 0000000..a72ac51
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2015 Pengutronix, Sascha Hauer <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/pm_domain.h>
+#include <linux/delay.h>
+#include <dt-bindings/power/mt8173-power.h>
+#include <linux/mfd/syscon.h>
+
+#define SPM_VDE_PWR_CON 0x0210
+#define SPM_MFG_PWR_CON 0x0214
+#define SPM_VEN_PWR_CON 0x0230
+#define SPM_ISP_PWR_CON 0x0238
+#define SPM_DIS_PWR_CON 0x023c
+#define SPM_VEN2_PWR_CON 0x0298
+#define SPM_AUDIO_PWR_CON 0x029c
+#define SPM_MFG_2D_PWR_CON 0x02c0
+#define SPM_MFG_ASYNC_PWR_CON 0x02c4
+#define SPM_USB_PWR_CON 0x02cc
+#define SPM_PWR_STATUS 0x060c
+#define SPM_PWR_STATUS_2ND 0x0610
+
+#define PWR_RST_B_BIT BIT(0)
+#define PWR_ISO_BIT BIT(1)
+#define PWR_ON_BIT BIT(2)
+#define PWR_ON_2ND_BIT BIT(3)
+#define PWR_CLK_DIS_BIT BIT(4)
+
+#define DIS_PWR_STA_MASK BIT(3)
+#define MFG_PWR_STA_MASK BIT(4)
+#define ISP_PWR_STA_MASK BIT(5)
+#define VDE_PWR_STA_MASK BIT(7)
+#define VEN2_PWR_STA_MASK BIT(20)
+#define VEN_PWR_STA_MASK BIT(21)
+#define MFG_2D_PWR_STA_MASK BIT(22)
+#define MFG_ASYNC_PWR_STA_MASK BIT(23)
+#define AUDIO_PWR_STA_MASK BIT(24)
+#define USB_PWR_STA_MASK BIT(25)
+
+struct scp_domain_data {
+ const char *name;
+ u32 sta_mask;
+ int ctl_offs;
+ u32 sram_pdn_bits;
+ u32 sram_pdn_ack_bits;
+ int id;
+};
+
+static struct scp_domain_data scp_domain_data[] = {
+ {
+ .id = MT8173_POWER_DOMAIN_VDE,
+ .name = "vde",
+ .sta_mask = VDE_PWR_STA_MASK,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ }, {
+ .id = MT8173_POWER_DOMAIN_MFG,
+ .name = "mfg",
+ .sta_mask = MFG_PWR_STA_MASK,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(13, 8),
+ .sram_pdn_ack_bits = GENMASK(21, 16),
+ }, {
+ .id = MT8173_POWER_DOMAIN_VEN,
+ .name = "ven",
+ .sta_mask = VEN_PWR_STA_MASK,
+ .ctl_offs = SPM_VEN_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ }, {
+ .id = MT8173_POWER_DOMAIN_ISP,
+ .name = "isp",
+ .sta_mask = ISP_PWR_STA_MASK,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ }, {
+ .id = MT8173_POWER_DOMAIN_DIS,
+ .name = "dis",
+ .sta_mask = DIS_PWR_STA_MASK,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ }, {
+ .id = MT8173_POWER_DOMAIN_VEN2,
+ .name = "ven2",
+ .sta_mask = VEN2_PWR_STA_MASK,
+ .ctl_offs = SPM_VEN2_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ }, {
+ .id = MT8173_POWER_DOMAIN_AUDIO,
+ .name = "audio",
+ .sta_mask = AUDIO_PWR_STA_MASK,
+ .ctl_offs = SPM_AUDIO_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ }, {
+ .id = MT8173_POWER_DOMAIN_MFG_2D,
+ .name = "mfg_2d",
+ .sta_mask = MFG_2D_PWR_STA_MASK,
+ .ctl_offs = SPM_MFG_2D_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ }, {
+ .id = MT8173_POWER_DOMAIN_MFG_ASYNC,
+ .name = "mfg_async",
+ .sta_mask = MFG_ASYNC_PWR_STA_MASK,
+ .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = 0,
+ }, {
+ .id = MT8173_POWER_DOMAIN_USB,
+ .name = "usb",
+ .sta_mask = USB_PWR_STA_MASK,
+ .ctl_offs = SPM_USB_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+};
+
+#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
+
+struct scp;
+
+struct scp_domain {
+ struct generic_pm_domain pmd;
+ struct scp_domain_data *data;
+ struct scp *scp;
+};
+
+struct scp {
+ struct scp_domain domains[NUM_DOMAINS];
+ struct generic_pm_domain *pmd[NUM_DOMAINS];
+ struct genpd_onecell_data pd_data;
+ struct device *dev;
+ void __iomem *base;
+};
+
+static int scpsys_power_on(struct generic_pm_domain *genpd)
+{
+ struct scp_domain *scpd = container_of(genpd, struct scp_domain, pmd);
+ struct scp *scp = scpd->scp;
+ struct scp_domain_data *data = scpd->data;
+ unsigned long expired;
+ void __iomem *ctl_addr = scpd->scp->base + data->ctl_offs;
+ u32 sram_pdn_ack = data->sram_pdn_ack_bits;
+ u32 val;
+ int ret;
+
+ val = readl(ctl_addr);
+ val |= PWR_ON_BIT;
+ writel(val, ctl_addr);
+ val |= PWR_ON_2ND_BIT;
+ writel(val, ctl_addr);
+
+ /* wait until PWR_ACK = 1 */
+ expired = jiffies + HZ;
+ while (!(readl(scp->base + SPM_PWR_STATUS) & data->sta_mask) ||
+ !(readl(scp->base + SPM_PWR_STATUS_2ND) & data->sta_mask)) {
+ cpu_relax();
+ if (time_after(jiffies, expired)) {
+ ret = -EIO;
+ goto out;
+ }
+ }
+
+ val &= ~PWR_CLK_DIS_BIT;
+ writel(val, ctl_addr);
+
+ val &= ~PWR_ISO_BIT;
+ writel(val, ctl_addr);
+
+ val |= PWR_RST_B_BIT;
+ writel(val, ctl_addr);
+
+ val &= ~data->sram_pdn_bits;
+ writel(val, ctl_addr);
+
+ /* wait until SRAM_PDN_ACK all 0 */
+ expired = jiffies + HZ;
+ while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
+ cpu_relax();
+ if (time_after(jiffies, expired)) {
+ ret = -EIO;
+ goto out;
+ }
+ }
+
+ return 0;
+out:
+ dev_err(scp->dev, "Failed to power on domain %s\n", scpd->data->name);
+
+ return ret;
+}
+
+static int scpsys_power_off(struct generic_pm_domain *genpd)
+{
+ struct scp_domain *scpd = container_of(genpd, struct scp_domain, pmd);
+ struct scp *scp = scpd->scp;
+ struct scp_domain_data *data = scpd->data;
+ unsigned long expired;
+ void __iomem *ctl_addr = scpd->scp->base + data->ctl_offs;
+ u32 sram_pdn_ack = data->sram_pdn_ack_bits;
+ u32 val;
+ int ret;
+
+ val = readl(ctl_addr);
+ val |= data->sram_pdn_bits;
+ writel(val, ctl_addr);
+
+ /* wait until SRAM_PDN_ACK all 1 */
+ expired = jiffies + HZ;
+ while ((readl(ctl_addr) & sram_pdn_ack) != sram_pdn_ack) {
+ cpu_relax();
+ if (time_after(jiffies, expired)) {
+ ret = -EIO;
+ goto out;
+ }
+ }
+
+ val |= PWR_ISO_BIT;
+ writel(val, ctl_addr);
+
+ val &= ~PWR_RST_B_BIT;
+ writel(val, ctl_addr);
+
+ val |= PWR_CLK_DIS_BIT;
+ writel(val, ctl_addr);
+
+ val &= ~PWR_ON_BIT;
+ writel(val, ctl_addr);
+
+ val &= ~PWR_ON_2ND_BIT;
+ writel(val, ctl_addr);
+
+ /* wait until PWR_ACK = 0 */
+ expired = jiffies + HZ;
+ while ((readl(scp->base + SPM_PWR_STATUS) & data->sta_mask) ||
+ (readl(scp->base + SPM_PWR_STATUS_2ND) & data->sta_mask)) {
+ cpu_relax();
+ if (time_after(jiffies, expired)) {
+ ret = -EIO;
+ goto out;
+ }
+ }
+
+ return 0;
+
+out:
+ dev_err(scp->dev, "Failed to power on domain %s\n", scpd->data->name);
+
+ return ret;
+}
+
+static int scpsys_probe(struct platform_device *pdev)
+{
+ struct genpd_onecell_data *pd_data;
+ struct resource *res;
+ int i;
+ struct scp *scp;
+
+ scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
+ if (!scp)
+ return -ENOMEM;
+
+ scp->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ scp->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(scp->base))
+ return PTR_ERR(scp->base);
+
+ pd_data = &scp->pd_data;
+
+ pd_data->domains = scp->pmd;
+ pd_data->num_domains = NUM_DOMAINS;
+
+ for (i = 0; i < NUM_DOMAINS; i++) {
+ struct scp_domain *scpd = &scp->domains[i];
+ struct generic_pm_domain *pmd = &scpd->pmd;
+
+ scp->pmd[i] = pmd;
+ scpd->data = &scp_domain_data[i];
+ scpd->scp = scp;
+
+ pmd->name = scp_domain_data[i].name;
+ pmd->power_off = scpsys_power_off;
+ pmd->power_on = scpsys_power_on;
+ pmd->power_off_latency_ns = 20000;
+ pmd->power_on_latency_ns = 20000;
+
+ pd_data->domains[i] = pmd;
+ pm_genpd_init(pmd, NULL, 1);
+
+ /*
+ * If PM is disabled turn on all domains by default so that
+ * consumers can work.
+ */
+ if (!IS_ENABLED(CONFIG_PM))
+ pmd->power_on(pmd);
+ }
+
+ return of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
+}
+
+static struct of_device_id of_scpsys_match_tbl[] = {
+ {
+ .compatible = "mediatek,mt8173-scpsys",
+ }, {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(of, of_scpsys_match_tbl);
+
+static struct platform_driver scpsys_drv = {
+ .driver = {
+ .name = "mtk-scpsys",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(of_scpsys_match_tbl),
+ },
+ .probe = scpsys_probe,
+};
+
+module_platform_driver(scpsys_drv);
+
+MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+MODULE_DESCRIPTION("MediaTek MT8173 scpsys driver");
+MODULE_LICENSE("GPL");
diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h
new file mode 100644
index 0000000..88715f2
--- /dev/null
+++ b/include/dt-bindings/power/mt8173-power.h
@@ -0,0 +1,15 @@
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8173_POWER_DOMAIN_VDE 0
+#define MT8173_POWER_DOMAIN_MFG 1
+#define MT8173_POWER_DOMAIN_VEN 2
+#define MT8173_POWER_DOMAIN_ISP 3
+#define MT8173_POWER_DOMAIN_DIS 4
+#define MT8173_POWER_DOMAIN_VEN2 5
+#define MT8173_POWER_DOMAIN_AUDIO 6
+#define MT8173_POWER_DOMAIN_MFG_2D 7
+#define MT8173_POWER_DOMAIN_MFG_ASYNC 8
+#define MT8173_POWER_DOMAIN_USB 9
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
--
2.1.4
Enable support for generic power domains in the config.
Signed-off-by: Sascha Hauer <[email protected]>
---
arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7796af4..ba8469c 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -185,6 +185,7 @@ config ARCH_MEDIATEK
bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
select ARM_GIC
select PINCTRL
+ select PM_GENERIC_DOMAINS if PM
help
Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
--
2.1.4
This adds the SCPSYS device node to the MT8173 dtsi file.
Signed-off-by: Sascha Hauer <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 924fdb6..3c569b5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -125,6 +125,18 @@
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
};
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt8173-scpsys";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "vdec", "mfg", "venc", "disp", "ven2";
+ };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
--
2.1.4
On Monday, May 11, 2015 03:11:18 PM Sascha Hauer wrote:
> This series adds support for the MediaTek SCPSYS unit.
>
> The SCPSYS unit handles several power management related tasks such
> as thermal measurement, DVFS, interrupt filter and low level sleep
> control.
>
> The initial support only contains the generic power domain handling.
> This is needed to turn on power to the different power domains.
>
> The driver is quite straight forward now. Due to the lack of a better
> place I have put it to drivers/soc/mediatek. As the SCPSYS unit has
> several other tasks that also do not fit into some specific subsystem
> this probably is a good place for this driver.
>
> Please review, any input welcome.
>
> Sascha
>
> changes since v1:
> - make MFG_ASYNC a subdomain of MFG_2D and MFG_2D a subdomain of MFG
> - Add (now hopefully properly) infracfg register handling again
> - Add clock handling
> - Fix on/off mixup in error message
> - Make readonly data const
> - Fix MODULE_LICENSE to GPL v2
I can't find this changes. It looks like you send the wrong patches.
Please resend.
Cheers,
Matthias
On Mon, May 11, 2015 at 06:05:20PM +0200, Matthias Brugger_0 wrote:
> On Monday, May 11, 2015 03:11:18 PM Sascha Hauer wrote:
> > This series adds support for the MediaTek SCPSYS unit.
> >
> > The SCPSYS unit handles several power management related tasks such
> > as thermal measurement, DVFS, interrupt filter and low level sleep
> > control.
> >
> > The initial support only contains the generic power domain handling.
> > This is needed to turn on power to the different power domains.
> >
> > The driver is quite straight forward now. Due to the lack of a better
> > place I have put it to drivers/soc/mediatek. As the SCPSYS unit has
> > several other tasks that also do not fit into some specific subsystem
> > this probably is a good place for this driver.
> >
> > Please review, any input welcome.
> >
> > Sascha
> >
> > changes since v1:
> > - make MFG_ASYNC a subdomain of MFG_2D and MFG_2D a subdomain of MFG
> > - Add (now hopefully properly) infracfg register handling again
> > - Add clock handling
> > - Fix on/off mixup in error message
> > - Make readonly data const
> > - Fix MODULE_LICENSE to GPL v2
>
> I can't find this changes. It looks like you send the wrong patches.
> Please resend.
Damn, I just proved that changelogs are useful ;)
I have just resent this series.
Sascha
--
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Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Mon, May 11, 2015 at 9:11 PM, Sascha Hauer <[email protected]> wrote:
> This adds the SCPSYS device node to the MT8173 dtsi file.
>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 924fdb6..3c569b5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -125,6 +125,18 @@
> <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + scpsys: scpsys@10006000 {
> + compatible = "mediatek,mt8173-scpsys";
> + #power-domain-cells = <1>;
> + reg = <0 0x10006000 0 0x1000>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&topckgen CLK_TOP_MFG_SEL>,
> + <&topckgen CLK_TOP_VENC_SEL>,
> + <&topckgen CLK_TOP_MM_SEL>,
> + <&topckgen CLK_TOP_VENC_LT_SEL>;
> + clock-names = "vdec", "mfg", "venc", "disp", "ven2";
(1) I think people like to align multi-line dts field values, so there
should be one more ' ' before each <&topckgen ...>.
(2) it is a bit awkward that these names do not match their clock
names. This seems more straightforward:
clock-names = "vdec", "mfg", "venc", "mm", "venc_lt";
(3) the scpsys binding patch does not list the clock fields.
(4) I don't think a patch with these CLK_TOP_* has been sent to the
list for review yet.
Thanks,
-Dan
> + };
> +
> sysirq: intpol-controller@10200620 {
> compatible = "mediatek,mt8173-sysirq",
> "mediatek,mt6577-sysirq";
> --
> 2.1.4
>
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Sascha Hauer <[email protected]> writes:
> This adds a power domain driver for the Mediatek SCPSYS unit.
>
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. The tasks include thermal
> measurement, dynamic voltage frequency scaling (DVFS), interrupt
> filter and lowlevel sleep control. The System Power Manager (SPM)
> inside the SCPSYS is for the MTCMOS power domain control.
>
> For now this driver only adds power domain support, the more
> advanced features are not yet supported. The driver implements
> the generic PM domain device tree bindings, the first user will
> most likely be the Mediatek AFE audio driver.
>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> drivers/soc/mediatek/Kconfig | 6 +
> drivers/soc/mediatek/Makefile | 1 +
> drivers/soc/mediatek/mtk-scpsys.c | 345 +++++++++++++++++++++++++++++++
> include/dt-bindings/power/mt8173-power.h | 15 ++
> 4 files changed, 367 insertions(+)
> create mode 100644 drivers/soc/mediatek/mtk-scpsys.c
> create mode 100644 include/dt-bindings/power/mt8173-power.h
>
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index bcdb22d..1d34819 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -9,3 +9,9 @@ config MTK_PMIC_WRAP
> Say yes here to add support for MediaTek PMIC Wrapper found
> on different MediaTek SoCs. The PMIC wrapper is a proprietary
> hardware to connect the PMIC.
> +
> +config MTK_SCPSYS
> + tristate "MediaTek SCPSYS Support"
depends on ARCH_MEDIATEK ?
> + help
> + Say yes here to add support for the MediaTek SCPSYS power domain
> + driver.
[...]
> +static int scpsys_probe(struct platform_device *pdev)
> +{
> + struct genpd_onecell_data *pd_data;
> + struct resource *res;
> + int i;
> + struct scp *scp;
> +
> + scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> + if (!scp)
> + return -ENOMEM;
> +
> + scp->dev = &pdev->dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + scp->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(scp->base))
> + return PTR_ERR(scp->base);
> +
> + pd_data = &scp->pd_data;
> +
> + pd_data->domains = scp->pmd;
> + pd_data->num_domains = NUM_DOMAINS;
> +
> + for (i = 0; i < NUM_DOMAINS; i++) {
> + struct scp_domain *scpd = &scp->domains[i];
> + struct generic_pm_domain *pmd = &scpd->pmd;
> +
> + scp->pmd[i] = pmd;
> + scpd->data = &scp_domain_data[i];
> + scpd->scp = scp;
> +
> + pmd->name = scp_domain_data[i].name;
> + pmd->power_off = scpsys_power_off;
> + pmd->power_on = scpsys_power_on;
> + pmd->power_off_latency_ns = 20000;
> + pmd->power_on_latency_ns = 20000;
I think I mentioned this before... are these numbers really identical
for all domains? I suggest you make these each a field in the domain
data so they can be different for each domain, and eventually come from
DT data.
> + pd_data->domains[i] = pmd;
> + pm_genpd_init(pmd, NULL, 1);
> +
> + /*
> + * If PM is disabled turn on all domains by default so that
> + * consumers can work.
> + */
> + if (!IS_ENABLED(CONFIG_PM))
> + pmd->power_on(pmd);
> + }
> +
> + return of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
> +}
Kevin