aarch64 doesn't have native store immediate instruction, such operation
has to be implemented by the below instruction sequence:
Load immediate to register
Store register
Signed-off-by: Yang Shi <[email protected]>
CC: Zi Shen Lim <[email protected]>
CC: Xi Wang <[email protected]>
---
Thsi patch might be buried by the storm of xadd discussion, however, it is
absolutely irrelevent to xadd, so resend the patch itself.
arch/arm64/net/bpf_jit_comp.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 6809647..49c1f1b 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -563,7 +563,25 @@ emit_cond_jmp:
case BPF_ST | BPF_MEM | BPF_H:
case BPF_ST | BPF_MEM | BPF_B:
case BPF_ST | BPF_MEM | BPF_DW:
- goto notyet;
+ /* Load imm to a register then store it */
+ ctx->tmp_used = 1;
+ emit_a64_mov_i(1, tmp2, off, ctx);
+ emit_a64_mov_i(1, tmp, imm, ctx);
+ switch (BPF_SIZE(code)) {
+ case BPF_W:
+ emit(A64_STR32(tmp, dst, tmp2), ctx);
+ break;
+ case BPF_H:
+ emit(A64_STRH(tmp, dst, tmp2), ctx);
+ break;
+ case BPF_B:
+ emit(A64_STRB(tmp, dst, tmp2), ctx);
+ break;
+ case BPF_DW:
+ emit(A64_STR64(tmp, dst, tmp2), ctx);
+ break;
+ }
+ break;
/* STX: *(size *)(dst + off) = src */
case BPF_STX | BPF_MEM | BPF_W:
--
2.0.2
On 11/30/2015 2:24 PM, Yang Shi wrote:
> aarch64 doesn't have native store immediate instruction, such operation
> has to be implemented by the below instruction sequence:
>
> Load immediate to register
> Store register
>
> Signed-off-by: Yang Shi <[email protected]>
> CC: Zi Shen Lim <[email protected]>
Had email exchange offline with Zi Shen Lim since he is traveling and
cannot send text-only mail, quoted below for his reply:
"I've given reviewed-by in response to original posting. Unless
something has changed, feel free to add it."
Since there is nothing changed, added his reviewed-by.
Reviewed-by: Zi Shen Lim <[email protected]>
Thanks,
Yang
> CC: Xi Wang <[email protected]>
> ---
> Thsi patch might be buried by the storm of xadd discussion, however, it is
> absolutely irrelevent to xadd, so resend the patch itself.
>
> arch/arm64/net/bpf_jit_comp.c | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
> index 6809647..49c1f1b 100644
> --- a/arch/arm64/net/bpf_jit_comp.c
> +++ b/arch/arm64/net/bpf_jit_comp.c
> @@ -563,7 +563,25 @@ emit_cond_jmp:
> case BPF_ST | BPF_MEM | BPF_H:
> case BPF_ST | BPF_MEM | BPF_B:
> case BPF_ST | BPF_MEM | BPF_DW:
> - goto notyet;
> + /* Load imm to a register then store it */
> + ctx->tmp_used = 1;
> + emit_a64_mov_i(1, tmp2, off, ctx);
> + emit_a64_mov_i(1, tmp, imm, ctx);
> + switch (BPF_SIZE(code)) {
> + case BPF_W:
> + emit(A64_STR32(tmp, dst, tmp2), ctx);
> + break;
> + case BPF_H:
> + emit(A64_STRH(tmp, dst, tmp2), ctx);
> + break;
> + case BPF_B:
> + emit(A64_STRB(tmp, dst, tmp2), ctx);
> + break;
> + case BPF_DW:
> + emit(A64_STR64(tmp, dst, tmp2), ctx);
> + break;
> + }
> + break;
>
> /* STX: *(size *)(dst + off) = src */
> case BPF_STX | BPF_MEM | BPF_W:
>
On Tue, Dec 01, 2015 at 02:20:40PM -0800, Shi, Yang wrote:
> On 11/30/2015 2:24 PM, Yang Shi wrote:
> >aarch64 doesn't have native store immediate instruction, such operation
> >has to be implemented by the below instruction sequence:
> >
> >Load immediate to register
> >Store register
> >
> >Signed-off-by: Yang Shi <[email protected]>
> >CC: Zi Shen Lim <[email protected]>
>
> Had email exchange offline with Zi Shen Lim since he is traveling and cannot
> send text-only mail, quoted below for his reply:
>
> "I've given reviewed-by in response to original posting. Unless something
> has changed, feel free to add it."
>
> Since there is nothing changed, added his reviewed-by.
>
> Reviewed-by: Zi Shen Lim <[email protected]>
I assume David will take this via netdev.
Will
From: Will Deacon <[email protected]>
Date: Wed, 2 Dec 2015 09:15:18 +0000
> On Tue, Dec 01, 2015 at 02:20:40PM -0800, Shi, Yang wrote:
>> On 11/30/2015 2:24 PM, Yang Shi wrote:
>> >aarch64 doesn't have native store immediate instruction, such operation
>> >has to be implemented by the below instruction sequence:
>> >
>> >Load immediate to register
>> >Store register
>> >
>> >Signed-off-by: Yang Shi <[email protected]>
>> >CC: Zi Shen Lim <[email protected]>
>>
>> Had email exchange offline with Zi Shen Lim since he is traveling and cannot
>> send text-only mail, quoted below for his reply:
>>
>> "I've given reviewed-by in response to original posting. Unless something
>> has changed, feel free to add it."
>>
>> Since there is nothing changed, added his reviewed-by.
>>
>> Reviewed-by: Zi Shen Lim <[email protected]>
>
> I assume David will take this via netdev.
Yes, I will, thanks.
From: Yang Shi <[email protected]>
Date: Mon, 30 Nov 2015 14:24:07 -0800
> aarch64 doesn't have native store immediate instruction, such operation
> has to be implemented by the below instruction sequence:
>
> Load immediate to register
> Store register
>
> Signed-off-by: Yang Shi <[email protected]>
Applied, thanks.