This patchs adds a new sample record type called
PERF_SAMPLE_SKID_IP. The goal is to record the
unmodified interrupted instruction pointer (IP) as
seen by the kernel and reflected in the machine state.
On some architectures, it is possible to avoid the IP skid using
hardware support. For instance, on Intel x86, the use of PEBS helps
eliminate the skid on Haswell and later processors. On older Intel
processor, software, i.e., the kernel, may succeed in eliminating
the skid.
Without this patch, on Haswell processors, if you set:
- attr.precise = 0, then you get the skid IP
- attr.precise = 1, then you get the skid PEBS ip (off-by-1)
- attr.precise = 2, then you get the skidless PEBS ip
The IP is captured when the event has PERF_SAMPLE_IP set in sample_type.
However, there are certain measurements where you need to have BOTH
the skidless IP and the skid IP. For instance, when studying branches,
the skid IP usually points to the target of the branch while the skidless
IP points to the branch instruction itself. Today, it is not possible to retrieve
both at the same time. This patch makes this possible by specifying
PERF_SAMPLE_IP|PERF_SAMPLE_SKID_IP.
As an example, consider the following code snipet:
37.51 42c2ed je 42c2f3
42c2ef add $0x1,%rdx
42c2f3 sub $0x1,%rax
When using PEBS (precise=2) and sampling on BR_INST_RETIRED.CONDITIONAL,
the IP always points to 0x42c2ed. With precise=1, the IP would point to
0x42c2f3. It is interesting to collect both IPs in a single run to determine
how often the conditional branch is taken vs. non-taken.
Understanding the skid is also interesting for other precise events.
In V2, we rebased to 10d94ff4d558 (v4.14-rc7).
In V3, code is rebased to 4.14-rc8, LKML comments have been integrated.
The new way to specify skid ip is per event:
$ perf record -e cpu/event=0xc5,skid-ip=1/ ....
In V4, we fix document of the ski-ip event option and move a session.c
change to the correct patch as per Jiri's remark.
Stephane Eranian (5):
perf/core: add PERF_RECORD_SAMPLE_SKID_IP record type
perf/x86: add PERF_SAMPLE_SKID_IP support for X86 PEBS
perf/tools: add support for PERF_SAMPLE_SKID_IP
perf/record: add documentation for using PERF_SAMPLE_SKID_IP
perf/script: add support for PERF_SAMPLE_SKID_IP
arch/x86/events/intel/ds.c | 7 +++++++
include/linux/perf_event.h | 2 ++
include/uapi/linux/perf_event.h | 4 +++-
kernel/events/core.c | 14 ++++++++++++++
tools/include/uapi/linux/perf_event.h | 4 +++-
tools/perf/Documentation/perf-record.txt | 8 ++++++++
tools/perf/Documentation/perf-script.txt | 2 +-
tools/perf/builtin-script.c | 10 ++++++++--
tools/perf/util/event.h | 1 +
tools/perf/util/evsel.c | 11 +++++++++++
tools/perf/util/evsel.h | 2 ++
tools/perf/util/parse-events.c | 7 +++++++
tools/perf/util/parse-events.h | 1 +
tools/perf/util/parse-events.l | 1 +
tools/perf/util/session.c | 3 +++
15 files changed, 72 insertions(+), 5 deletions(-)
--
2.7.4
From 1583495184409837486@xxx Wed Nov 08 10:58:07 +0000 2017
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This atch adds support for SKID_IP to Intel x86 processors in PEBS
mode.
Signed-off-by: Stephane Eranian <[email protected]>
---
arch/x86/events/intel/ds.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 3674a4b6f8bd..dd248ceda452 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1190,6 +1190,13 @@ static void setup_pebs_sample_data(struct perf_event *event,
x86_pmu.intel_cap.pebs_format >= 1)
data->addr = pebs->dla;
+ /*
+ * unmodified, skid IP which is guaranteed to be the next
+ * dyanmic instruction
+ */
+ if (sample_type & PERF_SAMPLE_SKID_IP)
+ data->skid_ip = pebs->ip;
+
if (x86_pmu.intel_cap.pebs_format >= 2) {
/* Only set the TSX weight when no memory weight. */
if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
--
2.7.4
From 1591089163189718077@xxx Wed Jan 31 06:41:10 +0000 2018
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