2019-01-09 15:27:31

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 00/10] Add support for DRM bridge and additional pixel formats

This patchset improves the use of eLCDIF block on iMX 8 SoCs (like 8MQ, 8MM
and 8QXP):

1. Add support for drm_bridge
On 8MQ and 8MM, the LCDIF block is not directly connected to a parallel
display connector, where an LCD panel can be attached, but instead it is
connected to DSI controller. Since this DSI stands between the display
controller (eLCDIF) and the physical connector, the DSI can be implemented
as a DRM bridge. So, in order to be able to connect the mxsfb driver to
the DSI driver, the support for a drm_bridge was needed in mxsfb DRM
driver (the actual driver for the eLCDIF block).

2. Add support for additional pixel formats
Some of the pixel formats needed by Android were not implemented in this
driver, but they were actually supported. So, add support for them.

3. Few minor features and bug-fixing
The addition of max-res DT property was actually needed in order to limit
the bandwidth usage of the eLCDIF block. This is need on systems where
multiple display controllers are presend and the memory bandwidth is not
enough to handle all of them at maximum capacity (like it is the case on
8MQ, where there are two display controllers: DCSS and eLCDIF).
The rest of the patches are bug-fixes.


Mirela Rabulea (2):
drm/mxsfb: Add support for new pixel formats in eLCDIF
drm/mxsfb: Signal mode changed when bpp changed

Robert Chiras (8):
drm/mxsfb: Update mxsfb to support a bridge
dt-bindings: display: Add max-res property for mxsfb
drm/mxsfb: Add max-res property for MXSFB
drm/mxsfb: Update mxsfb with additional pixel formats
drm/mxsfb: Fix the vblank events
drm/mxsfb: Update mxsfb to support LCD reset
drm/mxsfb: Improve the axi clock usage
drm/mxsfb: Clear OUTSTANDING_REQS bits

.../devicetree/bindings/display/mxsfb.txt | 6 +
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 215 ++++++++++++++++++---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 187 ++++++++++++++----
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 11 +-
drivers/gpu/drm/mxsfb/mxsfb_out.c | 26 +--
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 112 +++++++----
6 files changed, 433 insertions(+), 124 deletions(-)

--
2.7.4



2019-01-09 14:15:25

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 02/10] dt-bindings: display: Add max-res property for mxsfb

Add new optional property 'max-res', to limit the maximum supported
resolution by the MXSFB_DRM driver.

Signed-off-by: Robert Chiras <[email protected]>
---
Documentation/devicetree/bindings/display/mxsfb.txt | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt b/Documentation/devicetree/bindings/display/mxsfb.txt
index 472e1ea..55e22ed 100644
--- a/Documentation/devicetree/bindings/display/mxsfb.txt
+++ b/Documentation/devicetree/bindings/display/mxsfb.txt
@@ -17,6 +17,12 @@ Required properties:
Required sub-nodes:
- port: The connection to an encoder chip.

+Optional properties:
+- max-res: an array with a maximum of two integers, representing the
+ maximum supported resolution, in the form of
+ <maxX>, <maxY>; if one of the item is <0>, the default
+ driver-defined maximum resolution for that axis is used
+
Example:

lcdif1: display-controller@2220000 {
--
2.7.4


2019-01-09 14:15:34

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 09/10] drm/mxsfb: Improve the axi clock usage

Currently, the enable of the axi clock return status is ignored, causing
issues when the enable fails then we try to disable it. Therefore, it is
better to check the return status and disable it only when enable
succeeded.
Also, remove the helper functions around clk_axi, since we can directly
use the clk API function for enable/disable the clock. Those functions
are already checking for NULL clk and returning 0 if that's the case.

Signed-off-by: Robert Chiras <[email protected]>
Acked-by: Leonard Crestez <[email protected]>
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8 ++++----
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 32 +++++++++++++-------------------
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 3 ---
3 files changed, 17 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index 8d1b6a6..b9437c7 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -411,7 +411,7 @@ void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb)
{
dma_addr_t paddr;

- mxsfb_enable_axi_clk(mxsfb);
+ clk_prepare_enable(mxsfb->clk_axi);
writel(0, mxsfb->base + LCDC_CTRL);
mxsfb_crtc_mode_set_nofb(mxsfb);

@@ -428,7 +428,7 @@ void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb)
void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb)
{
mxsfb_disable_controller(mxsfb);
- mxsfb_disable_axi_clk(mxsfb);
+ clk_disable_unprepare(mxsfb->clk_axi);
}

void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
@@ -456,9 +456,9 @@ void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,

paddr = mxsfb_get_fb_paddr(mxsfb);
if (paddr) {
- mxsfb_enable_axi_clk(mxsfb);
+ clk_prepare_enable(mxsfb->clk_axi);
writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
- mxsfb_disable_axi_clk(mxsfb);
+ clk_disable_unprepare(mxsfb->clk_axi);
}

if (!fb || !old_fb)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
index 135b8e1..5e18353 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
@@ -103,18 +103,6 @@ drm_pipe_to_mxsfb_drm_private(struct drm_simple_display_pipe *pipe)
return container_of(pipe, struct mxsfb_drm_private, pipe);
}

-void mxsfb_enable_axi_clk(struct mxsfb_drm_private *mxsfb)
-{
- if (mxsfb->clk_axi)
- clk_prepare_enable(mxsfb->clk_axi);
-}
-
-void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb)
-{
- if (mxsfb->clk_axi)
- clk_disable_unprepare(mxsfb->clk_axi);
-}
-
/**
* mxsfb_atomic_helper_check - validate state object
* @dev: DRM device
@@ -237,25 +225,31 @@ static void mxsfb_pipe_update(struct drm_simple_display_pipe *pipe,
static int mxsfb_pipe_enable_vblank(struct drm_simple_display_pipe *pipe)
{
struct mxsfb_drm_private *mxsfb = drm_pipe_to_mxsfb_drm_private(pipe);
+ int ret = 0;
+
+ ret = clk_prepare_enable(mxsfb->clk_axi);
+ if (ret)
+ return ret;

/* Clear and enable VBLANK IRQ */
- mxsfb_enable_axi_clk(mxsfb);
writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET);
- mxsfb_disable_axi_clk(mxsfb);
+ clk_disable_unprepare(mxsfb->clk_axi);

- return 0;
+ return ret;
}

static void mxsfb_pipe_disable_vblank(struct drm_simple_display_pipe *pipe)
{
struct mxsfb_drm_private *mxsfb = drm_pipe_to_mxsfb_drm_private(pipe);

+ if (clk_prepare_enable(mxsfb->clk_axi))
+ return;
+
/* Disable and clear VBLANK IRQ */
- mxsfb_enable_axi_clk(mxsfb);
writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);
writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
- mxsfb_disable_axi_clk(mxsfb);
+ clk_disable_unprepare(mxsfb->clk_axi);
}

static struct drm_simple_display_pipe_funcs mxsfb_funcs = {
@@ -440,7 +434,7 @@ static irqreturn_t mxsfb_irq_handler(int irq, void *data)
struct mxsfb_drm_private *mxsfb = drm->dev_private;
u32 reg;

- mxsfb_enable_axi_clk(mxsfb);
+ clk_prepare_enable(mxsfb->clk_axi);

reg = readl(mxsfb->base + LCDC_CTRL1);

@@ -449,7 +443,7 @@ static irqreturn_t mxsfb_irq_handler(int irq, void *data)

writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);

- mxsfb_disable_axi_clk(mxsfb);
+ clk_disable_unprepare(mxsfb->clk_axi);

return IRQ_HANDLED;
}
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
index c15b4f9..ce98411 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
@@ -47,9 +47,6 @@ struct mxsfb_drm_private {
int mxsfb_setup_crtc(struct drm_device *dev);
int mxsfb_create_output(struct drm_device *dev);

-void mxsfb_enable_axi_clk(struct mxsfb_drm_private *mxsfb);
-void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb);
-
void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb);
void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb);
void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
--
2.7.4


2019-01-09 14:15:44

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 05/10] drm/mxsfb: Fix the vblank events

Currently, the vblank support is not correctly implemented in MXSFB_DRM
driver. The call to drm_vblank_init is made with mode_config.num_crtc
which at that time is 0. Because of this, vblank is not activated, so
there won't be any vblank event submitted.

Signed-off-by: Robert Chiras <[email protected]>
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
index 76230d7..aa35c43 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
@@ -43,6 +43,9 @@
#include "mxsfb_drv.h"
#include "mxsfb_regs.h"

+/* The eLCDIF max possible CRTCs */
+#define MAX_CRTCS 1
+
enum mxsfb_devtype {
MXSFB_V3,
MXSFB_V4,
@@ -140,6 +143,8 @@ static void mxsfb_pipe_enable(struct drm_simple_display_pipe *pipe,
mxsfb->connector = &mxsfb->panel_connector;
}

+ drm_crtc_vblank_on(&mxsfb->pipe.crtc);
+
pm_runtime_get_sync(drm->dev);
drm_panel_prepare(mxsfb->panel);
mxsfb_crtc_enable(mxsfb);
@@ -249,7 +254,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)

pm_runtime_enable(drm->dev);

- ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+ ret = drm_vblank_init(drm, MAX_CRTCS);
if (ret < 0) {
dev_err(drm->dev, "Failed to initialise vblank\n");
goto err_vblank;
@@ -272,6 +277,8 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
goto err_vblank;
}

+ drm_crtc_vblank_off(&mxsfb->pipe.crtc);
+
/*
* Attach panel only if there is one.
* If there is no panel attach, it must be a bridge. In this case, we
--
2.7.4


2019-01-09 14:16:05

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 07/10] drm/mxsfb: Signal mode changed when bpp changed

From: Mirela Rabulea <[email protected]>

Add mxsfb_atomic_helper_check to signal mode changed when bpp changed.
This will trigger the execution of disable/enable on
a modeset with different bpp than the current one.

Signed-off-by: Mirela Rabulea <[email protected]>
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 48 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
index d3fb3a8..f528a37 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
@@ -115,9 +115,55 @@ void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb)
clk_disable_unprepare(mxsfb->clk_axi);
}

+/**
+ * mxsfb_atomic_helper_check - validate state object
+ * @dev: DRM device
+ * @state: the driver state object
+ *
+ * On top of the drm imlementation drm_atomic_helper_check,
+ * check if the bpp is changed, if so, signal mode_changed,
+ * this will trigger disable/enable
+ *
+ * RETURNS:
+ * Zero for success or -errno
+ */
+static int mxsfb_atomic_helper_check(struct drm_device *dev,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *crtc_state;
+ int i, ret;
+
+ ret = drm_atomic_helper_check(dev, state);
+ if (ret)
+ return ret;
+
+ for_each_crtc_in_state(state, crtc, crtc_state, i) {
+ struct drm_plane_state *primary_state;
+ int old_bpp = 0;
+ int new_bpp = 0;
+
+ if (!crtc->primary || !crtc->primary->old_fb)
+ continue;
+ primary_state =
+ drm_atomic_get_plane_state(state, crtc->primary);
+ if (!primary_state || !primary_state->fb)
+ continue;
+ old_bpp = crtc->primary->old_fb->format->depth;
+ new_bpp = primary_state->fb->format->depth;
+ if (old_bpp != new_bpp) {
+ crtc_state->mode_changed = true;
+ DRM_DEBUG_ATOMIC(
+ "[CRTC:%d:%s] mode changed, bpp %d->%d\n",
+ crtc->base.id, crtc->name, old_bpp, new_bpp);
+ }
+ }
+ return ret;
+}
+
static const struct drm_mode_config_funcs mxsfb_mode_config_funcs = {
.fb_create = drm_gem_fb_create,
- .atomic_check = drm_atomic_helper_check,
+ .atomic_check = mxsfb_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
};

--
2.7.4


2019-01-09 14:16:12

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 06/10] drm/mxsfb: Add support for new pixel formats in eLCDIF

From: Mirela Rabulea <[email protected]>

Add support for the following pixel formats:
16 bpp: RG16 ,BG16, XR15, XB15, AR15, AB15
Set the bus format based on input from the user and panel capabilities.
Save the bus format in crtc->mode.private_flags, the DSI will use it.
Use drm_get_format_name instead of locally defined fourcc_to_str.

Signed-off-by: Mirela Rabulea <[email protected]>
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 100 ++++++++++++++++++++++++++-----------
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 5 ++
2 files changed, 76 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index 6aa8804..b62b607 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -48,24 +48,6 @@ static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
mxsfb->devdata->hs_wdth_shift;
}

-/* Print Four-character-code (FOURCC) */
-static char *fourcc_to_str(u32 fmt)
-{
- /* Use 10 chars so we can simultaneously print two codes */
- static char code[10], *c = &code[0];
-
- if (c == &code[10])
- c = &code[0];
-
- *(c++) = (unsigned char)(fmt & 0xff);
- *(c++) = (unsigned char)((fmt >> 8) & 0xff);
- *(c++) = (unsigned char)((fmt >> 16) & 0xff);
- *(c++) = (unsigned char)((fmt >> 24) & 0xff);
- *(c++) = '\0';
-
- return (c - 5);
-}
-
/* Setup the MXSFB registers for decoding the pixels out of the framebuffer */
static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb, bool update)
{
@@ -74,6 +56,7 @@ static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb, bool update)
const u32 format = crtc->primary->state->fb->format->format;
u32 ctrl = 0, ctrl1 = 0;
bool bgr_format = true;
+ struct drm_format_name_buf format_name_buf;

if (!update)
ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
@@ -92,7 +75,7 @@ static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb, bool update)
}

DRM_DEV_DEBUG_DRIVER(drm->dev, "Setting up %s mode\n",
- fourcc_to_str(format));
+ drm_get_format_name(format, &format_name_buf));

/* Do some clean-up that we might have from a previous mode */
ctrl &= ~CTRL_SHIFT_DIR(1);
@@ -103,19 +86,41 @@ static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb, bool update)
mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);

switch (format) {
- case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565: /* BG16 */
+ if (mxsfb->devdata->ipversion < 4)
+ goto err;
+ writel(CTRL2_ODD_LINE_PATTERN(0x5) |
+ CTRL2_EVEN_LINE_PATTERN(0x5),
+ mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
+ /* Fall through */
+ case DRM_FORMAT_RGB565: /* RG16 */
ctrl |= CTRL_SET_WORD_LENGTH(0);
+ ctrl &= ~CTRL_DF16;
ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
break;
- case DRM_FORMAT_RGBX8888:
- case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_XBGR1555: /* XB15 */
+ case DRM_FORMAT_ABGR1555: /* AB15 */
+ if (mxsfb->devdata->ipversion < 4)
+ goto err;
+ writel(CTRL2_ODD_LINE_PATTERN(0x5) |
+ CTRL2_EVEN_LINE_PATTERN(0x5),
+ mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
+ /* Fall through */
+ case DRM_FORMAT_XRGB1555: /* XR15 */
+ case DRM_FORMAT_ARGB1555: /* AR15 */
+ ctrl |= CTRL_SET_WORD_LENGTH(0);
+ ctrl |= CTRL_DF16;
+ ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
+ break;
+ case DRM_FORMAT_RGBX8888: /* RX24 */
+ case DRM_FORMAT_RGBA8888: /* RA24 */
/* RGBX - > 0RGB */
ctrl |= CTRL_SHIFT_DIR(1);
ctrl |= CTRL_SHIFT_NUM(8);
bgr_format = false;
/* Fall through */
- case DRM_FORMAT_XBGR8888:
- case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_XBGR8888: /* XB24 */
+ case DRM_FORMAT_ABGR8888: /* AB24 */
if (bgr_format) {
if (mxsfb->devdata->ipversion < 4)
goto err;
@@ -124,8 +129,8 @@ static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb, bool update)
mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
}
/* Fall through */
- case DRM_FORMAT_XRGB8888:
- case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XRGB8888: /* XR24 */
+ case DRM_FORMAT_ARGB8888: /* AR24 */
ctrl |= CTRL_SET_WORD_LENGTH(3);
/* Do not use packed pixels = one pixel per word instead. */
ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7);
@@ -146,19 +151,56 @@ static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb, bool update)

err:
DRM_DEV_ERROR(drm->dev, "Unhandled pixel format: %s\n",
- fourcc_to_str(format));
+ drm_get_format_name(format, &format_name_buf));
+
return -EINVAL;
}

+static u32 get_bus_format_from_bpp(u32 bpp)
+{
+ switch (bpp) {
+ case 16:
+ return MEDIA_BUS_FMT_RGB565_1X16;
+ case 18:
+ return MEDIA_BUS_FMT_RGB666_1X18;
+ case 24:
+ return MEDIA_BUS_FMT_RGB888_1X24;
+ default:
+ return MEDIA_BUS_FMT_RGB888_1X24;
+ }
+}
+
static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)
{
struct drm_crtc *crtc = &mxsfb->pipe.crtc;
+ unsigned int bits_per_pixel = crtc->primary->state->fb->format->depth;
struct drm_device *drm = crtc->dev;
u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ int num_bus_formats = mxsfb->connector->display_info.num_bus_formats;
+ const u32 *bus_formats = mxsfb->connector->display_info.bus_formats;
u32 reg = 0;
+ int i = 0;
+
+ /* match the user requested bus_format to one supported by the panel */
+ if (num_bus_formats) {
+ u32 user_bus_format = get_bus_format_from_bpp(bits_per_pixel);
+
+ bus_format = bus_formats[0];
+ for (i = 0; i < num_bus_formats; i++) {
+ if (user_bus_format == bus_formats[i]) {
+ bus_format = user_bus_format;
+ break;
+ }
+ }
+ }

- if (mxsfb->connector->display_info.num_bus_formats)
- bus_format = mxsfb->connector->display_info.bus_formats[0];
+ /*
+ * CRTC will dictate the bus format via private_flags[16:1]
+ * and private_flags[0] will signal a bus format change
+ */
+ crtc->mode.private_flags &= ~0x1FFFF; /* clear bus format */
+ crtc->mode.private_flags |= (bus_format << 1); /* set bus format */
+ crtc->mode.private_flags |= 0x1; /* bus format change indication*/

DRM_DEV_DEBUG_DRIVER(drm->dev,
"Using bus_format: 0x%08X\n", bus_format);
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
index aa35c43..d3fb3a8 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
@@ -65,6 +65,11 @@ static const uint32_t mxsfb_formats[] = {
DRM_FORMAT_ABGR8888,
DRM_FORMAT_RGBX8888,
DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_ABGR1555,
+ DRM_FORMAT_XBGR1555,
+ DRM_FORMAT_BGR565
};

static const struct mxsfb_devdata mxsfb_devdata[] = {
--
2.7.4


2019-01-09 14:17:04

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 08/10] drm/mxsfb: Update mxsfb to support LCD reset

The eLCDIF controller has control pin for the external LCD reset pin.
Add support for it and assert this pin in enable and de-assert it in
disable.
Also, correct the pm_runtime_enable call, since it was made too early in
the probe, causing issues to DRM enable routines.

Signed-off-by: Robert Chiras <[email protected]>
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12 ++++++++++--
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 20 ++++++++------------
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 1 +
3 files changed, 19 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index b62b607..8d1b6a6 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -230,9 +230,12 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
clk_prepare_enable(mxsfb->clk_disp_axi);
clk_prepare_enable(mxsfb->clk);

- if (mxsfb->devdata->ipversion >= 4)
+ if (mxsfb->devdata->ipversion >= 4) {
writel(CTRL2_OUTSTANDING_REQS(REQ_16),
mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
+ /* Assert LCD Reset bit */
+ writel(CTRL2_LCD_RESET, mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
+ }

/* If it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
@@ -250,9 +253,12 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
{
u32 reg;

- if (mxsfb->devdata->ipversion >= 4)
+ if (mxsfb->devdata->ipversion >= 4) {
writel(CTRL2_OUTSTANDING_REQS(0x7),
mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
+ /* De-assert LCD Reset bit */
+ writel(CTRL2_LCD_RESET, mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
+ }

writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR);

@@ -346,6 +352,8 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
return;

clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
+ DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n",
+ m->crtc_clock, (int)(clk_get_rate(mxsfb->clk) / 1000));

DRM_DEV_DEBUG_DRIVER(drm->dev,
"Connector bus_flags: 0x%08X\n", bus_flags);
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
index f528a37..135b8e1 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
@@ -287,7 +287,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
if (IS_ERR(mxsfb->base))
return PTR_ERR(mxsfb->base);

- mxsfb->clk = devm_clk_get(drm->dev, NULL);
+ mxsfb->clk = devm_clk_get(drm->dev, "pix");
if (IS_ERR(mxsfb->clk))
return PTR_ERR(mxsfb->clk);

@@ -303,12 +303,10 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
if (ret)
return ret;

- pm_runtime_enable(drm->dev);
-
ret = drm_vblank_init(drm, MAX_CRTCS);
if (ret < 0) {
dev_err(drm->dev, "Failed to initialise vblank\n");
- goto err_vblank;
+ return ret;
}

/* Modeset init */
@@ -317,7 +315,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
ret = mxsfb_create_output(drm);
if (ret < 0) {
dev_err(drm->dev, "Failed to create outputs\n");
- goto err_vblank;
+ return ret;
}

ret = drm_simple_display_pipe_init(drm, &mxsfb->pipe, &mxsfb_funcs,
@@ -325,7 +323,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
mxsfb->connector);
if (ret < 0) {
dev_err(drm->dev, "Cannot setup simple display pipe\n");
- goto err_vblank;
+ return ret;
}

drm_crtc_vblank_off(&mxsfb->pipe.crtc);
@@ -342,14 +340,14 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
ret = drm_panel_attach(mxsfb->panel, mxsfb->connector);
if (ret) {
dev_err(drm->dev, "Cannot connect panel\n");
- goto err_vblank;
+ return ret;
}
} else if (mxsfb->bridge) {
ret = drm_simple_display_pipe_attach_bridge(&mxsfb->pipe,
mxsfb->bridge);
if (ret) {
dev_err(drm->dev, "Cannot connect bridge\n");
- goto err_vblank;
+ return ret;
}
}

@@ -369,9 +367,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)

drm_mode_config_reset(drm);

- pm_runtime_get_sync(drm->dev);
ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
- pm_runtime_put_sync(drm->dev);

if (ret < 0) {
dev_err(drm->dev, "Failed to install IRQ handler\n");
@@ -393,14 +389,14 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)

drm_helper_hpd_irq_event(drm);

+ pm_runtime_enable(drm->dev);
+
return 0;

err_cma:
drm_irq_uninstall(drm);
err_irq:
drm_panel_detach(mxsfb->panel);
-err_vblank:
- pm_runtime_disable(drm->dev);

return ret;
}
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_regs.h b/drivers/gpu/drm/mxsfb/mxsfb_regs.h
index 4904fdd..1d85750 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_regs.h
+++ b/drivers/gpu/drm/mxsfb/mxsfb_regs.h
@@ -95,6 +95,7 @@
#define CTRL2_OUTSTANDING_REQS(x) REG_PUT((x), 23, 21)
#define CTRL2_ODD_LINE_PATTERN(x) REG_PUT((x), 18, 16)
#define CTRL2_EVEN_LINE_PATTERN(x) REG_PUT((x), 14, 12)
+#define CTRL2_LCD_RESET BIT(0)

#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
--
2.7.4


2019-01-09 14:17:13

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 01/10] drm/mxsfb: Update mxsfb to support a bridge

Currently, the MXSFB DRM driver only supports a panel. But, its output
display signal can also be redirected to another encoder, like a DSI
controller. In this case, that DSI controller may act like a drm_bridge.
In order support this use-case too, this patch adds support for
drm_bridge in mxsfb.

Signed-off-by: Robert Chiras <[email protected]>
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 44 +++++++++++++++++++++++++++++++++---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 46 +++++++++++++++++++++++++++++++++-----
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 4 +++-
drivers/gpu/drm/mxsfb/mxsfb_out.c | 26 +++++++++++----------
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 15 +++++++++++++
5 files changed, 114 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index 24b1f0c..f0648ce 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -101,8 +101,11 @@ static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)

reg = readl(mxsfb->base + LCDC_CTRL);

- if (mxsfb->connector.display_info.num_bus_formats)
- bus_format = mxsfb->connector.display_info.bus_formats[0];
+ if (mxsfb->connector->display_info.num_bus_formats)
+ bus_format = mxsfb->connector->display_info.bus_formats[0];
+
+ DRM_DEV_DEBUG_DRIVER(drm->dev,
+ "Using bus_format: 0x%08X\n", bus_format);

reg &= ~CTRL_BUS_WIDTH_MASK;
switch (bus_format) {
@@ -130,6 +133,9 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
clk_prepare_enable(mxsfb->clk_disp_axi);
clk_prepare_enable(mxsfb->clk);

+ writel(CTRL2_OUTSTANDING_REQS__REQ_16,
+ mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
+
/* If it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);

@@ -139,12 +145,15 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
writel(reg, mxsfb->base + LCDC_VDCTRL4);

writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET);
+ writel(CTRL1_RECOVERY_ON_UNDERFLOW, mxsfb->base + LCDC_CTRL1 + REG_SET);
}

static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
{
u32 reg;

+ writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR);
+
/*
* Even if we disable the controller here, it will still continue
* until its FIFOs are running out of data
@@ -210,8 +219,9 @@ static dma_addr_t mxsfb_get_fb_paddr(struct mxsfb_drm_private *mxsfb)

static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
{
+ struct drm_device *drm = mxsfb->pipe.crtc.dev;
struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;
- const u32 bus_flags = mxsfb->connector.display_info.bus_flags;
+ const u32 bus_flags = mxsfb->connector->display_info.bus_flags;
u32 vdctrl0, vsync_pulse_len, hsync_pulse_len;
int err;

@@ -235,6 +245,11 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)

clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);

+ DRM_DEV_DEBUG_DRIVER(drm->dev,
+ "Connector bus_flags: 0x%08X\n", bus_flags);
+ DRM_DEV_DEBUG_DRIVER(drm->dev,
+ "Mode flags: 0x%08X\n", m->flags);
+
writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) |
TRANSFER_COUNT_SET_HCOUNT(m->crtc_hdisplay),
mxsfb->base + mxsfb->devdata->transfer_count);
@@ -287,6 +302,7 @@ void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb)
dma_addr_t paddr;

mxsfb_enable_axi_clk(mxsfb);
+ writel(0, mxsfb->base + LCDC_CTRL);
mxsfb_crtc_mode_set_nofb(mxsfb);

/* Write cur_buf as well to avoid an initial corrupt frame */
@@ -310,6 +326,8 @@ void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
{
struct drm_simple_display_pipe *pipe = &mxsfb->pipe;
struct drm_crtc *crtc = &pipe->crtc;
+ struct drm_framebuffer *fb = pipe->plane.state->fb;
+ struct drm_framebuffer *old_fb = old_state->fb;
struct drm_pending_vblank_event *event;
dma_addr_t paddr;

@@ -332,4 +350,24 @@ void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
mxsfb_disable_axi_clk(mxsfb);
}
+
+ if (!fb || !old_fb)
+ return;
+
+ /*
+ * TODO: Currently, we only support pixel format change, but we need
+ * also to care about size changes too
+ */
+ if (old_fb->format->format != fb->format->format) {
+ struct drm_format_name_buf old_fmt_buf;
+ struct drm_format_name_buf new_fmt_buf;
+
+ DRM_DEV_DEBUG_DRIVER(crtc->dev->dev,
+ "Switching pixel format: %s -> %s\n",
+ drm_get_format_name(old_fb->format->format,
+ &old_fmt_buf),
+ drm_get_format_name(fb->format->format,
+ &new_fmt_buf));
+ mxsfb_set_pixel_fmt(mxsfb, true);
+ }
}
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
index 88ba003..9a73564 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
@@ -106,9 +106,25 @@ static void mxsfb_pipe_enable(struct drm_simple_display_pipe *pipe,
struct drm_crtc_state *crtc_state,
struct drm_plane_state *plane_state)
{
+ struct drm_connector *connector;
struct mxsfb_drm_private *mxsfb = drm_pipe_to_mxsfb_drm_private(pipe);
struct drm_device *drm = pipe->plane.dev;

+ if (!mxsfb->connector) {
+ list_for_each_entry(connector,
+ &drm->mode_config.connector_list,
+ head)
+ if (connector->encoder == &(mxsfb->pipe.encoder)) {
+ mxsfb->connector = connector;
+ break;
+ }
+ }
+
+ if (!mxsfb->connector) {
+ dev_warn(drm->dev, "No connector attached, using default\n");
+ mxsfb->connector = &mxsfb->panel_connector;
+ }
+
pm_runtime_get_sync(drm->dev);
drm_panel_prepare(mxsfb->panel);
mxsfb_crtc_enable(mxsfb);
@@ -134,6 +150,9 @@ static void mxsfb_pipe_disable(struct drm_simple_display_pipe *pipe)
drm_crtc_send_vblank_event(crtc, event);
}
spin_unlock_irq(&drm->event_lock);
+
+ if (mxsfb->connector != &mxsfb->panel_connector)
+ mxsfb->connector = NULL;
}

static void mxsfb_pipe_update(struct drm_simple_display_pipe *pipe,
@@ -231,16 +250,33 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)

ret = drm_simple_display_pipe_init(drm, &mxsfb->pipe, &mxsfb_funcs,
mxsfb_formats, ARRAY_SIZE(mxsfb_formats), NULL,
- &mxsfb->connector);
+ mxsfb->connector);
if (ret < 0) {
dev_err(drm->dev, "Cannot setup simple display pipe\n");
goto err_vblank;
}

- ret = drm_panel_attach(mxsfb->panel, &mxsfb->connector);
- if (ret) {
- dev_err(drm->dev, "Cannot connect panel\n");
- goto err_vblank;
+ /*
+ * Attach panel only if there is one.
+ * If there is no panel attach, it must be a bridge. In this case, we
+ * need a reference to its connector for a proper initialization.
+ * We will do this check in pipe->enable(), since the connector won't
+ * be attached to an encoder until then.
+ */
+
+ if (mxsfb->panel) {
+ ret = drm_panel_attach(mxsfb->panel, mxsfb->connector);
+ if (ret) {
+ dev_err(drm->dev, "Cannot connect panel\n");
+ goto err_vblank;
+ }
+ } else if (mxsfb->bridge) {
+ ret = drm_simple_display_pipe_attach_bridge(&mxsfb->pipe,
+ mxsfb->bridge);
+ if (ret) {
+ dev_err(drm->dev, "Cannot connect bridge\n");
+ goto err_vblank;
+ }
}

drm->mode_config.min_width = MXSFB_MIN_XRES;
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
index 5d0883f..71238ad 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
@@ -35,8 +35,10 @@ struct mxsfb_drm_private {
struct clk *clk_disp_axi;

struct drm_simple_display_pipe pipe;
- struct drm_connector connector;
+ struct drm_connector panel_connector;
+ struct drm_connector *connector;
struct drm_panel *panel;
+ struct drm_bridge *bridge;
struct drm_fbdev_cma *fbdev;
};

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_out.c b/drivers/gpu/drm/mxsfb/mxsfb_out.c
index e5edf01..ed0d8d3 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_out.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_out.c
@@ -30,7 +30,8 @@
static struct mxsfb_drm_private *
drm_connector_to_mxsfb_drm_private(struct drm_connector *connector)
{
- return container_of(connector, struct mxsfb_drm_private, connector);
+ return container_of(connector, struct mxsfb_drm_private,
+ panel_connector);
}

static int mxsfb_panel_get_modes(struct drm_connector *connector)
@@ -85,22 +86,23 @@ static const struct drm_connector_funcs mxsfb_panel_connector_funcs = {
int mxsfb_create_output(struct drm_device *drm)
{
struct mxsfb_drm_private *mxsfb = drm->dev_private;
- struct drm_panel *panel;
int ret;

- ret = drm_of_find_panel_or_bridge(drm->dev->of_node, 0, 0, &panel, NULL);
+ ret = drm_of_find_panel_or_bridge(drm->dev->of_node, 0, 0,
+ &mxsfb->panel, &mxsfb->bridge);
if (ret)
return ret;

- mxsfb->connector.dpms = DRM_MODE_DPMS_OFF;
- mxsfb->connector.polled = 0;
- drm_connector_helper_add(&mxsfb->connector,
- &mxsfb_panel_connector_helper_funcs);
- ret = drm_connector_init(drm, &mxsfb->connector,
- &mxsfb_panel_connector_funcs,
- DRM_MODE_CONNECTOR_Unknown);
- if (!ret)
- mxsfb->panel = panel;
+ if (mxsfb->panel) {
+ mxsfb->connector = &mxsfb->panel_connector;
+ mxsfb->connector->dpms = DRM_MODE_DPMS_OFF;
+ mxsfb->connector->polled = 0;
+ drm_connector_helper_add(mxsfb->connector,
+ &mxsfb_panel_connector_helper_funcs);
+ ret = drm_connector_init(drm, mxsfb->connector,
+ &mxsfb_panel_connector_funcs,
+ DRM_MODE_CONNECTOR_Unknown);
+ }

return ret;
}
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_regs.h b/drivers/gpu/drm/mxsfb/mxsfb_regs.h
index 66a6ba9..c5b5e40 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_regs.h
+++ b/drivers/gpu/drm/mxsfb/mxsfb_regs.h
@@ -22,19 +22,31 @@

#define LCDC_CTRL 0x00
#define LCDC_CTRL1 0x10
+#define LCDC_V4_CTRL2 0x20
#define LCDC_V3_TRANSFER_COUNT 0x20
#define LCDC_V4_TRANSFER_COUNT 0x30
#define LCDC_V4_CUR_BUF 0x40
#define LCDC_V4_NEXT_BUF 0x50
#define LCDC_V3_CUR_BUF 0x30
#define LCDC_V3_NEXT_BUF 0x40
+#define LCDC_TIMING 0x60
#define LCDC_VDCTRL0 0x70
#define LCDC_VDCTRL1 0x80
#define LCDC_VDCTRL2 0x90
#define LCDC_VDCTRL3 0xa0
#define LCDC_VDCTRL4 0xb0
+#define LCDC_DVICTRL0 0xc0
+#define LCDC_DVICTRL1 0xd0
+#define LCDC_DVICTRL2 0xe0
+#define LCDC_DVICTRL3 0xf0
+#define LCDC_DVICTRL4 0x100
+#define LCDC_V4_DATA 0x180
+#define LCDC_V3_DATA 0x1b0
#define LCDC_V4_DEBUG0 0x1d0
#define LCDC_V3_DEBUG0 0x1f0
+#define LCDC_AS_CTRL 0x210
+#define LCDC_AS_BUF 0x220
+#define LCDC_AS_NEXT_BUF 0x230

#define CTRL_SFTRST (1 << 31)
#define CTRL_CLKGATE (1 << 30)
@@ -53,12 +65,15 @@
#define CTRL_DF24 (1 << 1)
#define CTRL_RUN (1 << 0)

+#define CTRL1_RECOVERY_ON_UNDERFLOW (1 << 24)
#define CTRL1_FIFO_CLEAR (1 << 21)
#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
#define CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
#define CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)

+#define CTRL2_OUTSTANDING_REQS__REQ_16 (4 << 21)
+
#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff)
--
2.7.4


2019-01-09 14:17:27

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 03/10] drm/mxsfb: Add max-res property for MXSFB

Because of stability issues, we may want to limit the maximum resolution
supported by the MXSFB (eLCDIF) driver.
This patch add support for a new property which we can use to impose such
limitation.

Signed-off-by: Robert Chiras <[email protected]>
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
index 9a73564..c0b6198 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
@@ -201,6 +201,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
struct platform_device *pdev = to_platform_device(drm->dev);
struct mxsfb_drm_private *mxsfb;
struct resource *res;
+ u32 max_res[2] = {0, 0};
int ret;

mxsfb = devm_kzalloc(&pdev->dev, sizeof(*mxsfb), GFP_KERNEL);
@@ -279,10 +280,17 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
}
}

+ of_property_read_u32_array(drm->dev->of_node, "max-res",
+ &max_res[0], 2);
+ if (!max_res[0])
+ max_res[0] = MXSFB_MAX_XRES;
+ if (!max_res[1])
+ max_res[1] = MXSFB_MAX_YRES;
+
drm->mode_config.min_width = MXSFB_MIN_XRES;
drm->mode_config.min_height = MXSFB_MIN_YRES;
- drm->mode_config.max_width = MXSFB_MAX_XRES;
- drm->mode_config.max_height = MXSFB_MAX_YRES;
+ drm->mode_config.max_width = max_res[0];
+ drm->mode_config.max_height = max_res[1];
drm->mode_config.funcs = &mxsfb_mode_config_funcs;
drm->mode_config.helper_private = &mxsfb_mode_config_helpers;

--
2.7.4


2019-01-09 15:27:46

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 10/10] drm/mxsfb: Clear OUTSTANDING_REQS bits

Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF
is enabled, since it comes up with default value of 1 (this behaviour
has been seen on some imx8 platforms).
In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting
its value.

Signed-off-by: Robert Chiras <[email protected]>
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index b9437c7..c5689c2 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -231,6 +231,13 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
clk_prepare_enable(mxsfb->clk);

if (mxsfb->devdata->ipversion >= 4) {
+ /*
+ * On some platforms, bit 21 is defaulted to 1, which may alter
+ * the below setting. So, to make sure we have the right setting
+ * clear all the bits for CTRL2_OUTSTANDING_REQS.
+ */
+ writel(CTRL2_OUTSTANDING_REQS(0x7),
+ mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
writel(CTRL2_OUTSTANDING_REQS(REQ_16),
mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
/* Assert LCD Reset bit */
--
2.7.4


2019-01-09 15:48:28

by Robert Chiras

[permalink] [raw]
Subject: [PATCH 04/10] drm/mxsfb: Update mxsfb with additional pixel formats

Since version 4 of eLCDIF, there are some registers that can do
transformations on the input data, like re-arranging the pixel
components. By doing that, we can support more pixel formats.
This patch adds support for X/ABGR and RGBX/A. Although, the local alpha
is not supported by eLCDIF, the alpha pixel formats were added to the
supported pixel formats but it will be ignored. This was necessary since
there are systems (like Android) that requires such pixel formats.

Signed-off-by: Robert Chiras <[email protected]>
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 108 ++++++++++++++++++++++++++++---------
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 27 +++++++---
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 4 +-
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 100 ++++++++++++++++++++--------------
4 files changed, 169 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index f0648ce..6aa8804 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -48,15 +48,35 @@ static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
mxsfb->devdata->hs_wdth_shift;
}

+/* Print Four-character-code (FOURCC) */
+static char *fourcc_to_str(u32 fmt)
+{
+ /* Use 10 chars so we can simultaneously print two codes */
+ static char code[10], *c = &code[0];
+
+ if (c == &code[10])
+ c = &code[0];
+
+ *(c++) = (unsigned char)(fmt & 0xff);
+ *(c++) = (unsigned char)((fmt >> 8) & 0xff);
+ *(c++) = (unsigned char)((fmt >> 16) & 0xff);
+ *(c++) = (unsigned char)((fmt >> 24) & 0xff);
+ *(c++) = '\0';
+
+ return (c - 5);
+}
+
/* Setup the MXSFB registers for decoding the pixels out of the framebuffer */
-static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb)
+static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb, bool update)
{
struct drm_crtc *crtc = &mxsfb->pipe.crtc;
struct drm_device *drm = crtc->dev;
const u32 format = crtc->primary->state->fb->format->format;
- u32 ctrl, ctrl1;
+ u32 ctrl = 0, ctrl1 = 0;
+ bool bgr_format = true;

- ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
+ if (!update)
+ ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;

/*
* WARNING: The bus width, CTRL_SET_BUS_WIDTH(), is configured to
@@ -65,31 +85,69 @@ static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb)
* to arbitrary value. This limitation should not pose an issue.
*/

- /* CTRL1 contains IRQ config and status bits, preserve those. */
- ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
- ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
+ if (!update) {
+ /* CTRL1 contains IRQ config and status bits, preserve those. */
+ ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
+ ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
+ }
+
+ DRM_DEV_DEBUG_DRIVER(drm->dev, "Setting up %s mode\n",
+ fourcc_to_str(format));
+
+ /* Do some clean-up that we might have from a previous mode */
+ ctrl &= ~CTRL_SHIFT_DIR(1);
+ ctrl &= ~CTRL_SHIFT_NUM(0x3f);
+ if (mxsfb->devdata->ipversion >= 4)
+ writel(CTRL2_ODD_LINE_PATTERN(0x7) |
+ CTRL2_EVEN_LINE_PATTERN(0x7),
+ mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);

switch (format) {
case DRM_FORMAT_RGB565:
- dev_dbg(drm->dev, "Setting up RGB565 mode\n");
ctrl |= CTRL_SET_WORD_LENGTH(0);
ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
break;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ /* RGBX - > 0RGB */
+ ctrl |= CTRL_SHIFT_DIR(1);
+ ctrl |= CTRL_SHIFT_NUM(8);
+ bgr_format = false;
+ /* Fall through */
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ if (bgr_format) {
+ if (mxsfb->devdata->ipversion < 4)
+ goto err;
+ writel(CTRL2_ODD_LINE_PATTERN(0x5) |
+ CTRL2_EVEN_LINE_PATTERN(0x5),
+ mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
+ }
+ /* Fall through */
case DRM_FORMAT_XRGB8888:
- dev_dbg(drm->dev, "Setting up XRGB8888 mode\n");
+ case DRM_FORMAT_ARGB8888:
ctrl |= CTRL_SET_WORD_LENGTH(3);
/* Do not use packed pixels = one pixel per word instead. */
ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7);
break;
default:
- dev_err(drm->dev, "Unhandled pixel format %08x\n", format);
- return -EINVAL;
+ goto err;
}

- writel(ctrl1, mxsfb->base + LCDC_CTRL1);
- writel(ctrl, mxsfb->base + LCDC_CTRL);
+ if (update) {
+ writel(ctrl, mxsfb->base + LCDC_CTRL + REG_SET);
+ writel(ctrl1, mxsfb->base + LCDC_CTRL1 + REG_SET);
+ } else {
+ writel(ctrl, mxsfb->base + LCDC_CTRL);
+ writel(ctrl1, mxsfb->base + LCDC_CTRL1);
+ }

return 0;
+
+err:
+ DRM_DEV_ERROR(drm->dev, "Unhandled pixel format: %s\n",
+ fourcc_to_str(format));
+ return -EINVAL;
}

static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)
@@ -97,9 +155,7 @@ static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)
struct drm_crtc *crtc = &mxsfb->pipe.crtc;
struct drm_device *drm = crtc->dev;
u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
- u32 reg;
-
- reg = readl(mxsfb->base + LCDC_CTRL);
+ u32 reg = 0;

if (mxsfb->connector->display_info.num_bus_formats)
bus_format = mxsfb->connector->display_info.bus_formats[0];
@@ -107,22 +163,21 @@ static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)
DRM_DEV_DEBUG_DRIVER(drm->dev,
"Using bus_format: 0x%08X\n", bus_format);

- reg &= ~CTRL_BUS_WIDTH_MASK;
switch (bus_format) {
case MEDIA_BUS_FMT_RGB565_1X16:
- reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT);
+ reg = CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT);
break;
case MEDIA_BUS_FMT_RGB666_1X18:
- reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_18BIT);
+ reg = CTRL_SET_BUS_WIDTH(STMLCDIF_18BIT);
break;
case MEDIA_BUS_FMT_RGB888_1X24:
- reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
+ reg = CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
break;
default:
dev_err(drm->dev, "Unknown media bus format %d\n", bus_format);
break;
}
- writel(reg, mxsfb->base + LCDC_CTRL);
+ writel(reg, mxsfb->base + LCDC_CTRL + REG_SET);
}

static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
@@ -133,8 +188,9 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
clk_prepare_enable(mxsfb->clk_disp_axi);
clk_prepare_enable(mxsfb->clk);

- writel(CTRL2_OUTSTANDING_REQS__REQ_16,
- mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
+ if (mxsfb->devdata->ipversion >= 4)
+ writel(CTRL2_OUTSTANDING_REQS(REQ_16),
+ mxsfb->base + LCDC_V4_CTRL2 + REG_SET);

/* If it was disabled, re-enable the mode again */
writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
@@ -152,6 +208,10 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
{
u32 reg;

+ if (mxsfb->devdata->ipversion >= 4)
+ writel(CTRL2_OUTSTANDING_REQS(0x7),
+ mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
+
writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR);

/*
@@ -239,7 +299,7 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
/* Clear the FIFOs */
writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);

- err = mxsfb_set_pixel_fmt(mxsfb);
+ err = mxsfb_set_pixel_fmt(mxsfb, false);
if (err)
return;

@@ -322,7 +382,7 @@ void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb)
}

void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
- struct drm_plane_state *state)
+ struct drm_plane_state *old_state)
{
struct drm_simple_display_pipe *pipe = &mxsfb->pipe;
struct drm_crtc *crtc = &pipe->crtc;
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
index c0b6198..76230d7 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
@@ -48,6 +48,22 @@ enum mxsfb_devtype {
MXSFB_V4,
};

+/*
+ * When adding new formats, make sure to update the num_formats from
+ * mxsfb_devdata below.
+ */
+static const uint32_t mxsfb_formats[] = {
+ /* MXSFB_V3 */
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_RGB565,
+ /* MXSFB_V4 */
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_RGBA8888,
+};
+
static const struct mxsfb_devdata mxsfb_devdata[] = {
[MXSFB_V3] = {
.transfer_count = LCDC_V3_TRANSFER_COUNT,
@@ -57,6 +73,8 @@ static const struct mxsfb_devdata mxsfb_devdata[] = {
.hs_wdth_mask = 0xff,
.hs_wdth_shift = 24,
.ipversion = 3,
+ .flags = MXSFB_FLAG_NULL,
+ .num_formats = 3,
},
[MXSFB_V4] = {
.transfer_count = LCDC_V4_TRANSFER_COUNT,
@@ -66,14 +84,11 @@ static const struct mxsfb_devdata mxsfb_devdata[] = {
.hs_wdth_mask = 0x3fff,
.hs_wdth_shift = 18,
.ipversion = 4,
+ .flags = MXSFB_FLAG_BUSFREQ,
+ .num_formats = ARRAY_SIZE(mxsfb_formats),
},
};

-static const uint32_t mxsfb_formats[] = {
- DRM_FORMAT_XRGB8888,
- DRM_FORMAT_RGB565
-};
-
static struct mxsfb_drm_private *
drm_pipe_to_mxsfb_drm_private(struct drm_simple_display_pipe *pipe)
{
@@ -250,7 +265,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
}

ret = drm_simple_display_pipe_init(drm, &mxsfb->pipe, &mxsfb_funcs,
- mxsfb_formats, ARRAY_SIZE(mxsfb_formats), NULL,
+ mxsfb_formats, mxsfb->devdata->num_formats, NULL,
mxsfb->connector);
if (ret < 0) {
dev_err(drm->dev, "Cannot setup simple display pipe\n");
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
index 71238ad..c15b4f9 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
+++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
@@ -24,6 +24,8 @@ struct mxsfb_devdata {
unsigned int hs_wdth_mask;
unsigned int hs_wdth_shift;
unsigned int ipversion;
+ unsigned int flags;
+ unsigned int num_formats;
};

struct mxsfb_drm_private {
@@ -51,6 +53,6 @@ void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb);
void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb);
void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb);
void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
- struct drm_plane_state *state);
+ struct drm_plane_state *old_state);

#endif /* __MXSFB_DRV_H__ */
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_regs.h b/drivers/gpu/drm/mxsfb/mxsfb_regs.h
index c5b5e40..4904fdd 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_regs.h
+++ b/drivers/gpu/drm/mxsfb/mxsfb_regs.h
@@ -48,54 +48,76 @@
#define LCDC_AS_BUF 0x220
#define LCDC_AS_NEXT_BUF 0x230

-#define CTRL_SFTRST (1 << 31)
-#define CTRL_CLKGATE (1 << 30)
-#define CTRL_BYPASS_COUNT (1 << 19)
-#define CTRL_VSYNC_MODE (1 << 18)
-#define CTRL_DOTCLK_MODE (1 << 17)
-#define CTRL_DATA_SELECT (1 << 16)
-#define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10)
-#define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3)
-#define CTRL_BUS_WIDTH_MASK (0x3 << 10)
-#define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8)
-#define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3)
-#define CTRL_MASTER (1 << 5)
-#define CTRL_DF16 (1 << 3)
-#define CTRL_DF18 (1 << 2)
-#define CTRL_DF24 (1 << 1)
-#define CTRL_RUN (1 << 0)
-
-#define CTRL1_RECOVERY_ON_UNDERFLOW (1 << 24)
-#define CTRL1_FIFO_CLEAR (1 << 21)
-#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
-#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
-#define CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
-#define CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
-
-#define CTRL2_OUTSTANDING_REQS__REQ_16 (4 << 21)
+/* reg bit manipulation */
+#define REG_MASK(e, s) (((1 << ((e) - (s) + 1)) - 1) << (s))
+#define REG_PUT(x, e, s) (((x) << (s)) & REG_MASK(e, s))
+#define REG_GET(x, e, s) (((x) & REG_MASK(e, s)) >> (s))
+
+#define SWIZZLE_LE 0 /* Little-Endian or No swap */
+#define SWIZZLE_BE 1 /* Big-Endian or swap all */
+#define SWIZZLE_HWD 2 /* Swap half-words */
+#define SWIZZLE_HWD_BYTE 3 /* Swap bytes within each half-word */
+
+#define CTRL_SFTRST BIT(31)
+#define CTRL_CLKGATE BIT(30)
+#define CTRL_SHIFT_DIR(x) REG_PUT((x), 26, 26)
+#define CTRL_SHIFT_NUM(x) REG_PUT((x), 25, 21)
+#define CTRL_BYPASS_COUNT BIT(19)
+#define CTRL_VSYNC_MODE BIT(18)
+#define CTRL_DOTCLK_MODE BIT(17)
+#define CTRL_DATA_SELECT BIT(16)
+#define CTRL_INPUT_SWIZZLE(x) REG_PUT((x), 15, 14)
+#define CTRL_CSC_SWIZZLE(x) REG_PUT((x), 13, 12)
+#define CTRL_SET_BUS_WIDTH(x) REG_PUT((x), 11, 10)
+#define CTRL_GET_BUS_WIDTH(x) REG_GET((x), 11, 10)
+#define CTRL_BUS_WIDTH_MASK REG_PUT((0x3), 11, 10)
+#define CTRL_SET_WORD_LENGTH(x) REG_PUT((x), 9, 8)
+#define CTRL_GET_WORD_LENGTH(x) REG_GET((x), 9, 8)
+#define CTRL_MASTER BIT(5)
+#define CTRL_DF16 BIT(3)
+#define CTRL_DF18 BIT(2)
+#define CTRL_DF24 BIT(1)
+#define CTRL_RUN BIT(0)
+
+#define CTRL1_RECOVERY_ON_UNDERFLOW BIT(24)
+#define CTRL1_FIFO_CLEAR BIT(21)
+#define CTRL1_SET_BYTE_PACKAGING(x) REG_PUT((x), 19, 16)
+#define CTRL1_GET_BYTE_PACKAGING(x) REG_GET((x), 19, 16)
+#define CTRL1_CUR_FRAME_DONE_IRQ_EN BIT(13)
+#define CTRL1_CUR_FRAME_DONE_IRQ BIT(9)
+
+#define REQ_1 0
+#define REQ_2 1
+#define REQ_4 2
+#define REQ_8 3
+#define REQ_16 4
+
+#define CTRL2_OUTSTANDING_REQS(x) REG_PUT((x), 23, 21)
+#define CTRL2_ODD_LINE_PATTERN(x) REG_PUT((x), 18, 16)
+#define CTRL2_EVEN_LINE_PATTERN(x) REG_PUT((x), 14, 12)

#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff)
#define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff)

-#define VDCTRL0_ENABLE_PRESENT (1 << 28)
-#define VDCTRL0_VSYNC_ACT_HIGH (1 << 27)
-#define VDCTRL0_HSYNC_ACT_HIGH (1 << 26)
-#define VDCTRL0_DOTCLK_ACT_FALLING (1 << 25)
-#define VDCTRL0_ENABLE_ACT_HIGH (1 << 24)
-#define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
-#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
-#define VDCTRL0_HALF_LINE (1 << 19)
-#define VDCTRL0_HALF_LINE_MODE (1 << 18)
+#define VDCTRL0_ENABLE_PRESENT BIT(28)
+#define VDCTRL0_VSYNC_ACT_HIGH BIT(27)
+#define VDCTRL0_HSYNC_ACT_HIGH BIT(26)
+#define VDCTRL0_DOTCLK_ACT_FALLING BIT(25)
+#define VDCTRL0_ENABLE_ACT_HIGH BIT(24)
+#define VDCTRL0_VSYNC_PERIOD_UNIT BIT(21)
+#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT BIT(20)
+#define VDCTRL0_HALF_LINE BIT(19)
+#define VDCTRL0_HALF_LINE_MODE BIT(18)
#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)

#define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
#define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff)

-#define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
-#define VDCTRL3_VSYNC_ONLY (1 << 28)
+#define VDCTRL3_MUX_SYNC_SIGNALS BIT(29)
+#define VDCTRL3_VSYNC_ONLY BIT(28)
#define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16)
#define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff)
#define SET_VERT_WAIT_CNT(x) ((x) & 0xffff)
@@ -103,7 +125,7 @@

#define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */
#define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */
-#define VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
+#define VDCTRL4_SYNC_SIGNALS_ON BIT(18)
#define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff)

#define DEBUG0_HSYNC (1 < 26)
@@ -124,7 +146,7 @@
#define STMLCDIF_18BIT 2 /* pixel data bus to the display is of 18 bit width */
#define STMLCDIF_24BIT 3 /* pixel data bus to the display is of 24 bit width */

-#define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
-#define MXSFB_SYNC_DOTCLK_FALLING_ACT (1 << 7) /* negative edge sampling */
+#define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT BIT(6)
+#define MXSFB_SYNC_DOTCLK_FALLING_ACT BIT(7) /* negative edge sampling */

#endif /* __MXSFB_REGS_H__ */
--
2.7.4


2019-01-09 17:11:51

by Stefan Agner

[permalink] [raw]
Subject: Re: [PATCH 09/10] drm/mxsfb: Improve the axi clock usage

On 09.01.2019 15:13, Robert Chiras wrote:
> Currently, the enable of the axi clock return status is ignored, causing
> issues when the enable fails then we try to disable it. Therefore, it is
> better to check the return status and disable it only when enable
> succeeded.
> Also, remove the helper functions around clk_axi, since we can directly
> use the clk API function for enable/disable the clock. Those functions
> are already checking for NULL clk and returning 0 if that's the case.

Can we maybe even use the runtime PM system for that (adding two
callbacks for SET_RUNTIME_PM_OPS)?

I suggested it a while ago, but did not looked deeper into it:
https://lkml.org/lkml/2018/8/1/300

Since we basically enable on mxsfb_crtc_enable and disable on
mxsfb_crtc_disable, I think it would be pretty much the same thing.

--
Stefan


>
> Signed-off-by: Robert Chiras <[email protected]>
> Acked-by: Leonard Crestez <[email protected]>
> ---
> drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8 ++++----
> drivers/gpu/drm/mxsfb/mxsfb_drv.c | 32 +++++++++++++-------------------
> drivers/gpu/drm/mxsfb/mxsfb_drv.h | 3 ---
> 3 files changed, 17 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> index 8d1b6a6..b9437c7 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> @@ -411,7 +411,7 @@ void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb)
> {
> dma_addr_t paddr;
>
> - mxsfb_enable_axi_clk(mxsfb);
> + clk_prepare_enable(mxsfb->clk_axi);
> writel(0, mxsfb->base + LCDC_CTRL);
> mxsfb_crtc_mode_set_nofb(mxsfb);
>
> @@ -428,7 +428,7 @@ void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb)
> void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb)
> {
> mxsfb_disable_controller(mxsfb);
> - mxsfb_disable_axi_clk(mxsfb);
> + clk_disable_unprepare(mxsfb->clk_axi);
> }
>
> void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
> @@ -456,9 +456,9 @@ void mxsfb_plane_atomic_update(struct
> mxsfb_drm_private *mxsfb,
>
> paddr = mxsfb_get_fb_paddr(mxsfb);
> if (paddr) {
> - mxsfb_enable_axi_clk(mxsfb);
> + clk_prepare_enable(mxsfb->clk_axi);
> writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
> - mxsfb_disable_axi_clk(mxsfb);
> + clk_disable_unprepare(mxsfb->clk_axi);
> }
>
> if (!fb || !old_fb)
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> index 135b8e1..5e18353 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> @@ -103,18 +103,6 @@ drm_pipe_to_mxsfb_drm_private(struct
> drm_simple_display_pipe *pipe)
> return container_of(pipe, struct mxsfb_drm_private, pipe);
> }
>
> -void mxsfb_enable_axi_clk(struct mxsfb_drm_private *mxsfb)
> -{
> - if (mxsfb->clk_axi)
> - clk_prepare_enable(mxsfb->clk_axi);
> -}
> -
> -void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb)
> -{
> - if (mxsfb->clk_axi)
> - clk_disable_unprepare(mxsfb->clk_axi);
> -}
> -
> /**
> * mxsfb_atomic_helper_check - validate state object
> * @dev: DRM device
> @@ -237,25 +225,31 @@ static void mxsfb_pipe_update(struct
> drm_simple_display_pipe *pipe,
> static int mxsfb_pipe_enable_vblank(struct drm_simple_display_pipe *pipe)
> {
> struct mxsfb_drm_private *mxsfb = drm_pipe_to_mxsfb_drm_private(pipe);
> + int ret = 0;
> +
> + ret = clk_prepare_enable(mxsfb->clk_axi);
> + if (ret)
> + return ret;
>
> /* Clear and enable VBLANK IRQ */
> - mxsfb_enable_axi_clk(mxsfb);
> writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
> writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET);
> - mxsfb_disable_axi_clk(mxsfb);
> + clk_disable_unprepare(mxsfb->clk_axi);
>
> - return 0;
> + return ret;
> }
>
> static void mxsfb_pipe_disable_vblank(struct drm_simple_display_pipe *pipe)
> {
> struct mxsfb_drm_private *mxsfb = drm_pipe_to_mxsfb_drm_private(pipe);
>
> + if (clk_prepare_enable(mxsfb->clk_axi))
> + return;
> +
> /* Disable and clear VBLANK IRQ */
> - mxsfb_enable_axi_clk(mxsfb);
> writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);
> writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
> - mxsfb_disable_axi_clk(mxsfb);
> + clk_disable_unprepare(mxsfb->clk_axi);
> }
>
> static struct drm_simple_display_pipe_funcs mxsfb_funcs = {
> @@ -440,7 +434,7 @@ static irqreturn_t mxsfb_irq_handler(int irq, void *data)
> struct mxsfb_drm_private *mxsfb = drm->dev_private;
> u32 reg;
>
> - mxsfb_enable_axi_clk(mxsfb);
> + clk_prepare_enable(mxsfb->clk_axi);
>
> reg = readl(mxsfb->base + LCDC_CTRL1);
>
> @@ -449,7 +443,7 @@ static irqreturn_t mxsfb_irq_handler(int irq, void *data)
>
> writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
>
> - mxsfb_disable_axi_clk(mxsfb);
> + clk_disable_unprepare(mxsfb->clk_axi);
>
> return IRQ_HANDLED;
> }
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> index c15b4f9..ce98411 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> @@ -47,9 +47,6 @@ struct mxsfb_drm_private {
> int mxsfb_setup_crtc(struct drm_device *dev);
> int mxsfb_create_output(struct drm_device *dev);
>
> -void mxsfb_enable_axi_clk(struct mxsfb_drm_private *mxsfb);
> -void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb);
> -
> void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb);
> void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb);
> void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,

2019-01-10 22:01:42

by Fabio Estevam

[permalink] [raw]
Subject: Re: [PATCH 08/10] drm/mxsfb: Update mxsfb to support LCD reset

Hi Robert,

On Thu, Jan 10, 2019 at 6:34 AM Robert Chiras <[email protected]> wrote:
>
> The eLCDIF controller has control pin for the external LCD reset pin.
> Add support for it and assert this pin in enable and de-assert it in
> disable.
> Also, correct the pm_runtime_enable call, since it was made too early in
> the probe, causing issues to DRM enable routines.

The pm_runtime change should be on a different patch.

> Signed-off-by: Robert Chiras <[email protected]>
> ---
> drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12 ++++++++++--
> drivers/gpu/drm/mxsfb/mxsfb_drv.c | 20 ++++++++------------
> drivers/gpu/drm/mxsfb/mxsfb_regs.h | 1 +
> 3 files changed, 19 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> index b62b607..8d1b6a6 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> @@ -230,9 +230,12 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
> clk_prepare_enable(mxsfb->clk_disp_axi);
> clk_prepare_enable(mxsfb->clk);
>
> - if (mxsfb->devdata->ipversion >= 4)
> + if (mxsfb->devdata->ipversion >= 4) {
> writel(CTRL2_OUTSTANDING_REQS(REQ_16),
> mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
> + /* Assert LCD Reset bit */
> + writel(CTRL2_LCD_RESET, mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
> + }
>
> /* If it was disabled, re-enable the mode again */
> writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
> @@ -250,9 +253,12 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
> {
> u32 reg;
>
> - if (mxsfb->devdata->ipversion >= 4)
> + if (mxsfb->devdata->ipversion >= 4) {
> writel(CTRL2_OUTSTANDING_REQS(0x7),
> mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
> + /* De-assert LCD Reset bit */
> + writel(CTRL2_LCD_RESET, mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
> + }
>
> writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR);
>
> @@ -346,6 +352,8 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
> return;
>
> clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
> + DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n",
> + m->crtc_clock, (int)(clk_get_rate(mxsfb->clk) / 1000));

This unrelated change should also be in a different patch.
>
> DRM_DEV_DEBUG_DRIVER(drm->dev,
> "Connector bus_flags: 0x%08X\n", bus_flags);
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> index f528a37..135b8e1 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> @@ -287,7 +287,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
> if (IS_ERR(mxsfb->base))
> return PTR_ERR(mxsfb->base);
>
> - mxsfb->clk = devm_clk_get(drm->dev, NULL);
> + mxsfb->clk = devm_clk_get(drm->dev, "pix");

This breaks mx23 and mx28 as there is no "pix" clock defined in their
dtsi files.

2019-01-14 16:46:27

by Guido Günther

[permalink] [raw]
Subject: Re: [PATCH 04/10] drm/mxsfb: Update mxsfb with additional pixel formats

Hi,
On Wed, Jan 09, 2019 at 02:13:43PM +0000, Robert Chiras wrote:
> Since version 4 of eLCDIF, there are some registers that can do
> transformations on the input data, like re-arranging the pixel
> components. By doing that, we can support more pixel formats.
> This patch adds support for X/ABGR and RGBX/A. Although, the local alpha
> is not supported by eLCDIF, the alpha pixel formats were added to the
> supported pixel formats but it will be ignored. This was necessary since
> there are systems (like Android) that requires such pixel formats.
>
> Signed-off-by: Robert Chiras <[email protected]>
> ---
> drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 108 ++++++++++++++++++++++++++++---------
> drivers/gpu/drm/mxsfb/mxsfb_drv.c | 27 +++++++---
> drivers/gpu/drm/mxsfb/mxsfb_drv.h | 4 +-
> drivers/gpu/drm/mxsfb/mxsfb_regs.h | 100 ++++++++++++++++++++--------------
> 4 files changed, 169 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> index f0648ce..6aa8804 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> @@ -48,15 +48,35 @@ static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
> mxsfb->devdata->hs_wdth_shift;
> }
>
> +/* Print Four-character-code (FOURCC) */
> +static char *fourcc_to_str(u32 fmt)
> +{
> + /* Use 10 chars so we can simultaneously print two codes */
> + static char code[10], *c = &code[0];
> +
> + if (c == &code[10])
> + c = &code[0];
> +
> + *(c++) = (unsigned char)(fmt & 0xff);
> + *(c++) = (unsigned char)((fmt >> 8) & 0xff);
> + *(c++) = (unsigned char)((fmt >> 16) & 0xff);
> + *(c++) = (unsigned char)((fmt >> 24) & 0xff);
> + *(c++) = '\0';
> +
> + return (c - 5);
> +}
> +
> /* Setup the MXSFB registers for decoding the pixels out of the framebuffer */
> -static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb)
> +static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb, bool update)
> {
> struct drm_crtc *crtc = &mxsfb->pipe.crtc;
> struct drm_device *drm = crtc->dev;
> const u32 format = crtc->primary->state->fb->format->format;
> - u32 ctrl, ctrl1;
> + u32 ctrl = 0, ctrl1 = 0;
> + bool bgr_format = true;
>
> - ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
> + if (!update)
> + ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
>
> /*
> * WARNING: The bus width, CTRL_SET_BUS_WIDTH(), is configured to
> @@ -65,31 +85,69 @@ static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb)
> * to arbitrary value. This limitation should not pose an issue.
> */
>
> - /* CTRL1 contains IRQ config and status bits, preserve those. */
> - ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
> - ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
> + if (!update) {
> + /* CTRL1 contains IRQ config and status bits, preserve those. */
> + ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
> + ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
> + }
> +
> + DRM_DEV_DEBUG_DRIVER(drm->dev, "Setting up %s mode\n",
> + fourcc_to_str(format));
> +
> + /* Do some clean-up that we might have from a previous mode */
> + ctrl &= ~CTRL_SHIFT_DIR(1);
> + ctrl &= ~CTRL_SHIFT_NUM(0x3f);
> + if (mxsfb->devdata->ipversion >= 4)
> + writel(CTRL2_ODD_LINE_PATTERN(0x7) |
> + CTRL2_EVEN_LINE_PATTERN(0x7),
> + mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
>
> switch (format) {
> case DRM_FORMAT_RGB565:
> - dev_dbg(drm->dev, "Setting up RGB565 mode\n");
> ctrl |= CTRL_SET_WORD_LENGTH(0);
> ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
> break;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + /* RGBX - > 0RGB */
> + ctrl |= CTRL_SHIFT_DIR(1);
> + ctrl |= CTRL_SHIFT_NUM(8);
> + bgr_format = false;
> + /* Fall through */
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + if (bgr_format) {
> + if (mxsfb->devdata->ipversion < 4)
> + goto err;
> + writel(CTRL2_ODD_LINE_PATTERN(0x5) |
> + CTRL2_EVEN_LINE_PATTERN(0x5),
> + mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
> + }
> + /* Fall through */
> case DRM_FORMAT_XRGB8888:
> - dev_dbg(drm->dev, "Setting up XRGB8888 mode\n");
> + case DRM_FORMAT_ARGB8888:
> ctrl |= CTRL_SET_WORD_LENGTH(3);
> /* Do not use packed pixels = one pixel per word instead. */
> ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7);
> break;
> default:
> - dev_err(drm->dev, "Unhandled pixel format %08x\n", format);
> - return -EINVAL;
> + goto err;
> }
>
> - writel(ctrl1, mxsfb->base + LCDC_CTRL1);
> - writel(ctrl, mxsfb->base + LCDC_CTRL);
> + if (update) {
> + writel(ctrl, mxsfb->base + LCDC_CTRL + REG_SET);
> + writel(ctrl1, mxsfb->base + LCDC_CTRL1 + REG_SET);
> + } else {
> + writel(ctrl, mxsfb->base + LCDC_CTRL);
> + writel(ctrl1, mxsfb->base + LCDC_CTRL1);
> + }
>
> return 0;
> +
> +err:
> + DRM_DEV_ERROR(drm->dev, "Unhandled pixel format: %s\n",
> + fourcc_to_str(format));
> + return -EINVAL;
> }
>
> static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)
> @@ -97,9 +155,7 @@ static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)
> struct drm_crtc *crtc = &mxsfb->pipe.crtc;
> struct drm_device *drm = crtc->dev;
> u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
> - u32 reg;
> -
> - reg = readl(mxsfb->base + LCDC_CTRL);
> + u32 reg = 0;
>
> if (mxsfb->connector->display_info.num_bus_formats)
> bus_format = mxsfb->connector->display_info.bus_formats[0];
> @@ -107,22 +163,21 @@ static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)
> DRM_DEV_DEBUG_DRIVER(drm->dev,
> "Using bus_format: 0x%08X\n", bus_format);
>
> - reg &= ~CTRL_BUS_WIDTH_MASK;
> switch (bus_format) {
> case MEDIA_BUS_FMT_RGB565_1X16:
> - reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT);
> + reg = CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT);
> break;
> case MEDIA_BUS_FMT_RGB666_1X18:
> - reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_18BIT);
> + reg = CTRL_SET_BUS_WIDTH(STMLCDIF_18BIT);
> break;
> case MEDIA_BUS_FMT_RGB888_1X24:
> - reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
> + reg = CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
> break;
> default:
> dev_err(drm->dev, "Unknown media bus format %d\n", bus_format);
> break;
> }
> - writel(reg, mxsfb->base + LCDC_CTRL);
> + writel(reg, mxsfb->base + LCDC_CTRL + REG_SET);
> }
>
> static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
> @@ -133,8 +188,9 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
> clk_prepare_enable(mxsfb->clk_disp_axi);
> clk_prepare_enable(mxsfb->clk);
>
> - writel(CTRL2_OUTSTANDING_REQS__REQ_16,
> - mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
> + if (mxsfb->devdata->ipversion >= 4)
> + writel(CTRL2_OUTSTANDING_REQS(REQ_16),
> + mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
>
> /* If it was disabled, re-enable the mode again */
> writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
> @@ -152,6 +208,10 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
> {
> u32 reg;
>
> + if (mxsfb->devdata->ipversion >= 4)
> + writel(CTRL2_OUTSTANDING_REQS(0x7),
> + mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
> +
> writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR);
>
> /*
> @@ -239,7 +299,7 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
> /* Clear the FIFOs */
> writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
>
> - err = mxsfb_set_pixel_fmt(mxsfb);
> + err = mxsfb_set_pixel_fmt(mxsfb, false);
> if (err)
> return;
>
> @@ -322,7 +382,7 @@ void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb)
> }
>
> void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
> - struct drm_plane_state *state)
> + struct drm_plane_state *old_state)
> {
> struct drm_simple_display_pipe *pipe = &mxsfb->pipe;
> struct drm_crtc *crtc = &pipe->crtc;
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> index c0b6198..76230d7 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> @@ -48,6 +48,22 @@ enum mxsfb_devtype {
> MXSFB_V4,
> };
>
> +/*
> + * When adding new formats, make sure to update the num_formats from
> + * mxsfb_devdata below.
> + */
> +static const uint32_t mxsfb_formats[] = {
> + /* MXSFB_V3 */
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_RGB565,
> + /* MXSFB_V4 */
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_RGBX8888,
> + DRM_FORMAT_RGBA8888,
> +};
> +
> static const struct mxsfb_devdata mxsfb_devdata[] = {
> [MXSFB_V3] = {
> .transfer_count = LCDC_V3_TRANSFER_COUNT,
> @@ -57,6 +73,8 @@ static const struct mxsfb_devdata mxsfb_devdata[] = {
> .hs_wdth_mask = 0xff,
> .hs_wdth_shift = 24,
> .ipversion = 3,
> + .flags = MXSFB_FLAG_NULL,
> + .num_formats = 3,
> },
> [MXSFB_V4] = {
> .transfer_count = LCDC_V4_TRANSFER_COUNT,
> @@ -66,14 +84,11 @@ static const struct mxsfb_devdata mxsfb_devdata[] = {
> .hs_wdth_mask = 0x3fff,
> .hs_wdth_shift = 18,
> .ipversion = 4,
> + .flags = MXSFB_FLAG_BUSFREQ,

This and MXSFB_FLAG_NULL never got defined (unless I overlooked it).
Cheers,
-- Guido

> + .num_formats = ARRAY_SIZE(mxsfb_formats),
> },
> };
>
> -static const uint32_t mxsfb_formats[] = {
> - DRM_FORMAT_XRGB8888,
> - DRM_FORMAT_RGB565
> -};
> -
> static struct mxsfb_drm_private *
> drm_pipe_to_mxsfb_drm_private(struct drm_simple_display_pipe *pipe)
> {
> @@ -250,7 +265,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
> }
>
> ret = drm_simple_display_pipe_init(drm, &mxsfb->pipe, &mxsfb_funcs,
> - mxsfb_formats, ARRAY_SIZE(mxsfb_formats), NULL,
> + mxsfb_formats, mxsfb->devdata->num_formats, NULL,
> mxsfb->connector);
> if (ret < 0) {
> dev_err(drm->dev, "Cannot setup simple display pipe\n");
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> index 71238ad..c15b4f9 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> @@ -24,6 +24,8 @@ struct mxsfb_devdata {
> unsigned int hs_wdth_mask;
> unsigned int hs_wdth_shift;
> unsigned int ipversion;
> + unsigned int flags;
> + unsigned int num_formats;
> };
>
> struct mxsfb_drm_private {
> @@ -51,6 +53,6 @@ void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb);
> void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb);
> void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb);
> void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
> - struct drm_plane_state *state);
> + struct drm_plane_state *old_state);
>
> #endif /* __MXSFB_DRV_H__ */
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_regs.h b/drivers/gpu/drm/mxsfb/mxsfb_regs.h
> index c5b5e40..4904fdd 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_regs.h
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_regs.h
> @@ -48,54 +48,76 @@
> #define LCDC_AS_BUF 0x220
> #define LCDC_AS_NEXT_BUF 0x230
>
> -#define CTRL_SFTRST (1 << 31)
> -#define CTRL_CLKGATE (1 << 30)
> -#define CTRL_BYPASS_COUNT (1 << 19)
> -#define CTRL_VSYNC_MODE (1 << 18)
> -#define CTRL_DOTCLK_MODE (1 << 17)
> -#define CTRL_DATA_SELECT (1 << 16)
> -#define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10)
> -#define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3)
> -#define CTRL_BUS_WIDTH_MASK (0x3 << 10)
> -#define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8)
> -#define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3)
> -#define CTRL_MASTER (1 << 5)
> -#define CTRL_DF16 (1 << 3)
> -#define CTRL_DF18 (1 << 2)
> -#define CTRL_DF24 (1 << 1)
> -#define CTRL_RUN (1 << 0)
> -
> -#define CTRL1_RECOVERY_ON_UNDERFLOW (1 << 24)
> -#define CTRL1_FIFO_CLEAR (1 << 21)
> -#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
> -#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
> -#define CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
> -#define CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
> -
> -#define CTRL2_OUTSTANDING_REQS__REQ_16 (4 << 21)
> +/* reg bit manipulation */
> +#define REG_MASK(e, s) (((1 << ((e) - (s) + 1)) - 1) << (s))
> +#define REG_PUT(x, e, s) (((x) << (s)) & REG_MASK(e, s))
> +#define REG_GET(x, e, s) (((x) & REG_MASK(e, s)) >> (s))
> +
> +#define SWIZZLE_LE 0 /* Little-Endian or No swap */
> +#define SWIZZLE_BE 1 /* Big-Endian or swap all */
> +#define SWIZZLE_HWD 2 /* Swap half-words */
> +#define SWIZZLE_HWD_BYTE 3 /* Swap bytes within each half-word */
> +
> +#define CTRL_SFTRST BIT(31)
> +#define CTRL_CLKGATE BIT(30)
> +#define CTRL_SHIFT_DIR(x) REG_PUT((x), 26, 26)
> +#define CTRL_SHIFT_NUM(x) REG_PUT((x), 25, 21)
> +#define CTRL_BYPASS_COUNT BIT(19)
> +#define CTRL_VSYNC_MODE BIT(18)
> +#define CTRL_DOTCLK_MODE BIT(17)
> +#define CTRL_DATA_SELECT BIT(16)
> +#define CTRL_INPUT_SWIZZLE(x) REG_PUT((x), 15, 14)
> +#define CTRL_CSC_SWIZZLE(x) REG_PUT((x), 13, 12)
> +#define CTRL_SET_BUS_WIDTH(x) REG_PUT((x), 11, 10)
> +#define CTRL_GET_BUS_WIDTH(x) REG_GET((x), 11, 10)
> +#define CTRL_BUS_WIDTH_MASK REG_PUT((0x3), 11, 10)
> +#define CTRL_SET_WORD_LENGTH(x) REG_PUT((x), 9, 8)
> +#define CTRL_GET_WORD_LENGTH(x) REG_GET((x), 9, 8)
> +#define CTRL_MASTER BIT(5)
> +#define CTRL_DF16 BIT(3)
> +#define CTRL_DF18 BIT(2)
> +#define CTRL_DF24 BIT(1)
> +#define CTRL_RUN BIT(0)
> +
> +#define CTRL1_RECOVERY_ON_UNDERFLOW BIT(24)
> +#define CTRL1_FIFO_CLEAR BIT(21)
> +#define CTRL1_SET_BYTE_PACKAGING(x) REG_PUT((x), 19, 16)
> +#define CTRL1_GET_BYTE_PACKAGING(x) REG_GET((x), 19, 16)
> +#define CTRL1_CUR_FRAME_DONE_IRQ_EN BIT(13)
> +#define CTRL1_CUR_FRAME_DONE_IRQ BIT(9)
> +
> +#define REQ_1 0
> +#define REQ_2 1
> +#define REQ_4 2
> +#define REQ_8 3
> +#define REQ_16 4
> +
> +#define CTRL2_OUTSTANDING_REQS(x) REG_PUT((x), 23, 21)
> +#define CTRL2_ODD_LINE_PATTERN(x) REG_PUT((x), 18, 16)
> +#define CTRL2_EVEN_LINE_PATTERN(x) REG_PUT((x), 14, 12)
>
> #define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
> #define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
> #define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff)
> #define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff)
>
> -#define VDCTRL0_ENABLE_PRESENT (1 << 28)
> -#define VDCTRL0_VSYNC_ACT_HIGH (1 << 27)
> -#define VDCTRL0_HSYNC_ACT_HIGH (1 << 26)
> -#define VDCTRL0_DOTCLK_ACT_FALLING (1 << 25)
> -#define VDCTRL0_ENABLE_ACT_HIGH (1 << 24)
> -#define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
> -#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
> -#define VDCTRL0_HALF_LINE (1 << 19)
> -#define VDCTRL0_HALF_LINE_MODE (1 << 18)
> +#define VDCTRL0_ENABLE_PRESENT BIT(28)
> +#define VDCTRL0_VSYNC_ACT_HIGH BIT(27)
> +#define VDCTRL0_HSYNC_ACT_HIGH BIT(26)
> +#define VDCTRL0_DOTCLK_ACT_FALLING BIT(25)
> +#define VDCTRL0_ENABLE_ACT_HIGH BIT(24)
> +#define VDCTRL0_VSYNC_PERIOD_UNIT BIT(21)
> +#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT BIT(20)
> +#define VDCTRL0_HALF_LINE BIT(19)
> +#define VDCTRL0_HALF_LINE_MODE BIT(18)
> #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
> #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
>
> #define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
> #define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
>
> -#define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
> -#define VDCTRL3_VSYNC_ONLY (1 << 28)
> +#define VDCTRL3_MUX_SYNC_SIGNALS BIT(29)
> +#define VDCTRL3_VSYNC_ONLY BIT(28)
> #define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16)
> #define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff)
> #define SET_VERT_WAIT_CNT(x) ((x) & 0xffff)
> @@ -103,7 +125,7 @@
>
> #define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */
> #define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */
> -#define VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
> +#define VDCTRL4_SYNC_SIGNALS_ON BIT(18)
> #define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff)
>
> #define DEBUG0_HSYNC (1 < 26)
> @@ -124,7 +146,7 @@
> #define STMLCDIF_18BIT 2 /* pixel data bus to the display is of 18 bit width */
> #define STMLCDIF_24BIT 3 /* pixel data bus to the display is of 24 bit width */
>
> -#define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
> -#define MXSFB_SYNC_DOTCLK_FALLING_ACT (1 << 7) /* negative edge sampling */
> +#define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT BIT(6)
> +#define MXSFB_SYNC_DOTCLK_FALLING_ACT BIT(7) /* negative edge sampling */
>
> #endif /* __MXSFB_REGS_H__ */
> --
> 2.7.4
>
> _______________________________________________
> dri-devel mailing list
> [email protected]
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

2019-01-14 16:46:33

by Guido Günther

[permalink] [raw]
Subject: Re: [PATCH 07/10] drm/mxsfb: Signal mode changed when bpp changed

Hi,
On Wed, Jan 09, 2019 at 02:13:47PM +0000, Robert Chiras wrote:
> From: Mirela Rabulea <[email protected]>
>
> Add mxsfb_atomic_helper_check to signal mode changed when bpp changed.
> This will trigger the execution of disable/enable on
> a modeset with different bpp than the current one.
>
> Signed-off-by: Mirela Rabulea <[email protected]>
> ---
> drivers/gpu/drm/mxsfb/mxsfb_drv.c | 48 ++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 47 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> index d3fb3a8..f528a37 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> @@ -115,9 +115,55 @@ void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb)
> clk_disable_unprepare(mxsfb->clk_axi);
> }
>
> +/**
> + * mxsfb_atomic_helper_check - validate state object
> + * @dev: DRM device
> + * @state: the driver state object
> + *
> + * On top of the drm imlementation drm_atomic_helper_check,
> + * check if the bpp is changed, if so, signal mode_changed,
> + * this will trigger disable/enable
> + *
> + * RETURNS:
> + * Zero for success or -errno
> + */
> +static int mxsfb_atomic_helper_check(struct drm_device *dev,
> + struct drm_atomic_state *state)
> +{
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *crtc_state;
> + int i, ret;
> +
> + ret = drm_atomic_helper_check(dev, state);
> + if (ret)
> + return ret;
> +
> + for_each_crtc_in_state(state, crtc, crtc_state, i) {

This does not exist anymore in recent drm, see
9ba29fcb76a559078491adffc74f66bf92b9dbea.
Cheers,
-- Guido

> + struct drm_plane_state *primary_state;
> + int old_bpp = 0;
> + int new_bpp = 0;
> +
> + if (!crtc->primary || !crtc->primary->old_fb)
> + continue;
> + primary_state =
> + drm_atomic_get_plane_state(state, crtc->primary);
> + if (!primary_state || !primary_state->fb)
> + continue;
> + old_bpp = crtc->primary->old_fb->format->depth;
> + new_bpp = primary_state->fb->format->depth;
> + if (old_bpp != new_bpp) {
> + crtc_state->mode_changed = true;
> + DRM_DEBUG_ATOMIC(
> + "[CRTC:%d:%s] mode changed, bpp %d->%d\n",
> + crtc->base.id, crtc->name, old_bpp, new_bpp);
> + }
> + }
> + return ret;
> +}
> +
> static const struct drm_mode_config_funcs mxsfb_mode_config_funcs = {
> .fb_create = drm_gem_fb_create,
> - .atomic_check = drm_atomic_helper_check,
> + .atomic_check = mxsfb_atomic_helper_check,
> .atomic_commit = drm_atomic_helper_commit,
> };
>
> --
> 2.7.4
>
> _______________________________________________
> dri-devel mailing list
> [email protected]
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

2019-01-15 09:59:26

by Robert Chiras

[permalink] [raw]
Subject: Re: [PATCH 09/10] drm/mxsfb: Improve the axi clock usage

On Mi, 2019-01-09 at 18:09 +0100, Stefan Agner wrote:
> On 09.01.2019 15:13, Robert Chiras wrote:
> >
> > Currently, the enable of the axi clock return status is ignored,
> > causing
> > issues when the enable fails then we try to disable it. Therefore,
> > it is
> > better to check the return status and disable it only when enable
> > succeeded.
> > Also, remove the helper functions around clk_axi, since we can
> > directly
> > use the clk API function for enable/disable the clock. Those
> > functions
> > are already checking for NULL clk and returning 0 if that's the
> > case.
> Can we maybe even use the runtime PM system for that (adding two
> callbacks for SET_RUNTIME_PM_OPS)?
>
> I suggested it a while ago, but did not looked deeper into it:
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flk
> ml.org%2Flkml%2F2018%2F8%2F1%2F300&amp;data=02%7C01%7Crobert.chiras%4
> 0nxp.com%7Cfb15abdd151b4c643f4f08d67655464a%7C686ea1d3bc2b4c6fa92cd99
> c5c301635%7C0%7C0%7C636826505961622511&amp;sdata=MxpNiBXFW6gw9U8rKRF2
> 0ji73tZ5X5GqZWcninDBFWk%3D&amp;reserved=0
>
> Since we basically enable on mxsfb_crtc_enable and disable on
> mxsfb_crtc_disable, I think it would be pretty much the same thing.
>
> --
> Stefan
>

Hi Stefan,

I don't think I fully understand your suggestion here. The axi clock is
used when we are trying to access LCDIF registers while the block is
not running. For example, when the vblank needs to be enabled/disabled
while the block is idle (so it doesn't have anything to do with
mxsfb_crtc_enable/disable). How could the PM callbacks handle this
case?

Thanks,
Robert

>
> >
> >
> > Signed-off-by: Robert Chiras <[email protected]>
> > Acked-by: Leonard Crestez <[email protected]>
> > ---
> >  drivers/gpu/drm/mxsfb/mxsfb_crtc.c |  8 ++++----
> >  drivers/gpu/drm/mxsfb/mxsfb_drv.c  | 32 +++++++++++++-------------
> > ------
> >  drivers/gpu/drm/mxsfb/mxsfb_drv.h  |  3 ---
> >  3 files changed, 17 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> > b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> > index 8d1b6a6..b9437c7 100644
> > --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> > +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
> > @@ -411,7 +411,7 @@ void mxsfb_crtc_enable(struct mxsfb_drm_private
> > *mxsfb)
> >  {
> >   dma_addr_t paddr;
> >  
> > - mxsfb_enable_axi_clk(mxsfb);
> > + clk_prepare_enable(mxsfb->clk_axi);
> >   writel(0, mxsfb->base + LCDC_CTRL);
> >   mxsfb_crtc_mode_set_nofb(mxsfb);
> >  
> > @@ -428,7 +428,7 @@ void mxsfb_crtc_enable(struct mxsfb_drm_private
> > *mxsfb)
> >  void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb)
> >  {
> >   mxsfb_disable_controller(mxsfb);
> > - mxsfb_disable_axi_clk(mxsfb);
> > + clk_disable_unprepare(mxsfb->clk_axi);
> >  }
> >  
> >  void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
> > @@ -456,9 +456,9 @@ void mxsfb_plane_atomic_update(struct
> > mxsfb_drm_private *mxsfb,
> >  
> >   paddr = mxsfb_get_fb_paddr(mxsfb);
> >   if (paddr) {
> > - mxsfb_enable_axi_clk(mxsfb);
> > + clk_prepare_enable(mxsfb->clk_axi);
> >   writel(paddr, mxsfb->base + mxsfb->devdata-
> > >next_buf);
> > - mxsfb_disable_axi_clk(mxsfb);
> > + clk_disable_unprepare(mxsfb->clk_axi);
> >   }
> >  
> >   if (!fb || !old_fb)
> > diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> > b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> > index 135b8e1..5e18353 100644
> > --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> > +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> > @@ -103,18 +103,6 @@ drm_pipe_to_mxsfb_drm_private(struct
> > drm_simple_display_pipe *pipe)
> >   return container_of(pipe, struct mxsfb_drm_private, pipe);
> >  }
> >  
> > -void mxsfb_enable_axi_clk(struct mxsfb_drm_private *mxsfb)
> > -{
> > - if (mxsfb->clk_axi)
> > - clk_prepare_enable(mxsfb->clk_axi);
> > -}
> > -
> > -void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb)
> > -{
> > - if (mxsfb->clk_axi)
> > - clk_disable_unprepare(mxsfb->clk_axi);
> > -}
> > -
> >  /**
> >   * mxsfb_atomic_helper_check - validate state object
> >   * @dev: DRM device
> > @@ -237,25 +225,31 @@ static void mxsfb_pipe_update(struct
> > drm_simple_display_pipe *pipe,
> >  static int mxsfb_pipe_enable_vblank(struct drm_simple_display_pipe
> > *pipe)
> >  {
> >   struct mxsfb_drm_private *mxsfb =
> > drm_pipe_to_mxsfb_drm_private(pipe);
> > + int ret = 0;
> > +
> > + ret = clk_prepare_enable(mxsfb->clk_axi);
> > + if (ret)
> > + return ret;
> >  
> >   /* Clear and enable VBLANK IRQ */
> > - mxsfb_enable_axi_clk(mxsfb);
> >   writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1
> > + REG_CLR);
> >   writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base +
> > LCDC_CTRL1 + REG_SET);
> > - mxsfb_disable_axi_clk(mxsfb);
> > + clk_disable_unprepare(mxsfb->clk_axi);
> >  
> > - return 0;
> > + return ret;
> >  }
> >  
> >  static void mxsfb_pipe_disable_vblank(struct
> > drm_simple_display_pipe *pipe)
> >  {
> >   struct mxsfb_drm_private *mxsfb =
> > drm_pipe_to_mxsfb_drm_private(pipe);
> >  
> > + if (clk_prepare_enable(mxsfb->clk_axi))
> > + return;
> > +
> >   /* Disable and clear VBLANK IRQ */
> > - mxsfb_enable_axi_clk(mxsfb);
> >   writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base +
> > LCDC_CTRL1 + REG_CLR);
> >   writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1
> > + REG_CLR);
> > - mxsfb_disable_axi_clk(mxsfb);
> > + clk_disable_unprepare(mxsfb->clk_axi);
> >  }
> >  
> >  static struct drm_simple_display_pipe_funcs mxsfb_funcs = {
> > @@ -440,7 +434,7 @@ static irqreturn_t mxsfb_irq_handler(int irq,
> > void *data)
> >   struct mxsfb_drm_private *mxsfb = drm->dev_private;
> >   u32 reg;
> >  
> > - mxsfb_enable_axi_clk(mxsfb);
> > + clk_prepare_enable(mxsfb->clk_axi);
> >  
> >   reg = readl(mxsfb->base + LCDC_CTRL1);
> >  
> > @@ -449,7 +443,7 @@ static irqreturn_t mxsfb_irq_handler(int irq,
> > void *data)
> >  
> >   writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1
> > + REG_CLR);
> >  
> > - mxsfb_disable_axi_clk(mxsfb);
> > + clk_disable_unprepare(mxsfb->clk_axi);
> >  
> >   return IRQ_HANDLED;
> >  }
> > diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> > b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> > index c15b4f9..ce98411 100644
> > --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> > +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.h
> > @@ -47,9 +47,6 @@ struct mxsfb_drm_private {
> >  int mxsfb_setup_crtc(struct drm_device *dev);
> >  int mxsfb_create_output(struct drm_device *dev);
> >  
> > -void mxsfb_enable_axi_clk(struct mxsfb_drm_private *mxsfb);
> > -void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb);
> > -
> >  void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb);
> >  void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb);
> >  void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,