Freescale MMDC (Multi Mode DDR Controller) driver is supported
since i.MX6Q, but not yet documented, this patch adds binding
doc for MMDC module driver.
Signed-off-by: Anson Huang <[email protected]>
---
.../bindings/memory-controllers/fsl/mmdc.txt | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
new file mode 100644
index 0000000..5b5a224
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
@@ -0,0 +1,27 @@
+Freescale Multi Mode DDR controller (MMDC)
+
+Required properties :
+- compatible : should be one of following:
+ for i.MX6Q/i.MX6DL:
+ - "fsl,imx6q-mmdc";
+ for i.MX6SL:
+ - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
+ for i.MX6SLL:
+ - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
+ for i.MX6SX:
+ - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
+ for i.MX6UL/i.MX6ULL/i.MX6ULZ:
+ - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
+ for i.MX7ULP:
+ - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
+- reg : address and size of MMDC DDR controller registers
+
+Optional properties :
+- clocks : the clock provided by the SoC to access the MMDC registers
+
+Example :
+ mmdc0: mmdc@21b0000 { /* MMDC0 */
+ compatible = "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
+ };
--
2.7.4
i.MX7ULP has a MMDC module to control DDR, it reuses
i.MX6Q's MMDC module, add support for it.
Signed-off-by: Anson Huang <[email protected]>
---
arch/arm/boot/dts/imx7ulp.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index fca6e50..fca4a01 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -286,6 +286,12 @@
status = "disabled";
};
+ mmdc: mmdc@40ab0000 {
+ compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x40ab0000 0x1000>;
+ clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
+ };
+
iomuxc1: pinctrl@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
--
2.7.4
Hi Anson,
On Wed, Feb 27, 2019 at 7:08 AM Anson Huang <[email protected]> wrote:
> +Example :
> + mmdc0: mmdc@21b0000 { /* MMDC0 */
Node names should be generic, so:
memory-controller@21b0000
On Wed, Feb 27, 2019 at 7:08 AM Anson Huang <[email protected]> wrote:
> diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
> index fca6e50..fca4a01 100644
> --- a/arch/arm/boot/dts/imx7ulp.dtsi
> +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> @@ -286,6 +286,12 @@
> status = "disabled";
> };
>
> + mmdc: mmdc@40ab0000 {
Node names should be generic, so:
memory-controller@40ab0000
Hi, Fabio
Best Regards!
Anson Huang
> -----Original Message-----
> From: Fabio Estevam [mailto:[email protected]]
> Sent: 2019年2月28日 3:50
> To: Anson Huang <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; dl-linux-imx <[email protected]>
> Subject: Re: [PATCH 2/2] ARM: dts: imx7ulp: add mmdc support
>
> On Wed, Feb 27, 2019 at 7:08 AM Anson Huang <[email protected]>
> wrote:
>
> > diff --git a/arch/arm/boot/dts/imx7ulp.dtsi
> > b/arch/arm/boot/dts/imx7ulp.dtsi index fca6e50..fca4a01 100644
> > --- a/arch/arm/boot/dts/imx7ulp.dtsi
> > +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> > @@ -286,6 +286,12 @@
> > status = "disabled";
> > };
> >
> > + mmdc: mmdc@40ab0000 {
>
> Node names should be generic, so:
>
> memory-controller@40ab0000
Thanks, I also update other i.MX SoC's MMDC node name in V2 patch series.
Anson.