Add IMX8MQ_CLK_HDMI_PHY_27M clock for i.MX8MQ clock tree.
Signed-off-by: Anson Huang <[email protected]>
---
include/dt-bindings/clock/imx8mq-clock.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index b58cc64..f50ef4e9 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -400,5 +400,7 @@
#define IMX8MQ_CLK_GPIO4_ROOT 273
#define IMX8MQ_CLK_GPIO5_ROOT 274
-#define IMX8MQ_CLK_END 275
+#define IMX8MQ_CLK_HDMI_PHY_27M 275
+
+#define IMX8MQ_CLK_END 276
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
--
2.7.4
There is another 27MHz OSC inside i.MX8MQ's display block and
it can be one of reference clocks of all PLLs, add it into clock
tree and also add it as PLL's reference clock.
Signed-off-by: Anson Huang <[email protected]>
---
drivers/clk/imx/clk-imx8mq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index a9b3888..bb1bf9b 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -26,7 +26,7 @@ static u32 share_count_nand;
static struct clk *clks[IMX8MQ_CLK_END];
-static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "osc_hdmi_phy_27m", "dummy", };
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
@@ -281,6 +281,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(np, "ckil");
clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(np, "osc_25m");
clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(np, "osc_27m");
+ clks[IMX8MQ_CLK_HDMI_PHY_27M] = of_clk_get_by_name(np, "osc_hdmi_phy_27m");
clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
--
2.7.4
Add new fixed clock osc_hdmi_phy_27m.
Signed-off-by: Anson Huang <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 8e9d6d5..fbcdd4d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -48,6 +48,13 @@
clock-output-names = "osc_27m";
};
+ osc_hdmi_phy_27m: clock-osc-hdmi-phy-27m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names = "osc_hdmi_phy_27m";
+ };
+
clk_ext1: clock-ext1 {
compatible = "fixed-clock";
#clock-cells = <0>;
--
2.7.4
Am Donnerstag, den 07.03.2019, 03:41 +0000 schrieb Anson Huang:
> There is another 27MHz OSC inside i.MX8MQ's display block and
> it can be one of reference clocks of all PLLs, add it into clock
> tree and also add it as PLL's reference clock.
>
> Signed-off-by: Anson Huang <[email protected]>
> ---
> drivers/clk/imx/clk-imx8mq.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index a9b3888..bb1bf9b 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -26,7 +26,7 @@ static u32 share_count_nand;
>
> static struct clk *clks[IMX8MQ_CLK_END];
>
> -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
> +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "osc_hdmi_phy_27m", "dummy", };
> static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
> static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
> @@ -281,6 +281,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
> clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(np, "ckil");
> clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(np, "osc_25m");
> clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(np, "osc_27m");
> + clks[IMX8MQ_CLK_HDMI_PHY_27M] = of_clk_get_by_name(np, "osc_hdmi_phy_27m");
This is not acceptable. This adds a new required clock input, without
bothering to add the corresponding binding information or thinking
about backwards compatibility. At this point there are existing DTs out
there, which don't provide this required clock, which will cause a full
boot regression. This can only be an optional clock input at this
point.
Regards,
Lucas
> clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
> clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
> clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
Hi, Lucas
Best Regards!
Anson Huang
> -----Original Message-----
> From: Lucas Stach [mailto:[email protected]]
> Sent: 2019年3月7日 20:06
> To: Anson Huang <[email protected]>; [email protected];
> [email protected]; [email protected]; Fabio Estevam
> <[email protected]>; [email protected]; [email protected];
> [email protected]; [email protected]; Abel Vesa
> <[email protected]>; [email protected]; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Cc: dl-linux-imx <[email protected]>
> Subject: Re: [PATCH 2/3] clk: imx8mq: add hdmi_phy_27m clock as pll's
> reference clock
>
> Am Donnerstag, den 07.03.2019, 03:41 +0000 schrieb Anson Huang:
> > There is another 27MHz OSC inside i.MX8MQ's display block and it can
> > be one of reference clocks of all PLLs, add it into clock tree and
> > also add it as PLL's reference clock.
> >
> > Signed-off-by: Anson Huang <[email protected]>
> > ---
> > drivers/clk/imx/clk-imx8mq.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mq.c
> > b/drivers/clk/imx/clk-imx8mq.c index a9b3888..bb1bf9b 100644
> > --- a/drivers/clk/imx/clk-imx8mq.c
> > +++ b/drivers/clk/imx/clk-imx8mq.c
> > @@ -26,7 +26,7 @@ static u32 share_count_nand;
> >
> > static struct clk *clks[IMX8MQ_CLK_END];
> >
> > -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m",
> > "dummy", "dummy", };
> > +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m",
> > +"osc_hdmi_phy_27m", "dummy", };
> > static const char * const arm_pll_bypass_sels[] = {"arm_pll",
> > "arm_pll_ref_sel", };
> > static const char * const gpu_pll_bypass_sels[] = {"gpu_pll",
> > "gpu_pll_ref_sel", };
> > static const char * const vpu_pll_bypass_sels[] = {"vpu_pll",
> > "vpu_pll_ref_sel", }; @@ -281,6 +281,7 @@ static int
> imx8mq_clocks_probe(struct platform_device *pdev)
> > clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(np, "ckil");
> > clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(np, "osc_25m");
> > clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(np, "osc_27m");
> > + clks[IMX8MQ_CLK_HDMI_PHY_27M] = of_clk_get_by_name(np,
> > +"osc_hdmi_phy_27m");
>
> This is not acceptable. This adds a new required clock input, without
> bothering to add the corresponding binding information or thinking about
> backwards compatibility. At this point there are existing DTs out there, which
> don't provide this required clock, which will cause a full boot regression. This
> can only be an optional clock input at this point.
What do you think if we don't get such clock from DT? Just register this fixed clock
in clock driver directly, then there will be no dependency of DT.
Anson.
>
> Regards,
> Lucas
>
> > clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
> > clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
> > clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
Am Donnerstag, den 07.03.2019, 12:56 +0000 schrieb Anson Huang:
> Hi, Lucas
>
> Best Regards!
> Anson Huang
>
> > -----Original Message-----
> > > > From: Lucas Stach [mailto:[email protected]]
> > Sent: 2019年3月7日 20:06
> > > > > > To: Anson Huang <[email protected]>; [email protected];
> > > > [email protected]; [email protected]; Fabio Estevam
> > > > > > > > <[email protected]>; [email protected]; [email protected];
> > > > [email protected]; [email protected]; Abel Vesa
> > > > > > <[email protected]>; [email protected]; linux-arm-
> > > > [email protected]; [email protected]; linux-
> > [email protected]; [email protected]
> > > > Cc: dl-linux-imx <[email protected]>
> > Subject: Re: [PATCH 2/3] clk: imx8mq: add hdmi_phy_27m clock as pll's
> > reference clock
> >
> > Am Donnerstag, den 07.03.2019, 03:41 +0000 schrieb Anson Huang:
> > > There is another 27MHz OSC inside i.MX8MQ's display block and it can
> > > be one of reference clocks of all PLLs, add it into clock tree and
> > > also add it as PLL's reference clock.
> > >
> > > > > > Signed-off-by: Anson Huang <[email protected]>
> > > ---
> > > drivers/clk/imx/clk-imx8mq.c | 3 ++-
> > > 1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/imx/clk-imx8mq.c
> > > b/drivers/clk/imx/clk-imx8mq.c index a9b3888..bb1bf9b 100644
> > > --- a/drivers/clk/imx/clk-imx8mq.c
> > > +++ b/drivers/clk/imx/clk-imx8mq.c
> > > @@ -26,7 +26,7 @@ static u32 share_count_nand;
> > >
> > > static struct clk *clks[IMX8MQ_CLK_END];
> > >
> > > -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m",
> > > "dummy", "dummy", };
> > > +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m",
> > > +"osc_hdmi_phy_27m", "dummy", };
> > > static const char * const arm_pll_bypass_sels[] = {"arm_pll",
> > > "arm_pll_ref_sel", };
> > > static const char * const gpu_pll_bypass_sels[] = {"gpu_pll",
> > > "gpu_pll_ref_sel", };
> > > static const char * const vpu_pll_bypass_sels[] = {"vpu_pll",
> > > "vpu_pll_ref_sel", }; @@ -281,6 +281,7 @@ static int
> >
> > imx8mq_clocks_probe(struct platform_device *pdev)
> > > > > > clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(np, "ckil");
> > > > > > clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(np, "osc_25m");
> > > > > > clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(np, "osc_27m");
> > > > > > + clks[IMX8MQ_CLK_HDMI_PHY_27M] = of_clk_get_by_name(np,
> > > +"osc_hdmi_phy_27m");
> >
> > This is not acceptable. This adds a new required clock input, without
> > bothering to add the corresponding binding information or thinking about
> > backwards compatibility. At this point there are existing DTs out there, which
> > don't provide this required clock, which will cause a full boot regression. This
> > can only be an optional clock input at this point.
>
> What do you think if we don't get such clock from DT? Just register this fixed clock
> in clock driver directly, then there will be no dependency of DT.
I don't think that's a good idea, as there can probably be use-cases
where having the XTAL unpopulated is actually a valid system
configuration, so not having this clock must be valid for the CCM
driver.
Regards,
Lucas
On Thu, 7 Mar 2019 03:40:57 +0000, Anson Huang wrote:
> Add IMX8MQ_CLK_HDMI_PHY_27M clock for i.MX8MQ clock tree.
>
> Signed-off-by: Anson Huang <[email protected]>
> ---
> include/dt-bindings/clock/imx8mq-clock.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <[email protected]>