Add optional dt property to tune maximum desired analog clock rate.
Fabrice Gasnier (2):
dt-bindings: iio: stm32-adc: add max clock rate property
iio: adc: stm32: allow to tune analog clock
.../devicetree/bindings/iio/adc/st,stm32-adc.txt | 2 ++
drivers/iio/adc/stm32-adc-core.c | 16 +++++++++++++---
2 files changed, 15 insertions(+), 3 deletions(-)
--
2.7.4
Add new optional dt property to tune analog clock prescaler.
Driver looks for optional "st,max-clk-rate-hz", then computes
best approximation below that rate, using ADC internal prescaler.
Signed-off-by: Fabrice Gasnier <[email protected]>
---
drivers/iio/adc/stm32-adc-core.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
index 20c626c..6537f4f 100644
--- a/drivers/iio/adc/stm32-adc-core.c
+++ b/drivers/iio/adc/stm32-adc-core.c
@@ -79,6 +79,7 @@ struct stm32_adc_priv_cfg {
* @domain: irq domain reference
* @aclk: clock reference for the analog circuitry
* @bclk: bus clock common for all ADCs, depends on part used
+ * @max_clk_rate: desired maximum clock rate
* @booster: booster supply reference
* @vdd: vdd supply reference
* @vdda: vdda analog supply reference
@@ -95,6 +96,7 @@ struct stm32_adc_priv {
struct irq_domain *domain;
struct clk *aclk;
struct clk *bclk;
+ u32 max_clk_rate;
struct regulator *booster;
struct regulator *vdd;
struct regulator *vdda;
@@ -141,7 +143,7 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
}
for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
- if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
+ if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
break;
}
if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
@@ -230,7 +232,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
if (ckmode)
continue;
- if ((rate / div) <= priv->cfg->max_clk_rate_hz)
+ if ((rate / div) <= priv->max_clk_rate)
goto out;
}
}
@@ -250,7 +252,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
if (!ckmode)
continue;
- if ((rate / div) <= priv->cfg->max_clk_rate_hz)
+ if ((rate / div) <= priv->max_clk_rate)
goto out;
}
@@ -655,6 +657,7 @@ static int stm32_adc_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = pdev->dev.of_node;
struct resource *res;
+ u32 max_rate;
int ret;
if (!pdev->dev.of_node)
@@ -731,6 +734,13 @@ static int stm32_adc_probe(struct platform_device *pdev)
priv->common.vref_mv = ret / 1000;
dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
+ ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
+ &max_rate);
+ if (!ret)
+ priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
+ else
+ priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
+
ret = priv->cfg->clk_sel(pdev, priv);
if (ret < 0)
goto err_hw_stop;
--
2.7.4
Add optional dt property to tune maximum desired analog clock rate.
Signed-off-by: Fabrice Gasnier <[email protected]>
---
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
index 4c0da8c..8de9331 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
@@ -53,6 +53,8 @@ Optional properties:
analog input switches on stm32mp1.
- st,syscfg: Phandle to system configuration controller. It can be used to
control the analog circuitry on stm32mp1.
+- st,max-clk-rate-hz: Allow to specify desired max clock rate used by analog
+ circuitry.
Contents of a stm32 adc child node:
-----------------------------------
--
2.7.4
On Mon, 28 Oct 2019 17:11:48 +0100
Fabrice Gasnier <[email protected]> wrote:
> Add new optional dt property to tune analog clock prescaler.
> Driver looks for optional "st,max-clk-rate-hz", then computes
> best approximation below that rate, using ADC internal prescaler.
>
> Signed-off-by: Fabrice Gasnier <[email protected]>
If the previous email I wrote on this got to anyone before I hit
cancel, please ignore. Had completely failed to read the code correctly.
Anyhow this seems fine to me, but given there are a lot of existing
clk related bindings I'd like to give a little longer for Rob to
have a chance to take a look at the binding.
Give me a poke if I seem to have lost this in a week or so.
Thanks,
Jonathan
> ---
> drivers/iio/adc/stm32-adc-core.c | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
> index 20c626c..6537f4f 100644
> --- a/drivers/iio/adc/stm32-adc-core.c
> +++ b/drivers/iio/adc/stm32-adc-core.c
> @@ -79,6 +79,7 @@ struct stm32_adc_priv_cfg {
> * @domain: irq domain reference
> * @aclk: clock reference for the analog circuitry
> * @bclk: bus clock common for all ADCs, depends on part used
> + * @max_clk_rate: desired maximum clock rate
> * @booster: booster supply reference
> * @vdd: vdd supply reference
> * @vdda: vdda analog supply reference
> @@ -95,6 +96,7 @@ struct stm32_adc_priv {
> struct irq_domain *domain;
> struct clk *aclk;
> struct clk *bclk;
> + u32 max_clk_rate;
> struct regulator *booster;
> struct regulator *vdd;
> struct regulator *vdda;
> @@ -141,7 +143,7 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
> }
>
> for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
> - if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
> + if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
> break;
> }
> if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
> @@ -230,7 +232,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
> if (ckmode)
> continue;
>
> - if ((rate / div) <= priv->cfg->max_clk_rate_hz)
> + if ((rate / div) <= priv->max_clk_rate)
> goto out;
> }
> }
> @@ -250,7 +252,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
> if (!ckmode)
> continue;
>
> - if ((rate / div) <= priv->cfg->max_clk_rate_hz)
> + if ((rate / div) <= priv->max_clk_rate)
> goto out;
> }
>
> @@ -655,6 +657,7 @@ static int stm32_adc_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> struct device_node *np = pdev->dev.of_node;
> struct resource *res;
> + u32 max_rate;
> int ret;
>
> if (!pdev->dev.of_node)
> @@ -731,6 +734,13 @@ static int stm32_adc_probe(struct platform_device *pdev)
> priv->common.vref_mv = ret / 1000;
> dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
>
> + ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
> + &max_rate);
> + if (!ret)
> + priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
> + else
> + priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
> +
> ret = priv->cfg->clk_sel(pdev, priv);
> if (ret < 0)
> goto err_hw_stop;
On Mon, 28 Oct 2019 17:11:47 +0100, Fabrice Gasnier wrote:
> Add optional dt property to tune maximum desired analog clock rate.
>
> Signed-off-by: Fabrice Gasnier <[email protected]>
> ---
> Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, 5 Nov 2019 21:29:17 -0600
Rob Herring <[email protected]> wrote:
> On Mon, 28 Oct 2019 17:11:47 +0100, Fabrice Gasnier wrote:
> > Add optional dt property to tune maximum desired analog clock rate.
> >
> > Signed-off-by: Fabrice Gasnier <[email protected]>
> > ---
> > Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt | 2 ++
> > 1 file changed, 2 insertions(+)
> >
>
> Reviewed-by: Rob Herring <[email protected]>
Applied to the togreg branch of iio.git. Whether I get a pull request
out for this cycle or this hits early in next is dependent on whether
Linus hints at an rc8 and gives an extra week.
Thanks,
Jonathan
On Sun, 3 Nov 2019 12:30:42 +0000
Jonathan Cameron <[email protected]> wrote:
> On Mon, 28 Oct 2019 17:11:48 +0100
> Fabrice Gasnier <[email protected]> wrote:
>
> > Add new optional dt property to tune analog clock prescaler.
> > Driver looks for optional "st,max-clk-rate-hz", then computes
> > best approximation below that rate, using ADC internal prescaler.
> >
> > Signed-off-by: Fabrice Gasnier <[email protected]>
> If the previous email I wrote on this got to anyone before I hit
> cancel, please ignore. Had completely failed to read the code correctly.
>
> Anyhow this seems fine to me, but given there are a lot of existing
> clk related bindings I'd like to give a little longer for Rob to
> have a chance to take a look at the binding.
>
> Give me a poke if I seem to have lost this in a week or so.
Applied to the togreg branch of iio.git. Shortly to be pushed out
as testing for the autobuilders to poke at it.
Thanks,
Jonathan
>
> Thanks,
>
> Jonathan
>
>
>
> > ---
> > drivers/iio/adc/stm32-adc-core.c | 16 +++++++++++++---
> > 1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
> > index 20c626c..6537f4f 100644
> > --- a/drivers/iio/adc/stm32-adc-core.c
> > +++ b/drivers/iio/adc/stm32-adc-core.c
> > @@ -79,6 +79,7 @@ struct stm32_adc_priv_cfg {
> > * @domain: irq domain reference
> > * @aclk: clock reference for the analog circuitry
> > * @bclk: bus clock common for all ADCs, depends on part used
> > + * @max_clk_rate: desired maximum clock rate
> > * @booster: booster supply reference
> > * @vdd: vdd supply reference
> > * @vdda: vdda analog supply reference
> > @@ -95,6 +96,7 @@ struct stm32_adc_priv {
> > struct irq_domain *domain;
> > struct clk *aclk;
> > struct clk *bclk;
> > + u32 max_clk_rate;
> > struct regulator *booster;
> > struct regulator *vdd;
> > struct regulator *vdda;
> > @@ -141,7 +143,7 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
> > }
> >
> > for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
> > - if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
> > + if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
> > break;
> > }
> > if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
> > @@ -230,7 +232,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
> > if (ckmode)
> > continue;
> >
> > - if ((rate / div) <= priv->cfg->max_clk_rate_hz)
> > + if ((rate / div) <= priv->max_clk_rate)
> > goto out;
> > }
> > }
> > @@ -250,7 +252,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
> > if (!ckmode)
> > continue;
> >
> > - if ((rate / div) <= priv->cfg->max_clk_rate_hz)
> > + if ((rate / div) <= priv->max_clk_rate)
> > goto out;
> > }
> >
> > @@ -655,6 +657,7 @@ static int stm32_adc_probe(struct platform_device *pdev)
> > struct device *dev = &pdev->dev;
> > struct device_node *np = pdev->dev.of_node;
> > struct resource *res;
> > + u32 max_rate;
> > int ret;
> >
> > if (!pdev->dev.of_node)
> > @@ -731,6 +734,13 @@ static int stm32_adc_probe(struct platform_device *pdev)
> > priv->common.vref_mv = ret / 1000;
> > dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
> >
> > + ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
> > + &max_rate);
> > + if (!ret)
> > + priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
> > + else
> > + priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
> > +
> > ret = priv->cfg->clk_sel(pdev, priv);
> > if (ret < 0)
> > goto err_hw_stop;
>