Added QUSB2 PHY support for SC7180.
Converting dt binding to yaml.
Adding compatible for SC7180 in dt bindings.
Changes in v3:
*Using the generic phy cfg table for QUSB2 V2 phy.
*Added support for overriding tuning parameters in QUSB2 V2 PHY
from device tree.
Changes in v2:
Sorted the compatible in driver.
Converted dt binding to yaml.
Added compatible in yaml.
Sandeep Maheswaram (5):
phy: qcom-qusb2: Add QUSB2 PHY support for SC7180
dt-bindings: phy: qcom,qusb2: Convert QUSB2 phy bindings to yaml
dt-bindings: phy: qcom-qusb2: Add support for overriding Phy tuning
parameters
phy: qcom-qusb2: Add support for overriding tuning parameters in QUSB2
V2 PHY
arm64: dts: qcom: sc7180: Update QUSB2 V2 Phy tuning params for SC7180
.../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 185 +++++++++++++++++++++
.../devicetree/bindings/phy/qcom-qusb2-phy.txt | 68 --------
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 6 +-
drivers/phy/qualcomm/phy-qcom-qusb2.c | 73 +++++++-
4 files changed, 254 insertions(+), 78 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Convert QUSB2 phy bindings to DT schema format using json-schema.
Signed-off-by: Sandeep Maheswaram <[email protected]>
---
.../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 152 +++++++++++++++++++++
.../devicetree/bindings/phy/qcom-qusb2-phy.txt | 68 ---------
2 files changed, 152 insertions(+), 68 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
new file mode 100644
index 0000000..83cd01d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm QUSB2 phy controller
+
+maintainers:
+ - Manu Gautam <[email protected]>
+
+description:
+ QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
+
+properties:
+ compatible:
+ anyOf:
+ - items:
+ - const: qcom,msm8996-qusb2-phy
+ - items:
+ - const: qcom,msm8998-qusb2-phy
+ - items:
+ - const: qcom,sc7180-qusb2-phy
+ - items:
+ - const: qcom,sdm845-qusb2-phy
+ - items:
+ - enum:
+ - qcom,sc7180-qusb2-phy
+ - qcom,sdm845-qusb2-phy
+ - const: qcom,qusb2-v2-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ minItems: 2
+ items:
+ - description: phy config clock
+ - description: 19.2 MHz ref clk
+ - description: phy interface clock (Optional)
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: cfg_ahb
+ - const: ref
+ - const: iface
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ vdda-phy-dpdm-supply:
+ description:
+ Phandle to 3.1V regulator supply to Dp/Dm port signals.
+
+ resets:
+ maxItems: 1
+
+ nvmem-cells:
+ maxItems: 1
+ description:
+ Phandle to nvmem cell that contains 'HS Tx trim'
+ tuning parameter value for qusb2 phy.
+
+ qcom,tcsr-syscon:
+ description:
+ Phandle to TCSR syscon register region.
+ $ref: /schemas/types.yaml#/definitions/cell
+
+ qcom,imp-res-offset-value:
+ description:
+ It is a 6 bit value that specifies offset to be
+ added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
+ tuning parameter that may vary for different boards of same SOC.
+ This property is applicable to only QUSB2 v2 PHY.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ maximum: 63
+ default: 0
+
+ qcom,hstx-trim-value:
+ description:
+ It is a 4 bit value that specifies tuning for HSTX
+ output current.
+ Possible range is - 15mA to 24mA (stepsize of 600 uA).
+ See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
+ This property is applicable to only QUSB2 v2 PHY.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ maximum: 15
+ default: 3
+
+ qcom,preemphasis-level:
+ description:
+ It is a 2 bit value that specifies pre-emphasis level.
+ Possible range is 0 to 15% (stepsize of 5%).
+ See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
+ This property is applicable to only QUSB2 v2 PHY.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ maximum: 3
+ default: 2
+
+ qcom,preemphasis-width:
+ description:
+ It is a 1 bit value that specifies how long the HSTX
+ pre-emphasis (specified using qcom,preemphasis-level) must be in
+ effect. Duration could be half-bit of full-bit.
+ See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
+ This property is applicable to only QUSB2 v2 PHY.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ maximum: 1
+ default: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - vdda-pll-supply
+ - vdda-phy-dpdm-supply
+ - resets
+
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ usb_1_hsphy: phy@88e2000 {
+ compatible = "qcom,sdm845-qusb2-phy";
+ reg = <0 0x088e2000 0 0x400>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ nvmem-cells = <&qusb2p_hstx_trim>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
deleted file mode 100644
index fe29f9e..0000000
--- a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-Qualcomm QUSB2 phy controller
-=============================
-
-QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
-
-Required properties:
- - compatible: compatible list, contains
- "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
- "qcom,msm8998-qusb2-phy" for 10nm PHY on msm8998,
- "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
-
- - reg: offset and length of the PHY register set.
- - #phy-cells: must be 0.
-
- - clocks: a list of phandles and clock-specifier pairs,
- one for each entry in clock-names.
- - clock-names: must be "cfg_ahb" for phy config clock,
- "ref" for 19.2 MHz ref clk,
- "iface" for phy interface clock (Optional).
-
- - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
- - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
-
- - resets: Phandle to reset to phy block.
-
-Optional properties:
- - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
- tuning parameter value for qusb2 phy.
-
- - qcom,tcsr-syscon: Phandle to TCSR syscon register region.
- - qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be
- added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
- tuning parameter that may vary for different boards of same SOC.
- This property is applicable to only QUSB2 v2 PHY (sdm845).
- - qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX
- output current.
- Possible range is - 15mA to 24mA (stepsize of 600 uA).
- See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
- This property is applicable to only QUSB2 v2 PHY (sdm845).
- Default value is 22.2mA for sdm845.
- - qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level.
- Possible range is 0 to 15% (stepsize of 5%).
- See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
- This property is applicable to only QUSB2 v2 PHY (sdm845).
- Default value is 10% for sdm845.
-- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX
- pre-emphasis (specified using qcom,preemphasis-level) must be in
- effect. Duration could be half-bit of full-bit.
- See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
- This property is applicable to only QUSB2 v2 PHY (sdm845).
- Default value is full-bit width for sdm845.
-
-Example:
- hsusb_phy: phy@7411000 {
- compatible = "qcom,msm8996-qusb2-phy";
- reg = <0x7411000 0x180>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_RX1_USB2_CLKREF_CLK>,
- clock-names = "cfg_ahb", "ref";
-
- vdda-pll-supply = <&pm8994_l12>;
- vdda-phy-dpdm-supply = <&pm8994_l24>;
-
- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
- nvmem-cells = <&qusb2p_hstx_trim>;
- };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add support for overriding tuning parameters in QUSB2 V2 PHY
bias-ctrl-value,charge-ctrl-value and hsdisc-trim-value.
Signed-off-by: Sandeep Maheswaram <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 51 +++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index db4ae26..d8bed13 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -66,6 +66,14 @@
#define IMP_RES_OFFSET_MASK GENMASK(5, 0)
#define IMP_RES_OFFSET_SHIFT 0x0
+/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
+#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
+#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
+
+/* QUSB2PHY_CHG_CONTROL_2 register bits */
+#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
+#define CHG_CTRL2_OFFSET_SHIFT 0x4
+
/* QUSB2PHY_PORT_TUNE1 register bits */
#define HSTX_TRIM_MASK GENMASK(7, 4)
#define HSTX_TRIM_SHIFT 0x4
@@ -73,6 +81,10 @@
#define PREEMPHASIS_EN_MASK GENMASK(1, 0)
#define PREEMPHASIS_EN_SHIFT 0x0
+/* QUSB2PHY_PORT_TUNE2 register bits */
+#define HSDISC_TRIM_MASK GENMASK(1, 0)
+#define HSDISC_TRIM_SHIFT 0x0
+
#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
#define QUSB2PHY_PLL_CMODE 0x2c
@@ -327,6 +339,12 @@ struct qusb2_phy {
u8 preemphasis_level;
bool override_preemphasis_width;
u8 preemphasis_width;
+ bool override_bias_ctrl;
+ u8 bias_ctrl_value;
+ bool override_charge_ctrl;
+ u8 charge_ctrl_value;
+ bool override_hsdisc_trim;
+ u8 hsdisc_trim_value;
const struct qusb2_phy_cfg *cfg;
bool has_se_clk_scheme;
@@ -400,6 +418,16 @@ static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
qphy->imp_res_offset_value << IMP_RES_OFFSET_SHIFT,
IMP_RES_OFFSET_MASK);
+ if (qphy->override_bias_ctrl)
+ qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
+ qphy->bias_ctrl_value << BIAS_CTRL2_RES_OFFSET_SHIFT,
+ BIAS_CTRL2_RES_OFFSET_MASK);
+
+ if (qphy->override_charge_ctrl)
+ qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
+ qphy->charge_ctrl_value << CHG_CTRL2_OFFSET_SHIFT,
+ CHG_CTRL2_OFFSET_MASK);
+
if (qphy->override_hstx_trim)
qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
qphy->hstx_trim_value << HSTX_TRIM_SHIFT,
@@ -421,6 +449,11 @@ static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
cfg->regs[QUSB2PHY_PORT_TUNE1],
PREEMPH_WIDTH_HALF_BIT);
}
+
+ if (qphy->override_hsdisc_trim)
+ qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
+ qphy->hsdisc_trim_value << HSDISC_TRIM_SHIFT,
+ HSDISC_TRIM_MASK);
}
/*
@@ -874,6 +907,18 @@ static int qusb2_phy_probe(struct platform_device *pdev)
qphy->override_imp_res_offset = true;
}
+ if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value",
+ &value)) {
+ qphy->bias_ctrl_value = (u8)value;
+ qphy->override_bias_ctrl = true;
+ }
+
+ if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value",
+ &value)) {
+ qphy->charge_ctrl_value = (u8)value;
+ qphy->override_charge_ctrl = true;
+ }
+
if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
&value)) {
qphy->hstx_trim_value = (u8)value;
@@ -892,6 +937,12 @@ static int qusb2_phy_probe(struct platform_device *pdev)
qphy->override_preemphasis_width = true;
}
+ if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value",
+ &value)) {
+ qphy->hsdisc_trim_value = (u8)value;
+ qphy->override_hsdisc_trim = true;
+ }
+
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
/*
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Using generic cfg table for QUSB2 V2 PHY.
Add QUSB2 PHY config data and compatible for SC7180.
Signed-off-by: Sandeep Maheswaram <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index bf94a52..db4ae26 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
*/
#include <linux/clk.h>
@@ -177,7 +177,7 @@ static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
};
-static const unsigned int sdm845_regs_layout[] = {
+static const unsigned int qusb2_v2_regs_layout[] = {
[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
[QUSB2PHY_PLL_STATUS] = 0x1a0,
[QUSB2PHY_PORT_TUNE1] = 0x240,
@@ -191,7 +191,7 @@ static const unsigned int sdm845_regs_layout[] = {
[QUSB2PHY_INTR_CTRL] = 0x230,
};
-static const struct qusb2_phy_init_tbl sdm845_init_tbl[] = {
+static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
@@ -258,10 +258,10 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
.update_tune1_with_efuse = true,
};
-static const struct qusb2_phy_cfg sdm845_phy_cfg = {
- .tbl = sdm845_init_tbl,
- .tbl_num = ARRAY_SIZE(sdm845_init_tbl),
- .regs = sdm845_regs_layout,
+static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
+ .tbl = qusb2_v2_init_tbl,
+ .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
+ .regs = qusb2_v2_regs_layout,
.disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
POWER_DOWN),
@@ -774,8 +774,14 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
.compatible = "qcom,msm8998-qusb2-phy",
.data = &msm8998_phy_cfg,
}, {
+ .compatible = "qcom,sc7180-qusb2-phy",
+ .data = &qusb2_v2_phy_cfg,
+ }, {
.compatible = "qcom,sdm845-qusb2-phy",
- .data = &sdm845_phy_cfg,
+ .data = &qusb2_v2_phy_cfg,
+ }, {
+ .compatible = "qcom,qusb2-v2-phy",
+ .data = &qusb2_v2_phy_cfg,
},
{ },
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add support for overriding QUSB2 V2 phy tuning parameters
in device tree bindings.
Signed-off-by: Sandeep Maheswaram <[email protected]>
---
.../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
index 83cd01d..df4e000 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
@@ -84,6 +84,28 @@ properties:
maximum: 63
default: 0
+ qcom,bias-ctrl-value:
+ description:
+ It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
+ tuning parameter that may vary for different boards of same SOC.
+ This property is applicable to only QUSB2 v2 PHY.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ maximum: 63
+ default: 0
+
+ qcom,charge-ctrl-value:
+ description:
+ It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
+ tuning parameter that may vary for different boards of same SOC.
+ This property is applicable to only QUSB2 v2 PHY.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ maximum: 3
+ default: 0
+
qcom,hstx-trim-value:
description:
It is a 4 bit value that specifies tuning for HSTX
@@ -122,6 +144,17 @@ properties:
maximum: 1
default: 0
+ qcom,hsdisc-trim-value:
+ description:
+ It is a 2 bit value tuning parameter that control disconnect
+ threshold and may vary for different boards of same SOC.
+ This property is applicable to only QUSB2 v2 PHY.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ maximum: 3
+ default: 0
+
required:
- compatible
- reg
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On Fri, Jan 10, 2020 at 05:48:16PM +0530, Sandeep Maheswaram wrote:
> Convert QUSB2 phy bindings to DT schema format using json-schema.
>
> Signed-off-by: Sandeep Maheswaram <[email protected]>
> ---
> .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 152 +++++++++++++++++++++
> .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 68 ---------
> 2 files changed, 152 insertions(+), 68 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
Fails 'make dt_binding_check':
builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.example.dt.yaml:
phy@88e2000: 'vdda-pll-supply' is a required property
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.example.dt.yaml:
phy@88e2000: 'vdda-phy-dpdm-supply' is a required property
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> new file mode 100644
> index 0000000..83cd01d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> @@ -0,0 +1,152 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Qualcomm QUSB2 phy controller
> +
> +maintainers:
> + - Manu Gautam <[email protected]>
> +
> +description:
> + QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
> +
> +properties:
> + compatible:
> + anyOf:
anyOf is usually wrong. Use 'oneOf'.
> + - items:
> + - const: qcom,msm8996-qusb2-phy
> + - items:
> + - const: qcom,msm8998-qusb2-phy
> + - items:
> + - const: qcom,sc7180-qusb2-phy
> + - items:
> + - const: qcom,sdm845-qusb2-phy
These 4 can be a single enum. However, you should drop sc7180 and
sdm845. Those should match below. (Or drop the below. Just pick which
way and fixup any dts files that don't conform.)
> + - items:
> + - enum:
> + - qcom,sc7180-qusb2-phy
> + - qcom,sdm845-qusb2-phy
> + - const: qcom,qusb2-v2-phy
> +
> + reg:
> + maxItems: 1
> +
> + "#phy-cells":
> + const: 0
> +
> + clocks:
> + minItems: 2
> + items:
> + - description: phy config clock
> + - description: 19.2 MHz ref clk
> + - description: phy interface clock (Optional)
> +
> + clock-names:
> + minItems: 2
> + items:
> + - const: cfg_ahb
> + - const: ref
> + - const: iface
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> + vdda-phy-dpdm-supply:
> + description:
> + Phandle to 3.1V regulator supply to Dp/Dm port signals.
> +
> + resets:
> + maxItems: 1
> +
> + nvmem-cells:
> + maxItems: 1
> + description:
> + Phandle to nvmem cell that contains 'HS Tx trim'
> + tuning parameter value for qusb2 phy.
> +
> + qcom,tcsr-syscon:
> + description:
> + Phandle to TCSR syscon register region.
> + $ref: /schemas/types.yaml#/definitions/cell
s/cell/phandle/
> +
> + qcom,imp-res-offset-value:
> + description:
> + It is a 6 bit value that specifies offset to be
> + added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
> + tuning parameter that may vary for different boards of same SOC.
> + This property is applicable to only QUSB2 v2 PHY.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + maximum: 63
> + default: 0
> +
> + qcom,hstx-trim-value:
> + description:
> + It is a 4 bit value that specifies tuning for HSTX
> + output current.
> + Possible range is - 15mA to 24mA (stepsize of 600 uA).
> + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
> + This property is applicable to only QUSB2 v2 PHY.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + maximum: 15
> + default: 3
> +
> + qcom,preemphasis-level:
> + description:
> + It is a 2 bit value that specifies pre-emphasis level.
> + Possible range is 0 to 15% (stepsize of 5%).
> + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
> + This property is applicable to only QUSB2 v2 PHY.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + maximum: 3
> + default: 2
> +
> + qcom,preemphasis-width:
> + description:
> + It is a 1 bit value that specifies how long the HSTX
> + pre-emphasis (specified using qcom,preemphasis-level) must be in
> + effect. Duration could be half-bit of full-bit.
> + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
> + This property is applicable to only QUSB2 v2 PHY.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + maximum: 1
> + default: 0
> +
> +required:
> + - compatible
> + - reg
> + - "#phy-cells"
> + - clocks
> + - clock-names
> + - vdda-pll-supply
> + - vdda-phy-dpdm-supply
> + - resets
> +
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + usb_1_hsphy: phy@88e2000 {
> + compatible = "qcom,sdm845-qusb2-phy";
> + reg = <0 0x088e2000 0 0x400>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "cfg_ahb", "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +
> + nvmem-cells = <&qusb2p_hstx_trim>;
> + };
> diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
> deleted file mode 100644
> index fe29f9e..0000000
> --- a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
> +++ /dev/null
> @@ -1,68 +0,0 @@
> -Qualcomm QUSB2 phy controller
> -=============================
> -
> -QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
> -
> -Required properties:
> - - compatible: compatible list, contains
> - "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
> - "qcom,msm8998-qusb2-phy" for 10nm PHY on msm8998,
> - "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
> -
> - - reg: offset and length of the PHY register set.
> - - #phy-cells: must be 0.
> -
> - - clocks: a list of phandles and clock-specifier pairs,
> - one for each entry in clock-names.
> - - clock-names: must be "cfg_ahb" for phy config clock,
> - "ref" for 19.2 MHz ref clk,
> - "iface" for phy interface clock (Optional).
> -
> - - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
> - - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
> -
> - - resets: Phandle to reset to phy block.
> -
> -Optional properties:
> - - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
> - tuning parameter value for qusb2 phy.
> -
> - - qcom,tcsr-syscon: Phandle to TCSR syscon register region.
> - - qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be
> - added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
> - tuning parameter that may vary for different boards of same SOC.
> - This property is applicable to only QUSB2 v2 PHY (sdm845).
> - - qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX
> - output current.
> - Possible range is - 15mA to 24mA (stepsize of 600 uA).
> - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
> - This property is applicable to only QUSB2 v2 PHY (sdm845).
> - Default value is 22.2mA for sdm845.
> - - qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level.
> - Possible range is 0 to 15% (stepsize of 5%).
> - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
> - This property is applicable to only QUSB2 v2 PHY (sdm845).
> - Default value is 10% for sdm845.
> -- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX
> - pre-emphasis (specified using qcom,preemphasis-level) must be in
> - effect. Duration could be half-bit of full-bit.
> - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
> - This property is applicable to only QUSB2 v2 PHY (sdm845).
> - Default value is full-bit width for sdm845.
> -
> -Example:
> - hsusb_phy: phy@7411000 {
> - compatible = "qcom,msm8996-qusb2-phy";
> - reg = <0x7411000 0x180>;
> - #phy-cells = <0>;
> -
> - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> - <&gcc GCC_RX1_USB2_CLKREF_CLK>,
> - clock-names = "cfg_ahb", "ref";
> -
> - vdda-pll-supply = <&pm8994_l12>;
> - vdda-phy-dpdm-supply = <&pm8994_l24>;
> -
> - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> - nvmem-cells = <&qusb2p_hstx_trim>;
> - };
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
On Fri, 10 Jan 2020 17:48:17 +0530, Sandeep Maheswaram wrote:
> Add support for overriding QUSB2 V2 phy tuning parameters
> in device tree bindings.
>
> Signed-off-by: Sandeep Maheswaram <[email protected]>
> ---
> .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 33 ++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>
Hi,
On Fri, Jan 10, 2020 at 05:48:15PM +0530, Sandeep Maheswaram wrote:
> Using generic cfg table for QUSB2 V2 PHY.
> Add QUSB2 PHY config data and compatible for SC7180.
>
> Signed-off-by: Sandeep Maheswaram <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 22 ++++++++++++++--------
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index bf94a52..db4ae26 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
> */
>
> #include <linux/clk.h>
> @@ -177,7 +177,7 @@ static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
> QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
> };
>
> -static const unsigned int sdm845_regs_layout[] = {
> +static const unsigned int qusb2_v2_regs_layout[] = {
> [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
> [QUSB2PHY_PLL_STATUS] = 0x1a0,
> [QUSB2PHY_PORT_TUNE1] = 0x240,
> @@ -191,7 +191,7 @@ static const unsigned int sdm845_regs_layout[] = {
> [QUSB2PHY_INTR_CTRL] = 0x230,
> };
>
> -static const struct qusb2_phy_init_tbl sdm845_init_tbl[] = {
> +static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
> QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
> QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
> QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
> @@ -258,10 +258,10 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
> .update_tune1_with_efuse = true,
> };
>
> -static const struct qusb2_phy_cfg sdm845_phy_cfg = {
> - .tbl = sdm845_init_tbl,
> - .tbl_num = ARRAY_SIZE(sdm845_init_tbl),
> - .regs = sdm845_regs_layout,
> +static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
> + .tbl = qusb2_v2_init_tbl,
> + .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
> + .regs = qusb2_v2_regs_layout,
>
> .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
> POWER_DOWN),
> @@ -774,8 +774,14 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
> .compatible = "qcom,msm8998-qusb2-phy",
> .data = &msm8998_phy_cfg,
> }, {
> + .compatible = "qcom,sc7180-qusb2-phy",
> + .data = &qusb2_v2_phy_cfg,
> + }, {
I don't think you need the new entry as of now, since sc7180 just uses the
standard v2 configuration. DT compatible entries should look like this:
{
compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
...
}
hence the correct configuration is selected, even without a specific entry
for 'qcom,sc7180-qusb2-phy'.
> .compatible = "qcom,sdm845-qusb2-phy",
> - .data = &sdm845_phy_cfg,
> + .data = &qusb2_v2_phy_cfg,
> + }, {
think this can also be removed if you add 'qcom,qusb2-v2-phy' to the list
of compatible strings of nodes 'usb_1_hsphy' and 'usb_2_hsphy' in
arch/arm64/boot/dts/qcom/sdm845.dtsi.
> + .compatible = "qcom,qusb2-v2-phy",
> + .data = &qusb2_v2_phy_cfg,
> },
> { },
> };
Hi,
On Fri, Jan 10, 2020 at 05:48:16PM +0530, Sandeep Maheswaram wrote:
> Convert QUSB2 phy bindings to DT schema format using json-schema.
>
> Signed-off-by: Sandeep Maheswaram <[email protected]>
> ---
> .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 152 +++++++++++++++++++++
> .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 68 ---------
> 2 files changed, 152 insertions(+), 68 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> new file mode 100644
> index 0000000..83cd01d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> @@ -0,0 +1,152 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Qualcomm QUSB2 phy controller
> +
> +maintainers:
> + - Manu Gautam <[email protected]>
> +
> +description:
> + QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
> +
> +properties:
> + compatible:
> + anyOf:
> + - items:
> + - const: qcom,msm8996-qusb2-phy
> + - items:
> + - const: qcom,msm8998-qusb2-phy
> + - items:
> + - const: qcom,sc7180-qusb2-phy
> + - items:
> + - const: qcom,sdm845-qusb2-phy
> + - items:
> + - enum:
> + - qcom,sc7180-qusb2-phy
> + - qcom,sdm845-qusb2-phy
> + - const: qcom,qusb2-v2-phy
The subject says this patch converts the binding to YAML, however you are also
changing the binding (by adding 'qcom,sc7180-qusb2-phy' and 'qcom,qusb2-v2-phy'),
which is misleading. Please change this to one patch that does the 1:1 conversion
to YAML, and another that adds the new compatible strings.
Thanks
Matthias
Hi,
On Fri, Jan 10, 2020 at 05:48:18PM +0530, Sandeep Maheswaram wrote:
> Add support for overriding tuning parameters in QUSB2 V2 PHY
> bias-ctrl-value,charge-ctrl-value and hsdisc-trim-value.
>
> Signed-off-by: Sandeep Maheswaram <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 51 +++++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index db4ae26..d8bed13 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> @@ -66,6 +66,14 @@
> #define IMP_RES_OFFSET_MASK GENMASK(5, 0)
> #define IMP_RES_OFFSET_SHIFT 0x0
>
> +/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
> +#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
> +#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
> +
> +/* QUSB2PHY_CHG_CONTROL_2 register bits */
> +#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
> +#define CHG_CTRL2_OFFSET_SHIFT 0x4
> +
> /* QUSB2PHY_PORT_TUNE1 register bits */
> #define HSTX_TRIM_MASK GENMASK(7, 4)
> #define HSTX_TRIM_SHIFT 0x4
> @@ -73,6 +81,10 @@
> #define PREEMPHASIS_EN_MASK GENMASK(1, 0)
> #define PREEMPHASIS_EN_SHIFT 0x0
>
> +/* QUSB2PHY_PORT_TUNE2 register bits */
> +#define HSDISC_TRIM_MASK GENMASK(1, 0)
> +#define HSDISC_TRIM_SHIFT 0x0
> +
> #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
> #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
> #define QUSB2PHY_PLL_CMODE 0x2c
> @@ -327,6 +339,12 @@ struct qusb2_phy {
> u8 preemphasis_level;
> bool override_preemphasis_width;
> u8 preemphasis_width;
> + bool override_bias_ctrl;
> + u8 bias_ctrl_value;
> + bool override_charge_ctrl;
> + u8 charge_ctrl_value;
> + bool override_hsdisc_trim;
> + u8 hsdisc_trim_value;
Documentation for the new struct members is missing.
Given the increasing numbers of overrides you could consider to organize
them in a struct, instead of adding a 'override_' and '_value' to qusb2_phy
for every param. E.g.:
struct override_param {
bool override;
u8 value;
};
struct override_params {
struct override_param imp_res_offset;
struct override_param hstx_trim;
...
};
struct qusb2_phy {
struct override_params overrides;
};
Or - if you want to take it even further - something along these lines:
struct override_param {
const char *dt_property;
u32 offset;
u8 shift;
u8 mask;
// separate struct, since these are not constant?
bool override;
u8 value;
};
struct override_param params[] = {
{ "qcom,bias-ctrl-value", QUSB2PHY_PLL_BIAS_CONTROL_2, GENMASK(5, 0), 0 },
{ "qcom,charge-ctrl-value", QUSB2PHY_CHG_CTRL2, GENMASK(5, 4), 4 },
...
};