2020-01-14 15:58:27

by Moshe Shemesh

Subject: [PATCH net-next RFC 0/3] Add mlx5 devices FW upgrade reset support

This patchset adds support for FW upgrade.
On devlink reload, if a pending FW image is found, the driver will perform
a FW upgrade reset flow to activate the pending FW image.

Sending as RFC because the FW activation reset requires a pci link
toggling. Although it works and we verify that the device is the only
device on the pcie bridge before allowing such reset, as already done by
other drivers [1], we would like to get some feedback on the last patch
of this series.

[1] function trigger_sbr() at drivers/infiniband/hw/hfi1/pcie.c

Moshe Shemesh (3):
net/mlx5: Add structure layout and defines for MFRL register
net/mlx5: Add functions to set/query MFRL register
net/mlx5: Add FW upgrade reset support

drivers/net/ethernet/mellanox/mlx5/core/devlink.c | 81 +++++++++++++++++++++-
drivers/net/ethernet/mellanox/mlx5/core/fw.c | 44 ++++++++++++
.../net/ethernet/mellanox/mlx5/core/mlx5_core.h | 2 +
include/linux/mlx5/driver.h | 1 +
include/linux/mlx5/mlx5_ifc.h | 17 +++++
5 files changed, 144 insertions(+), 1 deletion(-)

--
1.8.3.1

2020-01-14 15:58:42

by Moshe Shemesh

Subject: [PATCH net-next RFC 2/3] net/mlx5: Add functions to set/query MFRL register

Add functions to set the reset level required and to query the reset
levels supported by fw.

Signed-off-by: Moshe Shemesh <[email protected]>
---
drivers/net/ethernet/mellanox/mlx5/core/fw.c | 44 ++++++++++++++++++++++
.../net/ethernet/mellanox/mlx5/core/mlx5_core.h | 2 +
2 files changed, 46 insertions(+)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
index 1723229..1c6dfe9 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
@@ -769,3 +769,47 @@ int mlx5_fw_version_query(struct mlx5_core_dev *dev,

return 0;
}
+
+static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
+ u8 reset_type_sel)
+{
+ u32 out[MLX5_ST_SZ_DW(mfrl_reg)];
+ u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
+
+ MLX5_SET(mfrl_reg, in, reset_level, reset_level);
+ MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
+
+ return mlx5_core_access_reg(dev, in, sizeof(in), out,
+ sizeof(out), MLX5_REG_MFRL, 0, 1);
+}
+
+static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
+ u8 *reset_type_sel, u8 *reset_type)
+{
+ u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
+ u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
+ int err;
+
+ err = mlx5_core_access_reg(dev, in, sizeof(in), out,
+ sizeof(out), MLX5_REG_MFRL, 0, 0);
+ if (err)
+ return err;
+
+ *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
+ *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
+ *reset_type_sel = MLX5_GET(mfrl_reg, out, rst_type_sel);
+
+ return 0;
+}
+
+int mlx5_fw_query_reset_level(struct mlx5_core_dev *dev, u8 *reset_level)
+{
+ u8 reset_type_sel, reset_type;
+
+ return mlx5_reg_mfrl_query(dev, reset_level, &reset_type_sel, &reset_type);
+}
+
+int mlx5_fw_set_reset_level(struct mlx5_core_dev *dev, u8 reset_level)
+{
+ return mlx5_reg_mfrl_set(dev, reset_level, 0);
+}
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
index da67b28..1b55a5a 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
@@ -210,6 +210,8 @@ int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw,
struct netlink_ext_ack *extack);
int mlx5_fw_version_query(struct mlx5_core_dev *dev,
u32 *running_ver, u32 *stored_ver);
+int mlx5_fw_query_reset_level(struct mlx5_core_dev *dev, u8 *reset_level);
+int mlx5_fw_set_reset_level(struct mlx5_core_dev *dev, u8 reset_level);

void mlx5e_init(void);
void mlx5e_cleanup(void);
--
1.8.3.1