Add FlexCAN support on i.MX8QXP.
Joakim Zhang (7):
firmware: imx: scu-pd: add power domain for I2C and INTMUX in CM40 SS
clk: imx8: Add SCU and LPCG clocks for I2C in CM40 SS
bindings: clock: imx8qxp: add "fsl,imx8qxp-lpcg-cm40" compatible
string
clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C in CM40 SS
arch: arm64: dts: imx8qxp: add device node for I2C and INTMUX in CM40
SS
clk: imx: imx8qxp: add LPCG clock for FlexCAN in ADMA SS
arch: arm64: dts: imx8qxp: add device node for CAN in ADMA SS
.../bindings/clock/imx8qxp-lpcg.txt | 1 +
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 74 ++++++++++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 106 ++++++++++++++++++
drivers/clk/imx/clk-imx8qxp-lpcg.c | 15 +++
drivers/clk/imx/clk-imx8qxp-lpcg.h | 3 +
drivers/clk/imx/clk-imx8qxp.c | 4 +
drivers/firmware/imx/scu-pd.c | 4 +
include/dt-bindings/clock/imx8-clock.h | 13 ++-
8 files changed, 219 insertions(+), 1 deletion(-)
--
2.17.1
Enable SCU and LPCG clocks for I2C in CM40 SS.
Signed-off-by: Joakim Zhang <[email protected]>
---
drivers/clk/imx/clk-imx8qxp-lpcg.c | 12 ++++++++++++
drivers/clk/imx/clk-imx8qxp-lpcg.h | 3 +++
drivers/clk/imx/clk-imx8qxp.c | 4 ++++
3 files changed, 19 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
index 04c8ee35e14c..795909ecfba6 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
@@ -151,6 +151,17 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
{ IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, },
};
+static const struct imx8qxp_lpcg_data imx8qxp_lpcg_cm40[] = {
+ { IMX_CM40_LPCG_I2C_CLK, "cm40_lpcg_i2c_clk", "cm40_i2c_clk", 0, CM40_I2C_LPCG, 0, 0, },
+ { IMX_CM40_LPCG_I2C_IPG_CLK, "cm40_lpcg_i2c_ipg_clk", "cm40_ipg_clk_root", 0, CM40_I2C_LPCG, 16, 0, },
+};
+
+static const struct imx8qxp_ss_lpcg imx8qxp_ss_cm40 = {
+ .lpcg = imx8qxp_lpcg_cm40,
+ .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_cm40),
+ .num_max = IMX_CM40_LPCG_CLK_END,
+};
+
static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
.lpcg = imx8qxp_lpcg_lsio,
.num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio),
@@ -219,6 +230,7 @@ static const struct of_device_id imx8qxp_lpcg_match[] = {
{ .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
{ .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
{ .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
+ { .compatible = "fsl,imx8qxp-lpcg-cm40", &imx8qxp_ss_cm40, },
{ /* sentinel */ }
};
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h
index 2a37ce57c500..28ca730dd135 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.h
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h
@@ -99,4 +99,7 @@
#define ADMA_FLEXCAN_1_LPCG 0x1ce0000
#define ADMA_FLEXCAN_2_LPCG 0x1cf0000
+/* CM40 SS */
+#define CM40_I2C_LPCG 0x60000
+
#endif /* _IMX8QXP_LPCG_H */
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 5e2903efc488..d051073ff042 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -53,6 +53,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
+ clks[IMX_CM40_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "cm40_ipg_clk_root", NULL, 0, 132000000);
/* ARM core */
clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
@@ -128,6 +129,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
+ /* CM40 SS */
+ clks[IMX_CM40_I2C_CLK] = imx_clk_scu("cm40_i2c_clk", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER);
+
for (i = 0; i < clk_data->num; i++) {
if (IS_ERR(clks[i]))
pr_warn("i.MX clk %u: register failed with %ld\n",
--
2.17.1
On Mon, Feb 17, 2020 at 11:19:18AM +0800, Joakim Zhang wrote:
> Enable SCU and LPCG clocks for I2C in CM40 SS.
>
> Signed-off-by: Joakim Zhang <[email protected]>
So you decided to stop waiting for Aisheng's new imx8qxp clock driver?
Shawn
> ---
> drivers/clk/imx/clk-imx8qxp-lpcg.c | 12 ++++++++++++
> drivers/clk/imx/clk-imx8qxp-lpcg.h | 3 +++
> drivers/clk/imx/clk-imx8qxp.c | 4 ++++
> 3 files changed, 19 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> index 04c8ee35e14c..795909ecfba6 100644
> --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
> +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> @@ -151,6 +151,17 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
> { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, },
> };
>
> +static const struct imx8qxp_lpcg_data imx8qxp_lpcg_cm40[] = {
> + { IMX_CM40_LPCG_I2C_CLK, "cm40_lpcg_i2c_clk", "cm40_i2c_clk", 0, CM40_I2C_LPCG, 0, 0, },
> + { IMX_CM40_LPCG_I2C_IPG_CLK, "cm40_lpcg_i2c_ipg_clk", "cm40_ipg_clk_root", 0, CM40_I2C_LPCG, 16, 0, },
> +};
> +
> +static const struct imx8qxp_ss_lpcg imx8qxp_ss_cm40 = {
> + .lpcg = imx8qxp_lpcg_cm40,
> + .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_cm40),
> + .num_max = IMX_CM40_LPCG_CLK_END,
> +};
> +
> static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
> .lpcg = imx8qxp_lpcg_lsio,
> .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio),
> @@ -219,6 +230,7 @@ static const struct of_device_id imx8qxp_lpcg_match[] = {
> { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
> { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
> { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
> + { .compatible = "fsl,imx8qxp-lpcg-cm40", &imx8qxp_ss_cm40, },
> { /* sentinel */ }
> };
>
> diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h
> index 2a37ce57c500..28ca730dd135 100644
> --- a/drivers/clk/imx/clk-imx8qxp-lpcg.h
> +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h
> @@ -99,4 +99,7 @@
> #define ADMA_FLEXCAN_1_LPCG 0x1ce0000
> #define ADMA_FLEXCAN_2_LPCG 0x1cf0000
>
> +/* CM40 SS */
> +#define CM40_I2C_LPCG 0x60000
> +
> #endif /* _IMX8QXP_LPCG_H */
> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> index 5e2903efc488..d051073ff042 100644
> --- a/drivers/clk/imx/clk-imx8qxp.c
> +++ b/drivers/clk/imx/clk-imx8qxp.c
> @@ -53,6 +53,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
> clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
> clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
> clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
> + clks[IMX_CM40_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "cm40_ipg_clk_root", NULL, 0, 132000000);
>
> /* ARM core */
> clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
> @@ -128,6 +129,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
> clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
> clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
>
> + /* CM40 SS */
> + clks[IMX_CM40_I2C_CLK] = imx_clk_scu("cm40_i2c_clk", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER);
> +
> for (i = 0; i < clk_data->num; i++) {
> if (IS_ERR(clks[i]))
> pr_warn("i.MX clk %u: register failed with %ld\n",
> --
> 2.17.1
>
> -----Original Message-----
> From: Shawn Guo <[email protected]>
> Sent: 2020??3??10?? 11:45
> To: Joakim Zhang <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; dl-linux-imx <[email protected]>; Anson Huang
> <[email protected]>; Leonard Crestez <[email protected]>;
> Daniel Baluta <[email protected]>; Aisheng Dong
> <[email protected]>; Peng Fan <[email protected]>; Andy Duan
> <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]
> Subject: Re: [PATCH 4/7] clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C
> in CM40 SS
>
> On Mon, Feb 17, 2020 at 11:19:18AM +0800, Joakim Zhang wrote:
> > Enable SCU and LPCG clocks for I2C in CM40 SS.
> >
> > Signed-off-by: Joakim Zhang <[email protected]>
>
> So you decided to stop waiting for Aisheng's new imx8qxp clock driver?
Hi Shawn,
Please ignore all clock and dts patches, I will send out again after Aisheng's new imx8qxp clock driver. Thanks.
Best Regards,
Joakim Zhang
> Shawn
>
> > ---
> > drivers/clk/imx/clk-imx8qxp-lpcg.c | 12 ++++++++++++
> > drivers/clk/imx/clk-imx8qxp-lpcg.h | 3 +++
> > drivers/clk/imx/clk-imx8qxp.c | 4 ++++
> > 3 files changed, 19 insertions(+)
> >
> > diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c
> > b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> > index 04c8ee35e14c..795909ecfba6 100644
> > --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
> > +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> > @@ -151,6 +151,17 @@ static const struct imx8qxp_lpcg_data
> imx8qxp_lpcg_lsio[] = {
> > { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk",
> > "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, }, };
> >
> > +static const struct imx8qxp_lpcg_data imx8qxp_lpcg_cm40[] = {
> > + { IMX_CM40_LPCG_I2C_CLK, "cm40_lpcg_i2c_clk", "cm40_i2c_clk", 0,
> CM40_I2C_LPCG, 0, 0, },
> > + { IMX_CM40_LPCG_I2C_IPG_CLK, "cm40_lpcg_i2c_ipg_clk",
> > +"cm40_ipg_clk_root", 0, CM40_I2C_LPCG, 16, 0, }, };
> > +
> > +static const struct imx8qxp_ss_lpcg imx8qxp_ss_cm40 = {
> > + .lpcg = imx8qxp_lpcg_cm40,
> > + .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_cm40),
> > + .num_max = IMX_CM40_LPCG_CLK_END,
> > +};
> > +
> > static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
> > .lpcg = imx8qxp_lpcg_lsio,
> > .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio), @@ -219,6 +230,7 @@
> > static const struct of_device_id imx8qxp_lpcg_match[] = {
> > { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
> > { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
> > { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
> > + { .compatible = "fsl,imx8qxp-lpcg-cm40", &imx8qxp_ss_cm40, },
> > { /* sentinel */ }
> > };
> >
> > diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h
> > b/drivers/clk/imx/clk-imx8qxp-lpcg.h
> > index 2a37ce57c500..28ca730dd135 100644
> > --- a/drivers/clk/imx/clk-imx8qxp-lpcg.h
> > +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h
> > @@ -99,4 +99,7 @@
> > #define ADMA_FLEXCAN_1_LPCG 0x1ce0000
> > #define ADMA_FLEXCAN_2_LPCG 0x1cf0000
> >
> > +/* CM40 SS */
> > +#define CM40_I2C_LPCG 0x60000
> > +
> > #endif /* _IMX8QXP_LPCG_H */
> > diff --git a/drivers/clk/imx/clk-imx8qxp.c
> > b/drivers/clk/imx/clk-imx8qxp.c index 5e2903efc488..d051073ff042
> > 100644
> > --- a/drivers/clk/imx/clk-imx8qxp.c
> > +++ b/drivers/clk/imx/clk-imx8qxp.c
> > @@ -53,6 +53,7 @@ static int imx8qxp_clk_probe(struct platform_device
> *pdev)
> > clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL,
> "hsio_per_clk_root", NULL, 0, 133333333);
> > clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL,
> "lsio_mem_clk_root", NULL, 0, 200000000);
> > clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL,
> "lsio_bus_clk_root", NULL, 0, 100000000);
> > + clks[IMX_CM40_IPG_CLK] = clk_hw_register_fixed_rate(NULL,
> "cm40_ipg_clk_root", NULL, 0, 132000000);
> >
> > /* ARM core */
> > clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35,
> IMX_SC_PM_CLK_CPU);
> > @@ -128,6 +129,9 @@ static int imx8qxp_clk_probe(struct platform_device
> *pdev)
> > clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk",
> IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
> > clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk",
> IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
> >
> > + /* CM40 SS */
> > + clks[IMX_CM40_I2C_CLK] = imx_clk_scu("cm40_i2c_clk",
> IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER);
> > +
> > for (i = 0; i < clk_data->num; i++) {
> > if (IS_ERR(clks[i]))
> > pr_warn("i.MX clk %u: register failed with %ld\n",
> > --
> > 2.17.1
> >