From: Kevin Tang <[email protected]>
DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
which transfers the image data from a video memory buffer to an internal
LCD interface.
Cc: Orson Zhai <[email protected]>
Cc: Baolin Wang <[email protected]>
Cc: Chunyan Zhang <[email protected]>
Signed-off-by: Kevin Tang <[email protected]>
---
.../devicetree/bindings/display/sprd/dpu.yaml | 85 ++++++++++++++++++++++
1 file changed, 85 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/sprd/dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/sprd/dpu.yaml b/Documentation/devicetree/bindings/display/sprd/dpu.yaml
new file mode 100644
index 0000000..7695d94
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sprd/dpu.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/sprd/dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc SoC Display Processor Unit (DPU)
+
+maintainers:
+ - David Airlie <[email protected]>
+ - Daniel Vetter <[email protected]>
+ - Rob Herring <[email protected]>
+ - Mark Rutland <[email protected]>
+
+description: |
+ DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
+ which transfers the image data from a video memory buffer to an internal
+ LCD interface.
+
+properties:
+ compatible:
+ const: sprd,sharkl3-dpu
+
+ reg:
+ maxItems: 1
+ description:
+ Physical base address and length of the DPU registers set
+
+ interrupts:
+ maxItems: 1
+ description:
+ The interrupt signal from DPU
+
+ clocks:
+ minItems: 2
+
+ clock-names:
+ items:
+ - const: clk_src_128m
+ - const: clk_src_384m
+
+ power-domains:
+ description: A phandle to DPU power domain node.
+
+ iommus:
+ description: A phandle to DPU iommu node.
+
+ port:
+ type: object
+ description:
+ A port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ That port should be the output endpoint, usually output to
+ the associated DSI.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/sprd,sc9860-clk.h>
+ dpu: dpu@0x63000000 {
+ compatible = "sprd,sharkl3-dpu";
+ reg = <0x0 0x63000000 0x0 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "clk_src_128m",
+ "clk_src_384m";
+
+ clocks = <&pll CLK_TWPLL_128M>,
+ <&pll CLK_TWPLL_384M>;
+
+ dpu_port: port {
+ dpu_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
--
2.7.4
Hi Kevin.
On Fri, Feb 21, 2020 at 03:48:53PM +0800, Kevin Tang wrote:
> From: Kevin Tang <[email protected]>
>
> DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
> which transfers the image data from a video memory buffer to an internal
> LCD interface.
>
> Cc: Orson Zhai <[email protected]>
> Cc: Baolin Wang <[email protected]>
> Cc: Chunyan Zhang <[email protected]>
> Signed-off-by: Kevin Tang <[email protected]>
> ---
> .../devicetree/bindings/display/sprd/dpu.yaml | 85 ++++++++++++++++++++++
> 1 file changed, 85 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/sprd/dpu.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/sprd/dpu.yaml b/Documentation/devicetree/bindings/display/sprd/dpu.yaml
> new file mode 100644
> index 0000000..7695d94
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/sprd/dpu.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/sprd/dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Unisoc SoC Display Processor Unit (DPU)
> +
> +maintainers:
> + - David Airlie <[email protected]>
> + - Daniel Vetter <[email protected]>
> + - Rob Herring <[email protected]>
> + - Mark Rutland <[email protected]>
> +
> +description: |
> + DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
> + which transfers the image data from a video memory buffer to an internal
> + LCD interface.
> +
> +properties:
> + compatible:
> + const: sprd,sharkl3-dpu
> +
> + reg:
> + maxItems: 1
> + description:
> + Physical base address and length of the DPU registers set
> +
> + interrupts:
> + maxItems: 1
> + description:
> + The interrupt signal from DPU
> +
> + clocks:
> + minItems: 2
Should this be maxItems: 2?
That would imply minItems: 2.
> +
> + clock-names:
> + items:
> + - const: clk_src_128m
> + - const: clk_src_384m
> +
> + power-domains:
> + description: A phandle to DPU power domain node.
> +
> + iommus:
> + description: A phandle to DPU iommu node.
> +
> + port:
> + type: object
> + description:
> + A port node with endpoint definitions as defined in
> + Documentation/devicetree/bindings/media/video-interfaces.txt.
> + That port should be the output endpoint, usually output to
> + the associated DSI.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - port
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/sprd,sc9860-clk.h>
> + dpu: dpu@0x63000000 {
> + compatible = "sprd,sharkl3-dpu";
> + reg = <0x0 0x63000000 0x0 0x1000>;
> + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "clk_src_128m",
> + "clk_src_384m";
> +
> + clocks = <&pll CLK_TWPLL_128M>,
> + <&pll CLK_TWPLL_384M>;
> +
> + dpu_port: port {
> + dpu_out: endpoint {
> + remote-endpoint = <&dsi_in>;
> + };
> + };
> + };
Did this example pass dt_binding_check with no warnings?
I wonder how the reg property could avoid generating warnings as the
upper node do not have #address_cells, #node_cells
Sam