v1 changes:
https://patchwork.kernel.org/patch/11680495/
https://patchwork.kernel.org/patch/11680497/
Crystal Guo (3):
dt-binding: mediatek: mt8192: update mtk-wdt document
dt-binding: mt8192: add toprgu reset-controller head file
watchdog: mt8192: add wdt support
.../devicetree/bindings/watchdog/mtk-wdt.txt | 5 ++--
drivers/watchdog/mtk_wdt.c | 6 +++++
.../dt-bindings/reset-controller/mt8192-resets.h | 30 ++++++++++++++++++++++
3 files changed, 39 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h
add driver setting to support mt8192 wdt
Signed-off-by: Crystal Guo <[email protected]>
---
drivers/watchdog/mtk_wdt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index d6a6393..aef0c2d 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -11,6 +11,7 @@
#include <dt-bindings/reset-controller/mt2712-resets.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
+#include <dt-bindings/reset-controller/mt8192-resets.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
@@ -76,6 +77,10 @@ struct mtk_wdt_data {
.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
};
+static const struct mtk_wdt_data mt8192_data = {
+ .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
+};
+
static int toprgu_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
@@ -322,6 +327,7 @@ static int mtk_wdt_resume(struct device *dev)
{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
{ .compatible = "mediatek,mt6589-wdt" },
{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
+ { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
--
1.8.1.1.dirty
add toprgu reset-controller head file for MT8192 platform
Signed-off-by: Crystal Guo <[email protected]>
---
.../dt-bindings/reset-controller/mt8192-resets.h | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h
diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h
new file mode 100644
index 0000000..be9a7ca
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8192-resets.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yong Liang <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
+
+#define MT8192_TOPRGU_MM_SW_RST 1
+#define MT8192_TOPRGU_MFG_SW_RST 2
+#define MT8192_TOPRGU_VENC_SW_RST 3
+#define MT8192_TOPRGU_VDEC_SW_RST 4
+#define MT8192_TOPRGU_IMG_SW_RST 5
+#define MT8192_TOPRGU_MD_SW_RST 7
+#define MT8192_TOPRGU_CONN_SW_RST 9
+#define MT8192_TOPRGU_CONN_MCU_SW_RST 12
+#define MT8192_TOPRGU_IPU0_SW_RST 14
+#define MT8192_TOPRGU_IPU1_SW_RST 15
+#define MT8192_TOPRGU_AUDIO_SW_RST 17
+#define MT8192_TOPRGU_CAMSYS_SW_RST 18
+#define MT8192_TOPRGU_MJC_SW_RST 19
+#define MT8192_TOPRGU_C2K_S2_SW_RST 20
+#define MT8192_TOPRGU_C2K_SW_RST 21
+#define MT8192_TOPRGU_PERI_SW_RST 22
+#define MT8192_TOPRGU_PERI_AO_SW_RST 23
+
+#define MT8192_TOPRGU_SW_RST_NUM 23
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
--
1.8.1.1.dirty
update mtk-wdt document for MT8192 platform
Signed-off-by: Crystal Guo <[email protected]>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 4dd36bd..e36ba60 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -4,14 +4,15 @@ Required properties:
- compatible should contain:
"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
- "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
+ "mediatek,mt2712-wdt": for MT2712
"mediatek,mt6589-wdt": for MT6589
"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
- "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
+ "mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
+ "mediatek,mt8192-wdt": for MT8192
- reg : Specifies base physical address and size of the registers.
--
1.8.1.1.dirty
On 29/07/2020 12:02, Crystal Guo wrote:
> update mtk-wdt document for MT8192 platform
should be two patches. one fixing the compatibles and second adding new board.
>
> Signed-off-by: Crystal Guo <[email protected]>
> ---
> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> index 4dd36bd..e36ba60 100644
> --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> @@ -4,14 +4,15 @@ Required properties:
>
> - compatible should contain:
> "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
> - "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
> + "mediatek,mt2712-wdt": for MT2712
> "mediatek,mt6589-wdt": for MT6589
> "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
> "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
> "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
> "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
> - "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
> + "mediatek,mt8183-wdt": for MT8183
We will need to update the DTSI in a seperate patch as well.
> "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
> + "mediatek,mt8192-wdt": for MT8192
>
> - reg : Specifies base physical address and size of the registers.
>
>
On Wed, 2020-07-29 at 18:18 +0800, Matthias Brugger wrote:
>
> On 29/07/2020 12:02, Crystal Guo wrote:
> > update mtk-wdt document for MT8192 platform
>
>
> should be two patches. one fixing the compatibles and second adding new board.
>
> >
> > Signed-off-by: Crystal Guo <[email protected]>
> > ---
> > Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > index 4dd36bd..e36ba60 100644
> > --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > @@ -4,14 +4,15 @@ Required properties:
> >
> > - compatible should contain:
> > "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
> > - "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
> > + "mediatek,mt2712-wdt": for MT2712
> > "mediatek,mt6589-wdt": for MT6589
> > "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
> > "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
> > "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
> > "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
> > - "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
> > + "mediatek,mt8183-wdt": for MT8183
>
> We will need to update the DTSI in a seperate patch as well.
Yes, this patch is based on
https://patchwork.kernel.org/patch/11690401/ , which modify description
for mt2712 and mt8183.
>
> > "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
> > + "mediatek,mt8192-wdt": for MT8192
> >
> > - reg : Specifies base physical address and size of the registers.
> >
> >
On 29/07/2020 12:02, Crystal Guo wrote:
> add driver setting to support mt8192 wdt
Commit message could be better:
"Add support for watchdog device found in MT8192 SoC." for example.
>
> Signed-off-by: Crystal Guo <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
> ---
> drivers/watchdog/mtk_wdt.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
> index d6a6393..aef0c2d 100644
> --- a/drivers/watchdog/mtk_wdt.c
> +++ b/drivers/watchdog/mtk_wdt.c
> @@ -11,6 +11,7 @@
>
> #include <dt-bindings/reset-controller/mt2712-resets.h>
> #include <dt-bindings/reset-controller/mt8183-resets.h>
> +#include <dt-bindings/reset-controller/mt8192-resets.h>
> #include <linux/delay.h>
> #include <linux/err.h>
> #include <linux/init.h>
> @@ -76,6 +77,10 @@ struct mtk_wdt_data {
> .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
> };
>
> +static const struct mtk_wdt_data mt8192_data = {
> + .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
> +};
> +
> static int toprgu_reset_update(struct reset_controller_dev *rcdev,
> unsigned long id, bool assert)
> {
> @@ -322,6 +327,7 @@ static int mtk_wdt_resume(struct device *dev)
> { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
> { .compatible = "mediatek,mt6589-wdt" },
> { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
> + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
>
On 30/07/2020 03:35, Crystal Guo wrote:
> On Wed, 2020-07-29 at 18:18 +0800, Matthias Brugger wrote:
>>
>> On 29/07/2020 12:02, Crystal Guo wrote:
>>> update mtk-wdt document for MT8192 platform
>>
>>
>> should be two patches. one fixing the compatibles and second adding new board.
>>
>>>
>>> Signed-off-by: Crystal Guo <[email protected]>
>>> ---
>>> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 5 +++--
>>> 1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
>>> index 4dd36bd..e36ba60 100644
>>> --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
>>> +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
>>> @@ -4,14 +4,15 @@ Required properties:
>>>
>>> - compatible should contain:
>>> "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
>>> - "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
>>> + "mediatek,mt2712-wdt": for MT2712
>>> "mediatek,mt6589-wdt": for MT6589
>>> "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
>>> "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
>>> "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
>>> "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
>>> - "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
>>> + "mediatek,mt8183-wdt": for MT8183
>>
>> We will need to update the DTSI in a seperate patch as well.
>
> Yes, this patch is based on
> https://patchwork.kernel.org/patch/11690401/ , which modify description
> for mt2712 and mt8183.
>
I don't understand your comment. This patch modifies the binding. The link you
provide is from an older version of the series (which is called v2 as well...)
So repeating myself: if you are updating the binding descritpion you will have
to update the dtsi as well as otherwise the binding and the dtsi are out of sync.
Regards,
Matthias
On 29/07/2020 12:02, Crystal Guo wrote:
> add toprgu reset-controller head file for MT8192 platform
>
> Signed-off-by: Crystal Guo <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
> ---
> .../dt-bindings/reset-controller/mt8192-resets.h | 30 ++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
> create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h
>
> diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h
> new file mode 100644
> index 0000000..be9a7ca
> --- /dev/null
> +++ b/include/dt-bindings/reset-controller/mt8192-resets.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2020 MediaTek Inc.
> + * Author: Yong Liang <[email protected]>
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
> +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
> +
> +#define MT8192_TOPRGU_MM_SW_RST 1
> +#define MT8192_TOPRGU_MFG_SW_RST 2
> +#define MT8192_TOPRGU_VENC_SW_RST 3
> +#define MT8192_TOPRGU_VDEC_SW_RST 4
> +#define MT8192_TOPRGU_IMG_SW_RST 5
> +#define MT8192_TOPRGU_MD_SW_RST 7
> +#define MT8192_TOPRGU_CONN_SW_RST 9
> +#define MT8192_TOPRGU_CONN_MCU_SW_RST 12
> +#define MT8192_TOPRGU_IPU0_SW_RST 14
> +#define MT8192_TOPRGU_IPU1_SW_RST 15
> +#define MT8192_TOPRGU_AUDIO_SW_RST 17
> +#define MT8192_TOPRGU_CAMSYS_SW_RST 18
> +#define MT8192_TOPRGU_MJC_SW_RST 19
> +#define MT8192_TOPRGU_C2K_S2_SW_RST 20
> +#define MT8192_TOPRGU_C2K_SW_RST 21
> +#define MT8192_TOPRGU_PERI_SW_RST 22
> +#define MT8192_TOPRGU_PERI_AO_SW_RST 23
> +
> +#define MT8192_TOPRGU_SW_RST_NUM 23
> +
> +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
>