v3 changes:
1.separate fixing compatibles description and adding new board with two patches.
2.update mt8183 DTSI for sync with the binding, while mt2712 DTSI has no watchdog node,
thus not update it together.
v2 changes:
https://patchwork.kernel.org/patch/11690729/
https://patchwork.kernel.org/patch/11690731/
https://patchwork.kernel.org/patch/11690719/
v1 changes:
https://patchwork.kernel.org/patch/11680495/
https://patchwork.kernel.org/patch/11680497/
Crystal Guo (5):
dt-binding: mediatek: watchdog: fix the description of compatible
arm64: dts: mt8183: update watchdog device node
dt-binding: mediatek: mt8192: update mtk-wdt document
dt-binding: mt8192: add toprgu reset-controller head file
watchdog: mt8192: add wdt support
.../devicetree/bindings/watchdog/mtk-wdt.txt | 5 ++--
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
drivers/watchdog/mtk_wdt.c | 6 +++++
.../dt-bindings/reset-controller/mt8192-resets.h | 30 ++++++++++++++++++++++
4 files changed, 40 insertions(+), 4 deletions(-)
create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h
update watchdog device node for MT8183
Signed-off-by: Crystal Guo <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 1e03c84..f8d8357 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -310,8 +310,7 @@
};
watchdog: watchdog@10007000 {
- compatible = "mediatek,mt8183-wdt",
- "mediatek,mt6589-wdt";
+ compatible = "mediatek,mt8183-wdt";
reg = <0 0x10007000 0 0x100>;
#reset-cells = <1>;
};
--
1.8.1.1.dirty
update mtk-wdt document for MT8192 platform
Signed-off-by: Crystal Guo <[email protected]>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 45eedc2..e36ba60 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
+ "mediatek,mt8192-wdt": for MT8192
- reg : Specifies base physical address and size of the registers.
--
1.8.1.1.dirty
add toprgu reset-controller head file for MT8192 platform
Signed-off-by: Crystal Guo <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
---
.../dt-bindings/reset-controller/mt8192-resets.h | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h
diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h
new file mode 100644
index 0000000..84fee34
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8192-resets.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yong Liang <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
+
+#define MT8183_TOPRGU_MM_SW_RST 1
+#define MT8183_TOPRGU_MFG_SW_RST 2
+#define MT8183_TOPRGU_VENC_SW_RST 3
+#define MT8183_TOPRGU_VDEC_SW_RST 4
+#define MT8183_TOPRGU_IMG_SW_RST 5
+#define MT8183_TOPRGU_MD_SW_RST 7
+#define MT8183_TOPRGU_CONN_SW_RST 9
+#define MT8183_TOPRGU_CONN_MCU_SW_RST 12
+#define MT8183_TOPRGU_IPU0_SW_RST 14
+#define MT8183_TOPRGU_IPU1_SW_RST 15
+#define MT8183_TOPRGU_AUDIO_SW_RST 17
+#define MT8183_TOPRGU_CAMSYS_SW_RST 18
+#define MT8192_TOPRGU_MJC_SW_RST 19
+#define MT8192_TOPRGU_C2K_S2_SW_RST 20
+#define MT8192_TOPRGU_C2K_SW_RST 21
+#define MT8192_TOPRGU_PERI_SW_RST 22
+#define MT8192_TOPRGU_PERI_AO_SW_RST 23
+
+#define MT8192_TOPRGU_SW_RST_NUM 23
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
--
1.8.1.1.dirty
Add support for watchdog device found in MT8192 SoC
Signed-off-by: Crystal Guo <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
---
drivers/watchdog/mtk_wdt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index d6a6393..aef0c2d 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -11,6 +11,7 @@
#include <dt-bindings/reset-controller/mt2712-resets.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
+#include <dt-bindings/reset-controller/mt8192-resets.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
@@ -76,6 +77,10 @@ struct mtk_wdt_data {
.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
};
+static const struct mtk_wdt_data mt8192_data = {
+ .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
+};
+
static int toprgu_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
@@ -322,6 +327,7 @@ static int mtk_wdt_resume(struct device *dev)
{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
{ .compatible = "mediatek,mt6589-wdt" },
{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
+ { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
--
1.8.1.1.dirty
On 30/07/2020 12:21, Crystal Guo wrote:
> update watchdog device node for MT8183
Explain why you update it.
>
> Signed-off-by: Crystal Guo <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 1e03c84..f8d8357 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -310,8 +310,7 @@
> };
>
> watchdog: watchdog@10007000 {
> - compatible = "mediatek,mt8183-wdt",
> - "mediatek,mt6589-wdt";
> + compatible = "mediatek,mt8183-wdt";
> reg = <0 0x10007000 0 0x100>;
> #reset-cells = <1>;
> };
>
On 7/30/20 3:21 AM, Crystal Guo wrote:
> Add support for watchdog device found in MT8192 SoC
>
> Signed-off-by: Crystal Guo <[email protected]>
> Reviewed-by: Matthias Brugger <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
> ---
> drivers/watchdog/mtk_wdt.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
> index d6a6393..aef0c2d 100644
> --- a/drivers/watchdog/mtk_wdt.c
> +++ b/drivers/watchdog/mtk_wdt.c
> @@ -11,6 +11,7 @@
>
> #include <dt-bindings/reset-controller/mt2712-resets.h>
> #include <dt-bindings/reset-controller/mt8183-resets.h>
> +#include <dt-bindings/reset-controller/mt8192-resets.h>
> #include <linux/delay.h>
> #include <linux/err.h>
> #include <linux/init.h>
> @@ -76,6 +77,10 @@ struct mtk_wdt_data {
> .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
> };
>
> +static const struct mtk_wdt_data mt8192_data = {
> + .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
> +};
> +
> static int toprgu_reset_update(struct reset_controller_dev *rcdev,
> unsigned long id, bool assert)
> {
> @@ -322,6 +327,7 @@ static int mtk_wdt_resume(struct device *dev)
> { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
> { .compatible = "mediatek,mt6589-wdt" },
> { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
> + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
>