Cleanup the PHY drivers for IPplus devices and add PHY counters and MDIX
support for the IP101A/G.
Patch 5 adds a model detection based on the behavior of the PHY.
Unfortunately, the IP101A shares the PHY ID with the IP101G. But the latter
provides more features. Try to detect the newer model by accessing the page
selection register. If it is writeable, it is assumed, that it is a IP101G.
With this detection in place, we can now access registers >= 16 in a
correct way on the IP101G; that is by first selecting the correct page.
This might previouly worked, because no one ever set another active page
before booting linux.
The last two patches add the new features.
Michael Walle (9):
net: phy: icplus: use PHY_ID_MATCH_MODEL() macro
net: phy: icplus: use PHY_ID_MATCH_EXACT() for IP101A/G
net: phy: icplus: drop address operator for functions
net: phy: icplus: use the .soft_reset() of the phy-core
net: phy: icplus: split IP101A/G driver
net: phy: icplus: don't set APS_EN bit on IP101G
net: phy: icplus: fix paged register access
net: phy: icplus: add PHY counter for IP101G
net: phy: icplus: add MDI/MDIX support for IP101A/G
drivers/net/phy/icplus.c | 384 ++++++++++++++++++++++++++++++++-------
1 file changed, 323 insertions(+), 61 deletions(-)
--
2.20.1
Implement the operations to set desired mode and retrieve the current
mode.
This feature was tested with an IP101G.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
---
Changes since v3:
- added return code check on phy_select_page()
Changes since v2:
- none
Changes since v1:
- none, except that the callbacks are register for both IP101A and IP101G
PHY drivers
drivers/net/phy/icplus.c | 97 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index 41bd0fa2ce17..4e15d4d02488 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -37,12 +37,17 @@ MODULE_LICENSE("GPL");
#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
#define IP101A_G_APS_ON BIT(1) /* IP101A/G APS Mode bit */
+#define IP101A_G_AUTO_MDIX_DIS BIT(11)
#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
#define IP101A_G_IRQ_PIN_USED BIT(15) /* INTR pin used */
#define IP101A_G_IRQ_ALL_MASK BIT(11) /* IRQ's inactive */
#define IP101A_G_IRQ_SPEED_CHANGE BIT(2)
#define IP101A_G_IRQ_DUPLEX_CHANGE BIT(1)
#define IP101A_G_IRQ_LINK_CHANGE BIT(0)
+#define IP101A_G_PHY_STATUS 18
+#define IP101A_G_MDIX BIT(9)
+#define IP101A_G_PHY_SPEC_CTRL 30
+#define IP101A_G_FORCE_MDIX BIT(3)
#define IP101G_PAGE_CONTROL 0x14
#define IP101G_PAGE_CONTROL_MASK GENMASK(4, 0)
@@ -299,6 +304,94 @@ static int ip101g_config_init(struct phy_device *phydev)
return ip101a_g_config_intr_pin(phydev);
}
+static int ip101a_g_read_status(struct phy_device *phydev)
+{
+ int oldpage, ret, stat1, stat2;
+
+ ret = genphy_read_status(phydev);
+ if (ret)
+ return ret;
+
+ oldpage = phy_select_page(phydev, IP101G_DEFAULT_PAGE);
+ if (oldpage < 0)
+ return oldpage;
+
+ ret = __phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
+ if (ret < 0)
+ goto out;
+ stat1 = ret;
+
+ ret = __phy_read(phydev, IP101A_G_PHY_SPEC_CTRL);
+ if (ret < 0)
+ goto out;
+ stat2 = ret;
+
+ if (stat1 & IP101A_G_AUTO_MDIX_DIS) {
+ if (stat2 & IP101A_G_FORCE_MDIX)
+ phydev->mdix_ctrl = ETH_TP_MDI_X;
+ else
+ phydev->mdix_ctrl = ETH_TP_MDI;
+ } else {
+ phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
+ }
+
+ if (stat2 & IP101A_G_MDIX)
+ phydev->mdix = ETH_TP_MDI_X;
+ else
+ phydev->mdix = ETH_TP_MDI;
+
+ ret = 0;
+
+out:
+ return phy_restore_page(phydev, oldpage, ret);
+}
+
+static int ip101a_g_config_mdix(struct phy_device *phydev)
+{
+ u16 ctrl = 0, ctrl2 = 0;
+ int oldpage, ret;
+
+ switch (phydev->mdix_ctrl) {
+ case ETH_TP_MDI:
+ ctrl = IP101A_G_AUTO_MDIX_DIS;
+ break;
+ case ETH_TP_MDI_X:
+ ctrl = IP101A_G_AUTO_MDIX_DIS;
+ ctrl2 = IP101A_G_FORCE_MDIX;
+ break;
+ case ETH_TP_MDI_AUTO:
+ break;
+ default:
+ return 0;
+ }
+
+ oldpage = phy_select_page(phydev, IP101G_DEFAULT_PAGE);
+ if (oldpage < 0)
+ return oldpage;
+
+ ret = __phy_modify(phydev, IP10XX_SPEC_CTRL_STATUS,
+ IP101A_G_AUTO_MDIX_DIS, ctrl);
+ if (ret)
+ goto out;
+
+ ret = __phy_modify(phydev, IP101A_G_PHY_SPEC_CTRL,
+ IP101A_G_FORCE_MDIX, ctrl2);
+
+out:
+ return phy_restore_page(phydev, oldpage, ret);
+}
+
+static int ip101a_g_config_aneg(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = ip101a_g_config_mdix(phydev);
+ if (ret)
+ return ret;
+
+ return genphy_config_aneg(phydev);
+}
+
static int ip101a_g_ack_interrupt(struct phy_device *phydev)
{
int err;
@@ -504,6 +597,8 @@ static struct phy_driver icplus_driver[] = {
.config_intr = ip101a_g_config_intr,
.handle_interrupt = ip101a_g_handle_interrupt,
.config_init = ip101a_config_init,
+ .config_aneg = ip101a_g_config_aneg,
+ .read_status = ip101a_g_read_status,
.soft_reset = genphy_soft_reset,
.suspend = genphy_suspend,
.resume = genphy_resume,
@@ -516,6 +611,8 @@ static struct phy_driver icplus_driver[] = {
.config_intr = ip101a_g_config_intr,
.handle_interrupt = ip101a_g_handle_interrupt,
.config_init = ip101g_config_init,
+ .config_aneg = ip101a_g_config_aneg,
+ .read_status = ip101a_g_read_status,
.soft_reset = genphy_soft_reset,
.get_sset_count = ip101g_get_sset_count,
.get_strings = ip101g_get_strings,
--
2.20.1
Registers >= 16 are paged. Be sure to set the page. It seems this was
working for now, because the default is correct for the registers used
in the driver at the moment. But this will also assume, nobody will
change the page select register before linux is started. The page select
register is _not_ reset with a soft reset of the PHY.
To ease the function reuse between the non-paged register space of the
IP101A and the IP101G, add noop read_page()/write_page() callbacks so
the IP101G functions can also be used for the IP101A.
Signed-off-by: Michael Walle <[email protected]>
---
Changes since v3:
- added return code check on phy_select_page()
- initialize err, found by kernel test robot
Changes since v2:
- none
Changes since v1:
- introduce a noop read/write_page() for the IP101A
- also use phy_*_paged() for the interrupt status register
Andrew, I've dropped your Reviewed-by because of this.
drivers/net/phy/icplus.c | 67 ++++++++++++++++++++++++++++++++--------
1 file changed, 54 insertions(+), 13 deletions(-)
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index bc2b58061507..f98edd66cdd2 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -49,6 +49,8 @@ MODULE_LICENSE("GPL");
#define IP101G_DIGITAL_IO_SPEC_CTRL 0x1d
#define IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32 BIT(2)
+#define IP101G_DEFAULT_PAGE 16
+
#define IP175C_PHY_ID 0x02430d80
#define IP1001_PHY_ID 0x02430d90
#define IP101A_PHY_ID 0x02430c54
@@ -211,23 +213,27 @@ static int ip101a_g_probe(struct phy_device *phydev)
static int ip101a_g_config_intr_pin(struct phy_device *phydev)
{
struct ip101a_g_phy_priv *priv = phydev->priv;
- int err;
+ int oldpage, err = 0;
+
+ oldpage = phy_select_page(phydev, IP101G_DEFAULT_PAGE);
+ if (oldpage < 0)
+ return oldpage;
/* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */
switch (priv->sel_intr32) {
case IP101GR_SEL_INTR32_RXER:
- err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
- IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32, 0);
+ err = __phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
+ IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32, 0);
if (err < 0)
- return err;
+ goto out;
break;
case IP101GR_SEL_INTR32_INTR:
- err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
- IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32,
- IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32);
+ err = __phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
+ IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32,
+ IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32);
if (err < 0)
- return err;
+ goto out;
break;
default:
@@ -241,7 +247,8 @@ static int ip101a_g_config_intr_pin(struct phy_device *phydev)
break;
}
- return 0;
+out:
+ return phy_restore_page(phydev, oldpage, err);
}
static int ip101a_config_init(struct phy_device *phydev)
@@ -263,8 +270,10 @@ static int ip101g_config_init(struct phy_device *phydev)
static int ip101a_g_ack_interrupt(struct phy_device *phydev)
{
- int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
+ int err;
+ err = phy_read_paged(phydev, IP101G_DEFAULT_PAGE,
+ IP101A_G_IRQ_CONF_STATUS);
if (err < 0)
return err;
@@ -283,10 +292,12 @@ static int ip101a_g_config_intr(struct phy_device *phydev)
/* INTR pin used: Speed/link/duplex will cause an interrupt */
val = IP101A_G_IRQ_PIN_USED;
- err = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, val);
+ err = phy_write_paged(phydev, IP101G_DEFAULT_PAGE,
+ IP101A_G_IRQ_CONF_STATUS, val);
} else {
val = IP101A_G_IRQ_ALL_MASK;
- err = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, val);
+ err = phy_write_paged(phydev, IP101G_DEFAULT_PAGE,
+ IP101A_G_IRQ_CONF_STATUS, val);
if (err)
return err;
@@ -300,7 +311,8 @@ static irqreturn_t ip101a_g_handle_interrupt(struct phy_device *phydev)
{
int irq_status;
- irq_status = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
+ irq_status = phy_read_paged(phydev, IP101G_DEFAULT_PAGE,
+ IP101A_G_IRQ_CONF_STATUS);
if (irq_status < 0) {
phy_error(phydev);
return IRQ_NONE;
@@ -316,6 +328,31 @@ static irqreturn_t ip101a_g_handle_interrupt(struct phy_device *phydev)
return IRQ_HANDLED;
}
+/* The IP101A doesn't really have a page register. We just pretend to have one
+ * so we can use the paged versions of the callbacks of the IP101G.
+ */
+static int ip101a_read_page(struct phy_device *phydev)
+{
+ return IP101G_DEFAULT_PAGE;
+}
+
+static int ip101a_write_page(struct phy_device *phydev, int page)
+{
+ WARN_ONCE(page != IP101G_DEFAULT_PAGE, "wrong page selected\n");
+
+ return 0;
+}
+
+static int ip101g_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, IP101G_PAGE_CONTROL);
+}
+
+static int ip101g_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, IP101G_PAGE_CONTROL, page);
+}
+
static int ip101a_g_has_page_register(struct phy_device *phydev)
{
int oldval, val, ret;
@@ -390,6 +427,8 @@ static struct phy_driver icplus_driver[] = {
.name = "ICPlus IP101A",
.match_phy_device = ip101a_match_phy_device,
.probe = ip101a_g_probe,
+ .read_page = ip101a_read_page,
+ .write_page = ip101a_write_page,
.config_intr = ip101a_g_config_intr,
.handle_interrupt = ip101a_g_handle_interrupt,
.config_init = ip101a_config_init,
@@ -400,6 +439,8 @@ static struct phy_driver icplus_driver[] = {
.name = "ICPlus IP101G",
.match_phy_device = ip101g_match_phy_device,
.probe = ip101a_g_probe,
+ .read_page = ip101g_read_page,
+ .write_page = ip101g_write_page,
.config_intr = ip101a_g_config_intr,
.handle_interrupt = ip101a_g_handle_interrupt,
.config_init = ip101g_config_init,
--
2.20.1
The IP101G provides three counters: RX packets, CRC errors and symbol
errors. The error counters can be configured to clear automatically on
read. Unfortunately, this isn't true for the RX packet counter. Because
of this and because the RX packet counter is more likely to overflow,
than the error counters implement only support for the error counters.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
---
Changes since v3:
- none
Changes since v2:
- none
Changes since v1:
- renamed the functions to represend a IP101G-only function
- enable the counters in IP101G's config_init()
drivers/net/phy/icplus.c | 75 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index f98edd66cdd2..41bd0fa2ce17 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -51,6 +51,12 @@ MODULE_LICENSE("GPL");
#define IP101G_DEFAULT_PAGE 16
+#define IP101G_P1_CNT_CTRL 17
+#define CNT_CTRL_RX_EN BIT(13)
+#define IP101G_P8_CNT_CTRL 17
+#define CNT_CTRL_RDCLR_EN BIT(15)
+#define IP101G_CNT_REG 18
+
#define IP175C_PHY_ID 0x02430d80
#define IP1001_PHY_ID 0x02430d90
#define IP101A_PHY_ID 0x02430c54
@@ -65,8 +71,19 @@ enum ip101gr_sel_intr32 {
IP101GR_SEL_INTR32_RXER,
};
+struct ip101g_hw_stat {
+ const char *name;
+ int page;
+};
+
+static struct ip101g_hw_stat ip101g_hw_stats[] = {
+ { "phy_crc_errors", 1 },
+ { "phy_symbol_errors", 11, },
+};
+
struct ip101a_g_phy_priv {
enum ip101gr_sel_intr32 sel_intr32;
+ u64 stats[ARRAY_SIZE(ip101g_hw_stats)];
};
static int ip175c_config_init(struct phy_device *phydev)
@@ -265,6 +282,20 @@ static int ip101a_config_init(struct phy_device *phydev)
static int ip101g_config_init(struct phy_device *phydev)
{
+ int ret;
+
+ /* Enable the PHY counters */
+ ret = phy_modify_paged(phydev, 1, IP101G_P1_CNT_CTRL,
+ CNT_CTRL_RX_EN, CNT_CTRL_RX_EN);
+ if (ret)
+ return ret;
+
+ /* Clear error counters on read */
+ ret = phy_modify_paged(phydev, 8, IP101G_P8_CNT_CTRL,
+ CNT_CTRL_RDCLR_EN, CNT_CTRL_RDCLR_EN);
+ if (ret)
+ return ret;
+
return ip101a_g_config_intr_pin(phydev);
}
@@ -405,6 +436,47 @@ static int ip101g_match_phy_device(struct phy_device *phydev)
return ip101a_g_match_phy_device(phydev, false);
}
+static int ip101g_get_sset_count(struct phy_device *phydev)
+{
+ return ARRAY_SIZE(ip101g_hw_stats);
+}
+
+static void ip101g_get_strings(struct phy_device *phydev, u8 *data)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ip101g_hw_stats); i++)
+ strscpy(data + i * ETH_GSTRING_LEN,
+ ip101g_hw_stats[i].name, ETH_GSTRING_LEN);
+}
+
+static u64 ip101g_get_stat(struct phy_device *phydev, int i)
+{
+ struct ip101g_hw_stat stat = ip101g_hw_stats[i];
+ struct ip101a_g_phy_priv *priv = phydev->priv;
+ int val;
+ u64 ret;
+
+ val = phy_read_paged(phydev, stat.page, IP101G_CNT_REG);
+ if (val < 0) {
+ ret = U64_MAX;
+ } else {
+ priv->stats[i] += val;
+ ret = priv->stats[i];
+ }
+
+ return ret;
+}
+
+static void ip101g_get_stats(struct phy_device *phydev,
+ struct ethtool_stats *stats, u64 *data)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ip101g_hw_stats); i++)
+ data[i] = ip101g_get_stat(phydev, i);
+}
+
static struct phy_driver icplus_driver[] = {
{
PHY_ID_MATCH_MODEL(IP175C_PHY_ID),
@@ -445,6 +517,9 @@ static struct phy_driver icplus_driver[] = {
.handle_interrupt = ip101a_g_handle_interrupt,
.config_init = ip101g_config_init,
.soft_reset = genphy_soft_reset,
+ .get_sset_count = ip101g_get_sset_count,
+ .get_strings = ip101g_get_strings,
+ .get_stats = ip101g_get_stats,
.suspend = genphy_suspend,
.resume = genphy_resume,
} };
--
2.20.1
This bit is reserved as 'always-write-1'. While this is not a particular
error, because we are only setting it, guard it by checking the model to
prevent errors in the future.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
---
Changes since v3:
- none
Changes since v2:
- none
Changes since v1:
- dropped the model check. Instead use two different functions.
drivers/net/phy/icplus.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index dee4f4d988a2..bc2b58061507 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -208,10 +208,10 @@ static int ip101a_g_probe(struct phy_device *phydev)
return 0;
}
-static int ip101a_g_config_init(struct phy_device *phydev)
+static int ip101a_g_config_intr_pin(struct phy_device *phydev)
{
struct ip101a_g_phy_priv *priv = phydev->priv;
- int err, c;
+ int err;
/* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */
switch (priv->sel_intr32) {
@@ -241,11 +241,24 @@ static int ip101a_g_config_init(struct phy_device *phydev)
break;
}
+ return 0;
+}
+
+static int ip101a_config_init(struct phy_device *phydev)
+{
+ int ret;
+
/* Enable Auto Power Saving mode */
- c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
- c |= IP101A_G_APS_ON;
+ ret = phy_set_bits(phydev, IP10XX_SPEC_CTRL_STATUS, IP101A_G_APS_ON);
+ if (ret)
+ return ret;
- return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
+ return ip101a_g_config_intr_pin(phydev);
+}
+
+static int ip101g_config_init(struct phy_device *phydev)
+{
+ return ip101a_g_config_intr_pin(phydev);
}
static int ip101a_g_ack_interrupt(struct phy_device *phydev)
@@ -379,7 +392,7 @@ static struct phy_driver icplus_driver[] = {
.probe = ip101a_g_probe,
.config_intr = ip101a_g_config_intr,
.handle_interrupt = ip101a_g_handle_interrupt,
- .config_init = ip101a_g_config_init,
+ .config_init = ip101a_config_init,
.soft_reset = genphy_soft_reset,
.suspend = genphy_suspend,
.resume = genphy_resume,
@@ -389,7 +402,7 @@ static struct phy_driver icplus_driver[] = {
.probe = ip101a_g_probe,
.config_intr = ip101a_g_config_intr,
.handle_interrupt = ip101a_g_handle_interrupt,
- .config_init = ip101a_g_config_init,
+ .config_init = ip101g_config_init,
.soft_reset = genphy_soft_reset,
.suspend = genphy_suspend,
.resume = genphy_resume,
--
2.20.1
According to the datasheet of the IP101A/G there is no revision field
and MII_PHYSID2 always reads as 0x0c54. Use PHY_ID_MATCH_EXACT() then.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
---
Changes since v3:
- none
Changes since v2:
- none
Changes since v1:
- none
drivers/net/phy/icplus.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index 4407b1eb1a3d..ae3cf61c5ac2 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -349,7 +349,7 @@ static struct phy_driver icplus_driver[] = {
.suspend = genphy_suspend,
.resume = genphy_resume,
}, {
- PHY_ID_MATCH_MODEL(IP101A_PHY_ID),
+ PHY_ID_MATCH_EXACT(IP101A_PHY_ID),
.name = "ICPlus IP101A/G",
/* PHY_BASIC_FEATURES */
.probe = ip101a_g_probe,
@@ -365,7 +365,7 @@ module_phy_driver(icplus_driver);
static struct mdio_device_id __maybe_unused icplus_tbl[] = {
{ PHY_ID_MATCH_MODEL(IP175C_PHY_ID) },
{ PHY_ID_MATCH_MODEL(IP1001_PHY_ID) },
- { PHY_ID_MATCH_MODEL(IP101A_PHY_ID) },
+ { PHY_ID_MATCH_EXACT(IP101A_PHY_ID) },
{ }
};
--
2.20.1
The PHY core already resets the PHY before .config_init() if a
.soft_reset() op is registered. Drop the open-coded ip1xx_reset().
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
---
Changes since v3:
- none
Changes since v2:
- none
Changes since v1:
- none
drivers/net/phy/icplus.c | 32 ++------------------------------
1 file changed, 2 insertions(+), 30 deletions(-)
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index 43b69addc0ce..036bac628b11 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -120,36 +120,10 @@ static int ip175c_config_init(struct phy_device *phydev)
return 0;
}
-static int ip1xx_reset(struct phy_device *phydev)
-{
- int bmcr;
-
- /* Software Reset PHY */
- bmcr = phy_read(phydev, MII_BMCR);
- if (bmcr < 0)
- return bmcr;
- bmcr |= BMCR_RESET;
- bmcr = phy_write(phydev, MII_BMCR, bmcr);
- if (bmcr < 0)
- return bmcr;
-
- do {
- bmcr = phy_read(phydev, MII_BMCR);
- if (bmcr < 0)
- return bmcr;
- } while (bmcr & BMCR_RESET);
-
- return 0;
-}
-
static int ip1001_config_init(struct phy_device *phydev)
{
int c;
- c = ip1xx_reset(phydev);
- if (c < 0)
- return c;
-
/* Enable Auto Power Saving mode */
c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
if (c < 0)
@@ -237,10 +211,6 @@ static int ip101a_g_config_init(struct phy_device *phydev)
struct ip101a_g_phy_priv *priv = phydev->priv;
int err, c;
- c = ip1xx_reset(phydev);
- if (c < 0)
- return c;
-
/* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */
switch (priv->sel_intr32) {
case IP101GR_SEL_INTR32_RXER:
@@ -346,6 +316,7 @@ static struct phy_driver icplus_driver[] = {
.name = "ICPlus IP1001",
/* PHY_GBIT_FEATURES */
.config_init = ip1001_config_init,
+ .soft_reset = genphy_soft_reset,
.suspend = genphy_suspend,
.resume = genphy_resume,
}, {
@@ -356,6 +327,7 @@ static struct phy_driver icplus_driver[] = {
.config_intr = ip101a_g_config_intr,
.handle_interrupt = ip101a_g_handle_interrupt,
.config_init = ip101a_g_config_init,
+ .soft_reset = genphy_soft_reset,
.suspend = genphy_suspend,
.resume = genphy_resume,
} };
--
2.20.1
Unfortunately, the IP101A and IP101G share the same PHY identifier.
While most of the functions are somewhat backwards compatible, there is
for example the APS_EN bit on the IP101A but on the IP101G this bit
reserved. Also, the IP101G has many more functionalities.
Deduce the model by accessing the page select register which - according
to the datasheet - is not available on the IP101A. If this register is
writable, assume we have an IP101G.
Split the combined IP101A/G driver into two separate drivers.
Signed-off-by: Michael Walle <[email protected]>
---
Changes since v3:
- none
Changes since v2:
- dropped the PHY_BASIC_FEATURES comments as suggested by Heiner
- converted the ternary operator to a simple comparison as suggested by
Heiner
Changes since v1:
- use match_phy_device() as suggested by Heiner
Andrew, I've dropped your Reviewed-by because of this.
drivers/net/phy/icplus.c | 69 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 66 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index 036bac628b11..dee4f4d988a2 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -44,6 +44,8 @@ MODULE_LICENSE("GPL");
#define IP101A_G_IRQ_DUPLEX_CHANGE BIT(1)
#define IP101A_G_IRQ_LINK_CHANGE BIT(0)
+#define IP101G_PAGE_CONTROL 0x14
+#define IP101G_PAGE_CONTROL_MASK GENMASK(4, 0)
#define IP101G_DIGITAL_IO_SPEC_CTRL 0x1d
#define IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32 BIT(2)
@@ -301,6 +303,58 @@ static irqreturn_t ip101a_g_handle_interrupt(struct phy_device *phydev)
return IRQ_HANDLED;
}
+static int ip101a_g_has_page_register(struct phy_device *phydev)
+{
+ int oldval, val, ret;
+
+ oldval = phy_read(phydev, IP101G_PAGE_CONTROL);
+ if (oldval < 0)
+ return oldval;
+
+ ret = phy_write(phydev, IP101G_PAGE_CONTROL, 0xffff);
+ if (ret)
+ return ret;
+
+ val = phy_read(phydev, IP101G_PAGE_CONTROL);
+ if (val < 0)
+ return val;
+
+ ret = phy_write(phydev, IP101G_PAGE_CONTROL, oldval);
+ if (ret)
+ return ret;
+
+ return val == IP101G_PAGE_CONTROL_MASK;
+}
+
+static int ip101a_g_match_phy_device(struct phy_device *phydev, bool ip101a)
+{
+ int ret;
+
+ if (phydev->phy_id != IP101A_PHY_ID)
+ return 0;
+
+ /* The IP101A and the IP101G share the same PHY identifier.The IP101G
+ * seems to be a successor of the IP101A and implements more functions.
+ * Amongst other things there is a page select register, which is not
+ * available on the IP101A. Use this to distinguish these two.
+ */
+ ret = ip101a_g_has_page_register(phydev);
+ if (ret < 0)
+ return ret;
+
+ return ip101a == !ret;
+}
+
+static int ip101a_match_phy_device(struct phy_device *phydev)
+{
+ return ip101a_g_match_phy_device(phydev, true);
+}
+
+static int ip101g_match_phy_device(struct phy_device *phydev)
+{
+ return ip101a_g_match_phy_device(phydev, false);
+}
+
static struct phy_driver icplus_driver[] = {
{
PHY_ID_MATCH_MODEL(IP175C_PHY_ID),
@@ -320,9 +374,18 @@ static struct phy_driver icplus_driver[] = {
.suspend = genphy_suspend,
.resume = genphy_resume,
}, {
- PHY_ID_MATCH_EXACT(IP101A_PHY_ID),
- .name = "ICPlus IP101A/G",
- /* PHY_BASIC_FEATURES */
+ .name = "ICPlus IP101A",
+ .match_phy_device = ip101a_match_phy_device,
+ .probe = ip101a_g_probe,
+ .config_intr = ip101a_g_config_intr,
+ .handle_interrupt = ip101a_g_handle_interrupt,
+ .config_init = ip101a_g_config_init,
+ .soft_reset = genphy_soft_reset,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+}, {
+ .name = "ICPlus IP101G",
+ .match_phy_device = ip101g_match_phy_device,
.probe = ip101a_g_probe,
.config_intr = ip101a_g_config_intr,
.handle_interrupt = ip101a_g_handle_interrupt,
--
2.20.1
Hello:
This series was applied to netdev/net-next.git (refs/heads/master):
On Thu, 11 Feb 2021 08:47:41 +0100 you wrote:
> Cleanup the PHY drivers for IPplus devices and add PHY counters and MDIX
> support for the IP101A/G.
>
> Patch 5 adds a model detection based on the behavior of the PHY.
> Unfortunately, the IP101A shares the PHY ID with the IP101G. But the latter
> provides more features. Try to detect the newer model by accessing the page
> selection register. If it is writeable, it is assumed, that it is a IP101G.
>
> [...]
Here is the summary with links:
- [net-next,v4,1/9] net: phy: icplus: use PHY_ID_MATCH_MODEL() macro
https://git.kernel.org/netdev/net-next/c/2ad4758cec48
- [net-next,v4,2/9] net: phy: icplus: use PHY_ID_MATCH_EXACT() for IP101A/G
https://git.kernel.org/netdev/net-next/c/7360a4de36a4
- [net-next,v4,3/9] net: phy: icplus: drop address operator for functions
https://git.kernel.org/netdev/net-next/c/8edf206cc2b5
- [net-next,v4,4/9] net: phy: icplus: use the .soft_reset() of the phy-core
https://git.kernel.org/netdev/net-next/c/df22de9a6f13
- [net-next,v4,5/9] net: phy: icplus: split IP101A/G driver
https://git.kernel.org/netdev/net-next/c/675115bf8c3d
- [net-next,v4,6/9] net: phy: icplus: don't set APS_EN bit on IP101G
https://git.kernel.org/netdev/net-next/c/eeac7d43d4dd
- [net-next,v4,7/9] net: phy: icplus: fix paged register access
https://git.kernel.org/netdev/net-next/c/f9bc51e6cce2
- [net-next,v4,8/9] net: phy: icplus: add PHY counter for IP101G
https://git.kernel.org/netdev/net-next/c/a0750d42e951
- [net-next,v4,9/9] net: phy: icplus: add MDI/MDIX support for IP101A/G
https://git.kernel.org/netdev/net-next/c/32ab60e53920
You are awesome, thank you!
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