2021-02-17 06:16:30

by Vincent Cheng

[permalink] [raw]
Subject: [PATCH v3 net-next 0/7] ptp: ptp_clockmatrix: Fix output 1 PPS alignment.

From: Vincent Cheng <[email protected]>

This series fixes a race condition that may result in the output clock
not aligned to internal 1 PPS clock.

Part of device initialization is to align the rising edge of output
clocks to the internal rising edge of the 1 PPS clock. If the system
APLL and DPLL are not locked when this alignment occurs, the alignment
fails and a fixed offset between the internal 1 PPS clock and the
output clock occurs.

If a clock is dynamically enabled after power-up, the output clock
also needs to be aligned to the internal 1 PPS clock.

v3:
Suggested by: Jakub Kicinski <[email protected]>
- Remove unnecessary 'err' variable
- Increase msleep()/loop accuracy by using jiffies in while()
- No empty lines between variables
- No empty lines between call and the if
- parenthesis around a == b are unnecessary
- Inconsistent \n usage in dev_()
- Remove unnecessary empty line
- Leave string format in place so static code checkers can
validate arguments

v2:
Suggested by: Richard Cochran <[email protected]>
- Added const to "char * fmt"
- Break unrelated header change into separate patch

Vincent Cheng (7):
ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.
ptp: ptp_clockmatrix: Add alignment of 1 PPS to idtcm_perout_enable.
ptp: ptp_clockmatrix: Remove unused header declarations.
ptp: ptp_clockmatrix: Clean-up dev_*() messages.
ptp: ptp_clockmatrix: Coding style - tighten vertical spacing.
ptp: ptp_clockmatrix: Simplify code - remove unnecessary `err`
variable.
ptp: ptp_clockmatrix: clean-up - parenthesis around a == b are
unnecessary

drivers/ptp/idt8a340_reg.h | 10 ++
drivers/ptp/ptp_clockmatrix.c | 313 ++++++++++++++++++------------------------
drivers/ptp/ptp_clockmatrix.h | 17 ++-
3 files changed, 162 insertions(+), 178 deletions(-)

--
2.7.4


2021-02-17 06:41:59

by Vincent Cheng

[permalink] [raw]
Subject: [PATCH v3 net-next 3/7] ptp: ptp_clockmatrix: Remove unused header declarations.

From: Vincent Cheng <[email protected]>

Removed unused header declarations.

Signed-off-by: Vincent Cheng <[email protected]>
---
drivers/ptp/ptp_clockmatrix.h | 2 --
1 file changed, 2 deletions(-)

diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h
index 0233236..fb32327 100644
--- a/drivers/ptp/ptp_clockmatrix.h
+++ b/drivers/ptp/ptp_clockmatrix.h
@@ -15,7 +15,6 @@
#define FW_FILENAME "idtcm.bin"
#define MAX_TOD (4)
#define MAX_PLL (8)
-#define MAX_OUTPUT (12)

#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)

@@ -138,7 +137,6 @@ struct idtcm_channel {
enum pll_mode pll_mode;
u8 pll;
u16 output_mask;
- u8 output_phase_adj[MAX_OUTPUT][4];
};

struct idtcm {
--
2.7.4

2021-02-17 06:43:41

by Vincent Cheng

[permalink] [raw]
Subject: [PATCH v3 net-next 1/7] ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.

From: Vincent Cheng <[email protected]>

Part of the device initialization aligns the rising edge of the output
clock to the internal 1 PPS clock. If the system APLL and DPLL is not
locked, then the alignment will fail and there will be a fixed offset
between the internal 1 PPS clock and the output clock.

After loading the device firmware, poll the system APLL and DPLL for
locked state prior to initialization, timing out after 2 seconds.

Signed-off-by: Vincent Cheng <[email protected]>
Acked-by: Richard Cochran <[email protected]>
---
drivers/ptp/idt8a340_reg.h | 10 +++++++
drivers/ptp/ptp_clockmatrix.c | 64 +++++++++++++++++++++++++++++++++++++++++--
drivers/ptp/ptp_clockmatrix.h | 15 ++++++++++
3 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/drivers/ptp/idt8a340_reg.h b/drivers/ptp/idt8a340_reg.h
index a664dfe..ac524cf 100644
--- a/drivers/ptp/idt8a340_reg.h
+++ b/drivers/ptp/idt8a340_reg.h
@@ -122,6 +122,8 @@
#define OTP_SCSR_CONFIG_SELECT 0x0022

#define STATUS 0xc03c
+#define DPLL_SYS_STATUS 0x0020
+#define DPLL_SYS_APLL_STATUS 0x0021
#define USER_GPIO0_TO_7_STATUS 0x008a
#define USER_GPIO8_TO_15_STATUS 0x008b

@@ -707,4 +709,12 @@
/* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */
#define COMBO_MASTER_HOLD BIT(0)

+/* Bit definitions for DPLL_SYS_STATUS register */
+#define DPLL_SYS_STATE_MASK (0xf)
+
+/* Bit definitions for SYS_APLL_STATUS register */
+#define SYS_APLL_LOSS_LOCK_LIVE_MASK BIT(0)
+#define SYS_APLL_LOSS_LOCK_LIVE_LOCKED 0
+#define SYS_APLL_LOSS_LOCK_LIVE_UNLOCKED 1
+
#endif
diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c
index 051511f..9bfd32b 100644
--- a/drivers/ptp/ptp_clockmatrix.c
+++ b/drivers/ptp/ptp_clockmatrix.c
@@ -335,6 +335,67 @@ static int wait_for_boot_status_ready(struct idtcm *idtcm)
return -EBUSY;
}

+static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
+{
+ return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status,
+ sizeof(u8));
+}
+
+static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status)
+{
+ return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8));
+}
+
+static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS);
+ u8 apll = 0;
+ u8 dpll = 0;
+ int err;
+
+ do {
+ err = read_sys_apll_status(idtcm, &apll);
+ if (err)
+ return err;
+
+ err = read_sys_dpll_status(idtcm, &dpll);
+ if (err)
+ return err;
+
+ apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK;
+ dpll &= DPLL_SYS_STATE_MASK;
+
+ if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED &&
+ dpll == DPLL_STATE_LOCKED) {
+ return 0;
+ } else if (dpll == DPLL_STATE_FREERUN ||
+ dpll == DPLL_STATE_HOLDOVER ||
+ dpll == DPLL_STATE_OPEN_LOOP) {
+ dev_warn(&idtcm->client->dev,
+ "No wait state: DPLL_SYS_STATE %d", dpll);
+ return -EPERM;
+ }
+
+ msleep(LOCK_POLL_INTERVAL_MS);
+ } while (time_is_after_jiffies(timeout));
+
+ dev_warn(&idtcm->client->dev,
+ "%d ms lock timeout: SYS APLL Loss Lock %d SYS DPLL state %d",
+ LOCK_TIMEOUT_MS, apll, dpll);
+
+ return -ETIME;
+}
+
+static void wait_for_chip_ready(struct idtcm *idtcm)
+{
+ if (wait_for_boot_status_ready(idtcm))
+ dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0");
+
+ if (wait_for_sys_apll_dpll_lock(idtcm))
+ dev_warn(&idtcm->client->dev,
+ "Continuing while SYS APLL/DPLL is not locked");
+}
+
static int _idtcm_gettime(struct idtcm_channel *channel,
struct timespec64 *ts)
{
@@ -2235,8 +2296,7 @@ static int idtcm_probe(struct i2c_client *client,
dev_warn(&idtcm->client->dev,
"loading firmware failed with %d\n", err);

- if (wait_for_boot_status_ready(idtcm))
- dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0\n");
+ wait_for_chip_ready(idtcm);

if (idtcm->tod_mask) {
for (i = 0; i < MAX_TOD; i++) {
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h
index 645de2c..0233236 100644
--- a/drivers/ptp/ptp_clockmatrix.h
+++ b/drivers/ptp/ptp_clockmatrix.h
@@ -51,6 +51,9 @@
#define TOD_WRITE_OVERHEAD_COUNT_MAX (2)
#define TOD_BYTE_COUNT (11)

+#define LOCK_TIMEOUT_MS (2000)
+#define LOCK_POLL_INTERVAL_MS (10)
+
#define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef)

#define IDTCM_MAX_WRITE_COUNT (512)
@@ -105,6 +108,18 @@ enum scsr_tod_write_type_sel {
SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
};

+/* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */
+enum dpll_state {
+ DPLL_STATE_MIN = 0,
+ DPLL_STATE_FREERUN = DPLL_STATE_MIN,
+ DPLL_STATE_LOCKACQ = 1,
+ DPLL_STATE_LOCKREC = 2,
+ DPLL_STATE_LOCKED = 3,
+ DPLL_STATE_HOLDOVER = 4,
+ DPLL_STATE_OPEN_LOOP = 5,
+ DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP,
+};
+
struct idtcm;

struct idtcm_channel {
--
2.7.4

2021-02-17 22:04:53

by patchwork-bot+netdevbpf

[permalink] [raw]
Subject: Re: [PATCH v3 net-next 0/7] ptp: ptp_clockmatrix: Fix output 1 PPS alignment.

Hello:

This series was applied to netdev/net-next.git (refs/heads/master):

On Wed, 17 Feb 2021 00:42:11 -0500 you wrote:
> From: Vincent Cheng <[email protected]>
>
> This series fixes a race condition that may result in the output clock
> not aligned to internal 1 PPS clock.
>
> Part of device initialization is to align the rising edge of output
> clocks to the internal rising edge of the 1 PPS clock. If the system
> APLL and DPLL are not locked when this alignment occurs, the alignment
> fails and a fixed offset between the internal 1 PPS clock and the
> output clock occurs.
>
> [...]

Here is the summary with links:
- [v3,net-next,1/7] ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.
https://git.kernel.org/netdev/net-next/c/797d3186544f
- [v3,net-next,2/7] ptp: ptp_clockmatrix: Add alignment of 1 PPS to idtcm_perout_enable.
https://git.kernel.org/netdev/net-next/c/e8b4d8b542b1
- [v3,net-next,3/7] ptp: ptp_clockmatrix: Remove unused header declarations.
https://git.kernel.org/netdev/net-next/c/10c270cf25bd
- [v3,net-next,4/7] ptp: ptp_clockmatrix: Clean-up dev_*() messages.
https://git.kernel.org/netdev/net-next/c/1c49d3e94778
- [v3,net-next,5/7] ptp: ptp_clockmatrix: Coding style - tighten vertical spacing.
https://git.kernel.org/netdev/net-next/c/fcfd37573a09
- [v3,net-next,6/7] ptp: ptp_clockmatrix: Simplify code - remove unnecessary `err` variable.
https://git.kernel.org/netdev/net-next/c/fde3b3a7069e
- [v3,net-next,7/7] ptp: ptp_clockmatrix: clean-up - parenthesis around a == b are unnecessary
https://git.kernel.org/netdev/net-next/c/77fdb168a3e2

You are awesome, thank you!
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