LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
boot protocol LoongArch-specific interrupt controllers (similar to APIC)
are already added in the ACPI Specification 6.5(which may be published in
early June this year and the board is reviewing the draft).
Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
work together with LS7A chipsets. The irq chips in LoongArch computers
include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are
per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are all
controllers out of CPU (i.e., in chipsets). These controllers (in other
words, irqchips) are linked in a hierarchy, and there are two models of
hierarchy (legacy model and extended model).
Legacy IRQ model:
In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC.
+---------------------------------------------+
| |
| +-----+ +---------+ +-------+ |
| | IPI | --> | CPUINTC | <-- | Timer | |
| +-----+ +---------+ +-------+ |
| ^ |
| | |
| +---------+ +-------+ |
| | LIOINTC | <-- | UARTs | |
| +---------+ +-------+ |
| ^ |
| | |
| +-----------+ |
| | HTVECINTC | |
| +-----------+ |
| ^ ^ |
| | | |
| +---------+ +---------+ |
| | PCH-PIC | | PCH-MSI | |
| +---------+ +---------+ |
| ^ ^ ^ |
| | | | |
| +---------+ +---------+ +---------+ |
| | PCH-LPC | | Devices | | Devices | |
| +---------+ +---------+ +---------+ |
| ^ |
| | |
| +---------+ |
| | Devices | |
| +---------+ |
| |
| |
+---------------------------------------------+
Extended IRQ model:
In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
gathered by EIOINTC, and then go to to CPUINTC directly.
+--------------------------------------------------------+
| |
| +-----+ +---------+ +-------+ |
| | IPI | --> | CPUINTC | <-- | Timer | |
| +-----+ +---------+ +-------+ |
| ^ ^ |
| | | |
| +---------+ +---------+ +-------+ |
| | EIOINTC | | LIOINTC | <-- | UARTs | |
| +---------+ +---------+ +-------+ |
| ^ ^ |
| | | |
| +---------+ +---------+ |
| | PCH-PIC | | PCH-MSI | |
| +---------+ +---------+ |
| ^ ^ ^ |
| | | | |
| +---------+ +---------+ +---------+ |
| | PCH-LPC | | Devices | | Devices | |
| +---------+ +---------+ +---------+ |
| ^ |
| | |
| +---------+ |
| | Devices | |
| +---------+ |
| |
| |
+--------------------------------------------------------+
The hierarchy model is constructed by parsing irq contronler structures
in MADT. Some controllers((e.g. LIOINTC, HTVECINTC, EIOINTC and PCH-LPC)
are hardcodingly connected to their parents, so their irqdomins are
separately routed to their parents in a fixed way. Some controllers
(e.g. PCH-PIC and PCH-MSI) could be routed to different parents for different
CPU. The firmware will config EIOINTC for the newer CPU and config HTVECINTC
for old CPU in MADT. By this way, PCH-PIC and PCH-MSI irqdomain can only be
routed one parent irqdomin: HTVECINTC or EIOINTC.
Example of irqchip topology in a system with two chipsets:
+------------------------------------------------------------+
| |
| +------------------+ |
| | CPUINTC | |
| +------------------+ |
| ^ ^ |
| | | |
| +----------+ +----------+ |
| | EIOINTC 0| | EIOINTC 1| |
| +----------+ +----------+ |
| ^ ^ ^ ^ |
| | | | | |
| +----------+ +----------+ +----------+ +----------+ |
| | PCH-PIC 0| | PCH-MSI 0| | PCH-PIC 1| | PCH-MSI 1| |
| +----------+ +----------+ +----------+ +----------+ |
| |
| |
+------------------------------------------------------------+
For systems with two chipsets, there are tow group(consists of EIOINTC, PCH-PIC and PCH-MSI) irqdomains,
and each group has same node id. So we defined a structure to mantain the relation of node and it's parent irqdomain.
struct acpi_vector_group {
int node;
struct irq_domain *parent;
};
The initialization and use of acpi_vector_group array are following:
1 Entry of struct acpi_vector_group array initialization:
By parsing MCFG, the node id（from bit44-47 of Base Address）of each pci segment is extracted. And from MADT, we have the node id of each EIOINTC.
entrys[pci segment].node = node id of pci segment
entrys[pci segment].parent = EIOINTC irqdomain(node id of EIOINTC == node id of pci segment)
2 Get parent irqdomain for PCH-PIC:
From MADT, we have the node id of each PCH-PIC(from bit44-47 of Base Address).
if (node of entry i == node of PCH-PIC)
return entrys[i].parent;
entrys[pci segment].node = node id of pci segment
entrys[pci segment].parent = EIOINTC irqdomain(node id of EIOINTC == node id of pci segment)
3 Get parent irqdomain for PCH-MSI of pci segment:
return entrys[pci segment].parent;
4 How to select a correct irqdomain to map irq for a device?
For devices using legacy irq behind PCH-PIC, GSI is used to select correct PCH-PIC irqdomain.
For devices using msi irq behind PCH-MSI, the pci segmen of the device is used to select correct PCH-MSI irqdomain.
V1 -> V2:
1, Remove queued patches;
2, Move common logic of DT/ACPI probing to common functions;
3, Split .suspend()/.resume() functions to separate patches.
V2 -> V3:
1, Fix a bug for loongson-pch-pic probe;
2, Some minor improvements for LPC controller.
V3 -> V4:
1, Rework the CPU interrupt controller driver;
2, Some minor improvements for other controllers.
V4 -> V5:
1, Add a description of LoonArch's IRQ model;
2, Support multiple EIOINTCs in one system;
3, Some minor improvements for other controllers.
V5 -> V6:
1, Attach a fwnode to CPUINTC irq domain;
2, Use raw spinlock instead of generic spinlock;
3, Improve the method of restoring EIOINTC state;
4, Update documentation, comments and commit messages.
V6 -> V7:
1, Fix build warnings reported by kernel test robot.
V7 -> V8:
1, Add arguments sanity checking for irqchip init functions;
2, Support Loongson-3C5000 (One NUMA Node includes 4 EIOINTC Node).
V8 -> V9:
1, Rebase on 5.17-rc5;
2, Update cover letter;
3, Some small improvements.
V9 -> V10:
1, Rebase on 5.17-rc6;
2, Fix build warnings reported by kernel test robot.
V10 -> V11:
1, Rebase on 5.18-rc4;
2, Fix irq affinity setting for EIOINTC;
3, Fix hwirq allocation failure for EIOINTC.
V11 -> RFC:
1, Refactored the way to build irqchip hierarchy topology.
RFC -> RFC V2:
1, Move all IO-interrupt related code to driver/irqchip from arch directory.
2. Add description for an example of two chipsets system.
RFC V2 -> RFC V3:
1, Add support for multiple GSI domains
2, Use ACPI_GENERIC_GSI for GSI handling
3, Drop suspend-resume stuff
4, Export fwnode handles instead of irq domain handles
Huacai Chen (1):
irqchip: Adjust Kconfig for Loongson
Jianmin Lv (10):
APCI: irq: Add support for multiple GSI domains
genirq/generic_chip: export irq_unmap_generic_chip
irqchip: Add LoongArch CPU interrupt controller support
irqchip: create library file for LoongArch irqchip driver
irqchip/loongson-pch-pic: Add ACPI init support
irqchip/loongson-pch-msi: Add ACPI init support
irqchip/loongson-htvec: Add ACPI init support
irqchip/loongson-liointc: Add ACPI init support
irqchip: Add Loongson Extended I/O interrupt controller support
irqchip: Add Loongson PCH LPC controller support
drivers/acpi/bus.c | 3 +
drivers/acpi/irq.c | 40 ++--
drivers/irqchip/Kconfig | 38 +++-
drivers/irqchip/Makefile | 3 +
drivers/irqchip/irq-gic-v3.c | 18 +-
drivers/irqchip/irq-gic.c | 18 +-
drivers/irqchip/irq-loongarch-cpu.c | 134 +++++++++++
drivers/irqchip/irq-loongarch-pic-common.c | 122 ++++++++++
drivers/irqchip/irq-loongarch-pic-common.h | 39 ++++
drivers/irqchip/irq-loongson-eiointc.c | 347 +++++++++++++++++++++++++++++
drivers/irqchip/irq-loongson-htvec.c | 119 +++++++---
drivers/irqchip/irq-loongson-liointc.c | 232 ++++++++++++-------
drivers/irqchip/irq-loongson-pch-lpc.c | 202 +++++++++++++++++
drivers/irqchip/irq-loongson-pch-msi.c | 138 ++++++++----
drivers/irqchip/irq-loongson-pch-pic.c | 167 +++++++++++---
include/linux/acpi.h | 3 +-
include/linux/cpuhotplug.h | 1 +
include/linux/irq.h | 1 +
kernel/irq/generic-chip.c | 2 +-
19 files changed, 1409 insertions(+), 218 deletions(-)
create mode 100644 drivers/irqchip/irq-loongarch-cpu.c
create mode 100644 drivers/irqchip/irq-loongarch-pic-common.c
create mode 100644 drivers/irqchip/irq-loongarch-pic-common.h
create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c
--
1.8.3.1
On Sat, 11 Jun 2022 15:02:35 +0100,
Jianmin Lv <[email protected]> wrote:
>
> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
> are already added in the ACPI Specification 6.5(which may be published in
> early June this year and the board is reviewing the draft).
Can you please make an effort to send patches in coherent way? Here's
what I see in my email reader:
[PATCH RFC V2 00/10] irqchip: Add LoongArch-related irqchip drivers
+[PATCH RFC V3 01/11] APCI: irq: Add support for multiple GSI domains
+[PATCH RFC V3 02/11] genirq/generic_chip: export irq_unmap_generic_chip
+[PATCH RFC V3 03/11] irqchip: Adjust Kconfig for Loongson
+[PATCH RFC V3 04/11] irqchip: Add LoongArch CPU interrupt controller support
\[PATCH RFC V3 05/11] irqchip: create library file for LoongArch irqchip driver
[PATCH RFC V3 06/11] irqchip/loongson-pch-pic: Add ACPI init support
+[PATCH RFC V3 07/11] irqchip/loongson-pch-msi: Add ACPI init support
+[PATCH RFC V3 08/11] irqchip/loongson-htvec: Add ACPI init support
+[PATCH RFC V3 09/11] irqchip/loongson-liointc: Add ACPI init support
+[PATCH RFC V3 10/11] irqchip: Add Loongson Extended I/O interrupt controller support
\[PATCH RFC V3 11/11] irqchip: Add Loongson PCH LPC controller support
[PATCH RFC V3 00/11] irqchip: Add LoongArch-related irqchip drivers
Three threads, with inconsistent version numbers, inconsistent patch
numbering, with a split in the middle, and this final cover letter
that isn't followed by anything. If you make a mistake, that's
fine. Fix it, and resend the series properly, possibly with a new
version number. Pro tip: you should only use 'git send-email', and
only once to send all your patches after having written the cover
letter. If you have to do anything else, you're doing something
wrong.
Also, please drop this 'RFC', as we're way past the RFC stage (to me,
RFC means "I don't know what I'm doing yet, this is not ready to be
merged").
[...]
> Jianmin Lv (10):
> APCI: irq: Add support for multiple GSI domains
I'm usually not too attached to authorship, but I definitely wrote
that one, and that casts some doubt on the authorship of all the
patches. For example, patch #4 has:
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Jianmin Lv <[email protected]>
but doesn't list Huacai Chen as the author. Either they are, and the
patch needs a From: line like in patch #3, or this is co-developed,
and you need the Co-Developed: tag ([1] has all the details).
I'll go and review the actual patches before the end of the week, but
you definitely need to address the patch attributions in this series.
Thanks,
M.
[1] Documentation/process/submitting-patches.rst
--
Without deviation from the norm, progress is not possible.
On 2022/6/15 上午12:25, Marc Zyngier wrote:
> On Sat, 11 Jun 2022 15:02:35 +0100,
> Jianmin Lv <[email protected]> wrote:
>>
>> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
>> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
>> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
>> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
>> are already added in the ACPI Specification 6.5(which may be published in
>> early June this year and the board is reviewing the draft).
>
> Can you please make an effort to send patches in coherent way? Here's
> what I see in my email reader:
>
> [PATCH RFC V2 00/10] irqchip: Add LoongArch-related irqchip drivers
> +[PATCH RFC V3 01/11] APCI: irq: Add support for multiple GSI domains
> +[PATCH RFC V3 02/11] genirq/generic_chip: export irq_unmap_generic_chip
> +[PATCH RFC V3 03/11] irqchip: Adjust Kconfig for Loongson
> +[PATCH RFC V3 04/11] irqchip: Add LoongArch CPU interrupt controller support
> \[PATCH RFC V3 05/11] irqchip: create library file for LoongArch irqchip driver
> [PATCH RFC V3 06/11] irqchip/loongson-pch-pic: Add ACPI init support
> +[PATCH RFC V3 07/11] irqchip/loongson-pch-msi: Add ACPI init support
> +[PATCH RFC V3 08/11] irqchip/loongson-htvec: Add ACPI init support
> +[PATCH RFC V3 09/11] irqchip/loongson-liointc: Add ACPI init support
> +[PATCH RFC V3 10/11] irqchip: Add Loongson Extended I/O interrupt controller support
> \[PATCH RFC V3 11/11] irqchip: Add Loongson PCH LPC controller support
> [PATCH RFC V3 00/11] irqchip: Add LoongArch-related irqchip drivers
>
> Three threads, with inconsistent version numbers, inconsistent patch
> numbering, with a split in the middle, and this final cover letter
> that isn't followed by anything. If you make a mistake, that's
> fine. Fix it, and resend the series properly, possibly with a new
> version number. Pro tip: you should only use 'git send-email', and
> only once to send all your patches after having written the cover
> letter. If you have to do anything else, you're doing something
> wrong.
>
Yes, Marc, thanks for your guidance. It's my mistake that I sent an old
cover letter when sending the patch series， so I sent a correct cover
letter after I found the mistake. I'll do it carefully in future.
> Also, please drop this 'RFC', as we're way past the RFC stage (to me,
> RFC means "I don't know what I'm doing yet, this is not ready to be
> merged").
>
Ok, I'll resend the series properly without 'RFC'.
> [...]
>
>> Jianmin Lv (10):
>> APCI: irq: Add support for multiple GSI domains
>
> I'm usually not too attached to authorship, but I definitely wrote
> that one, and that casts some doubt on the authorship of all the
> patches. For example, patch #4 has:
>
> Signed-off-by: Huacai Chen <[email protected]>
> Signed-off-by: Jianmin Lv <[email protected]>
>
> but doesn't list Huacai Chen as the author. Either they are, and the
> patch needs a From: line like in patch #3, or this is co-developed,
> and you need the Co-Developed: tag ([1] has all the details).
>
Thanks for your guidance again, I'm so sorry and please forgive
my ignorance about these rules. I'll do it as your guidance here
in future.
> I'll go and review the actual patches before the end of the week, but
> you definitely need to address the patch attributions in this series.
>
Ok, I'll address the patch attributions in this series as soon as
possible and resend it.
> Thanks,
>
> M.
>
> [1] Documentation/process/submitting-patches.rst
>