IBS_OP_DATA2 DataSrc provides detail about location of the data
being accessed from by load ops. Define macros for legacy and
extended DataSrc values.
Signed-off-by: Ravi Bangoria <[email protected]>
---
arch/x86/include/asm/amd-ibs.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
index f3eb098d63d4..cb2a5e113daa 100644
--- a/arch/x86/include/asm/amd-ibs.h
+++ b/arch/x86/include/asm/amd-ibs.h
@@ -6,6 +6,22 @@
#include <asm/msr-index.h>
+/* IBS_OP_DATA2 DataSrc */
+#define IBS_DATA_SRC_LOC_CACHE 2
+#define IBS_DATA_SRC_DRAM 3
+#define IBS_DATA_SRC_REM_CACHE 4
+#define IBS_DATA_SRC_IO 7
+
+/* IBS_OP_DATA2 DataSrc Extension */
+#define IBS_DATA_SRC_EXT_LOC_CACHE 1
+#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2
+#define IBS_DATA_SRC_EXT_DRAM 3
+#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5
+#define IBS_DATA_SRC_EXT_PMEM 6
+#define IBS_DATA_SRC_EXT_IO 7
+#define IBS_DATA_SRC_EXT_EXT_MEM 8
+#define IBS_DATA_SRC_EXT_PEER_AGENT_MEM 12
+
/*
* IBS Hardware MSRs
*/
--
2.31.1
Hi Ravi,
On Wed, Sep 28, 2022 at 2:59 AM Ravi Bangoria <[email protected]> wrote:
>
> IBS_OP_DATA2 DataSrc provides detail about location of the data
> being accessed from by load ops. Define macros for legacy and
> extended DataSrc values.
>
> Signed-off-by: Ravi Bangoria <[email protected]>
> ---
> arch/x86/include/asm/amd-ibs.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
> index f3eb098d63d4..cb2a5e113daa 100644
> --- a/arch/x86/include/asm/amd-ibs.h
> +++ b/arch/x86/include/asm/amd-ibs.h
> @@ -6,6 +6,22 @@
>
> #include <asm/msr-index.h>
>
> +/* IBS_OP_DATA2 DataSrc */
> +#define IBS_DATA_SRC_LOC_CACHE 2
> +#define IBS_DATA_SRC_DRAM 3
> +#define IBS_DATA_SRC_REM_CACHE 4
> +#define IBS_DATA_SRC_IO 7
> +
> +/* IBS_OP_DATA2 DataSrc Extension */
> +#define IBS_DATA_SRC_EXT_LOC_CACHE 1
> +#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2
> +#define IBS_DATA_SRC_EXT_DRAM 3
> +#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5
Is 4 undefined intentionally?
Thanks,
Namhyung
> +#define IBS_DATA_SRC_EXT_PMEM 6
> +#define IBS_DATA_SRC_EXT_IO 7
> +#define IBS_DATA_SRC_EXT_EXT_MEM 8
> +#define IBS_DATA_SRC_EXT_PEER_AGENT_MEM 12
> +
> /*
> * IBS Hardware MSRs
> */
> --
> 2.31.1
>
On 30-Sep-22 10:11 AM, Namhyung Kim wrote:
> Hi Ravi,
>
> On Wed, Sep 28, 2022 at 2:59 AM Ravi Bangoria <[email protected]> wrote:
>>
>> IBS_OP_DATA2 DataSrc provides detail about location of the data
>> being accessed from by load ops. Define macros for legacy and
>> extended DataSrc values.
>>
>> Signed-off-by: Ravi Bangoria <[email protected]>
>> ---
>> arch/x86/include/asm/amd-ibs.h | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
>> index f3eb098d63d4..cb2a5e113daa 100644
>> --- a/arch/x86/include/asm/amd-ibs.h
>> +++ b/arch/x86/include/asm/amd-ibs.h
>> @@ -6,6 +6,22 @@
>>
>> #include <asm/msr-index.h>
>>
>> +/* IBS_OP_DATA2 DataSrc */
>> +#define IBS_DATA_SRC_LOC_CACHE 2
>> +#define IBS_DATA_SRC_DRAM 3
>> +#define IBS_DATA_SRC_REM_CACHE 4
>> +#define IBS_DATA_SRC_IO 7
>> +
>> +/* IBS_OP_DATA2 DataSrc Extension */
>> +#define IBS_DATA_SRC_EXT_LOC_CACHE 1
>> +#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2
>> +#define IBS_DATA_SRC_EXT_DRAM 3
>> +#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5
>
> Is 4 undefined intentionally?
Yes, Here is the snippet from PPR (Processor Programming Reference) doc:
Values | Description
---------------------------------------------------------------------
0h | No valid status.
1h | Local L3 or other L1/L2 in CCX.
2h | Another CCX cache in the same NUMA node.
3h | DRAM.
4h | Reserved.
5h | Another CCX cache in a different NUMA node.
6h | DRAM address map with "long latency" bit set.
7h | MMIO/Config/PCI/APIC.
8h | Extension Memory (S-Link, GenZ, etc - identified by the CS
| target and/or address map at DF's choice).
9h-Bh | Reserved.
Ch | Peer Agent Memory.
Dh-1Fh | Reserved.
Thanks,
Ravi
On Thu, Sep 29, 2022 at 9:49 PM Ravi Bangoria <[email protected]> wrote:
>
> On 30-Sep-22 10:11 AM, Namhyung Kim wrote:
> > Hi Ravi,
> >
> > On Wed, Sep 28, 2022 at 2:59 AM Ravi Bangoria <[email protected]> wrote:
> >>
> >> IBS_OP_DATA2 DataSrc provides detail about location of the data
> >> being accessed from by load ops. Define macros for legacy and
> >> extended DataSrc values.
> >>
> >> Signed-off-by: Ravi Bangoria <[email protected]>
> >> ---
> >> arch/x86/include/asm/amd-ibs.h | 16 ++++++++++++++++
> >> 1 file changed, 16 insertions(+)
> >>
> >> diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
> >> index f3eb098d63d4..cb2a5e113daa 100644
> >> --- a/arch/x86/include/asm/amd-ibs.h
> >> +++ b/arch/x86/include/asm/amd-ibs.h
> >> @@ -6,6 +6,22 @@
> >>
> >> #include <asm/msr-index.h>
> >>
> >> +/* IBS_OP_DATA2 DataSrc */
> >> +#define IBS_DATA_SRC_LOC_CACHE 2
> >> +#define IBS_DATA_SRC_DRAM 3
> >> +#define IBS_DATA_SRC_REM_CACHE 4
> >> +#define IBS_DATA_SRC_IO 7
> >> +
> >> +/* IBS_OP_DATA2 DataSrc Extension */
> >> +#define IBS_DATA_SRC_EXT_LOC_CACHE 1
> >> +#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2
> >> +#define IBS_DATA_SRC_EXT_DRAM 3
> >> +#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5
> >
> > Is 4 undefined intentionally?
>
> Yes, Here is the snippet from PPR (Processor Programming Reference) doc:
>
> Values | Description
> ---------------------------------------------------------------------
> 0h | No valid status.
> 1h | Local L3 or other L1/L2 in CCX.
> 2h | Another CCX cache in the same NUMA node.
> 3h | DRAM.
> 4h | Reserved.
> 5h | Another CCX cache in a different NUMA node.
> 6h | DRAM address map with "long latency" bit set.
> 7h | MMIO/Config/PCI/APIC.
> 8h | Extension Memory (S-Link, GenZ, etc - identified by the CS
> | target and/or address map at DF's choice).
> 9h-Bh | Reserved.
> Ch | Peer Agent Memory.
> Dh-1Fh | Reserved.
Thanks for sharing it. It's a bit confusing since it was available before.
Anyway, is the PPR for Zen4 publicly available now?
Thanks,
Namhyung
>>>> +/* IBS_OP_DATA2 DataSrc */
>>>> +#define IBS_DATA_SRC_LOC_CACHE 2
>>>> +#define IBS_DATA_SRC_DRAM 3
>>>> +#define IBS_DATA_SRC_REM_CACHE 4
>>>> +#define IBS_DATA_SRC_IO 7
>>>> +
>>>> +/* IBS_OP_DATA2 DataSrc Extension */
>>>> +#define IBS_DATA_SRC_EXT_LOC_CACHE 1
>>>> +#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2
>>>> +#define IBS_DATA_SRC_EXT_DRAM 3
>>>> +#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5
>>>
>>> Is 4 undefined intentionally?
>>
>> Yes, Here is the snippet from PPR (Processor Programming Reference) doc:
>>
>> Values | Description
>> ---------------------------------------------------------------------
>> 0h | No valid status.
>> 1h | Local L3 or other L1/L2 in CCX.
>> 2h | Another CCX cache in the same NUMA node.
>> 3h | DRAM.
>> 4h | Reserved.
>> 5h | Another CCX cache in a different NUMA node.
>> 6h | DRAM address map with "long latency" bit set.
>> 7h | MMIO/Config/PCI/APIC.
>> 8h | Extension Memory (S-Link, GenZ, etc - identified by the CS
>> | target and/or address map at DF's choice).
>> 9h-Bh | Reserved.
>> Ch | Peer Agent Memory.
>> Dh-1Fh | Reserved.
>
> Thanks for sharing it. It's a bit confusing since it was available before.
Right, these bit definitions have changed in Zen4.
>
> Anyway, is the PPR for Zen4 publicly available now?
Sadly, no. But it's in progress.
Thanks,
Ravi
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 610c238041fbc682936d34132362a54a802600fe
Gitweb: https://git.kernel.org/tip/610c238041fbc682936d34132362a54a802600fe
Author: Ravi Bangoria <[email protected]>
AuthorDate: Wed, 28 Sep 2022 15:27:52 +05:30
Committer: Peter Zijlstra <[email protected]>
CommitterDate: Thu, 29 Sep 2022 12:20:54 +02:00
perf/x86/amd: Add IBS OP_DATA2 DataSrc bit definitions
IBS_OP_DATA2 DataSrc provides detail about location of the data
being accessed from by load ops. Define macros for legacy and
extended DataSrc values.
Signed-off-by: Ravi Bangoria <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
---
arch/x86/include/asm/amd-ibs.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
index f3eb098..cb2a5e1 100644
--- a/arch/x86/include/asm/amd-ibs.h
+++ b/arch/x86/include/asm/amd-ibs.h
@@ -6,6 +6,22 @@
#include <asm/msr-index.h>
+/* IBS_OP_DATA2 DataSrc */
+#define IBS_DATA_SRC_LOC_CACHE 2
+#define IBS_DATA_SRC_DRAM 3
+#define IBS_DATA_SRC_REM_CACHE 4
+#define IBS_DATA_SRC_IO 7
+
+/* IBS_OP_DATA2 DataSrc Extension */
+#define IBS_DATA_SRC_EXT_LOC_CACHE 1
+#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2
+#define IBS_DATA_SRC_EXT_DRAM 3
+#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5
+#define IBS_DATA_SRC_EXT_PMEM 6
+#define IBS_DATA_SRC_EXT_IO 7
+#define IBS_DATA_SRC_EXT_EXT_MEM 8
+#define IBS_DATA_SRC_EXT_PEER_AGENT_MEM 12
+
/*
* IBS Hardware MSRs
*/