2022-09-27 03:40:24

by Zhangshaokun

[permalink] [raw]
Subject: [PATCH v2] clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value

From: Yang Guo <[email protected]>

CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f883a7',
so fix them according to the Arm ARM DDI 0487I.a, Table I2-4
"CNTBaseN memory map" as follows:

Offset Register Type Description
0x000 CNTPCT[31:0] RO Physical Count register.
0x004 CNTPCT[63:32] RO
0x008 CNTVCT[31:0] RO Virtual Count register.
0x00C CNTVCT[63:32] RO

Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL")
Cc: [email protected]
Cc: Daniel Lezcano <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Marc Zyngier <[email protected]>
Cc: Mark Rutland <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Yang Guo <[email protected]>
Signed-off-by: Shaokun Zhang <[email protected]>
---
drivers/clocksource/arm_arch_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 9ab8221ee3c6..8122a1646925 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -44,8 +44,8 @@
#define CNTACR_RWVT BIT(4)
#define CNTACR_RWPT BIT(5)

-#define CNTVCT_LO 0x00
-#define CNTPCT_LO 0x08
+#define CNTPCT_LO 0x00
+#define CNTVCT_LO 0x08
#define CNTFRQ 0x10
#define CNTP_CVAL_LO 0x20
#define CNTP_CTL 0x2c
--
2.33.0


2022-09-27 10:37:55

by Daniel Lezcano

[permalink] [raw]
Subject: Re: [PATCH v2] clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value

On 27/09/2022 05:32, Shaokun Zhang wrote:
> From: Yang Guo <[email protected]>
>
> CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f883a7',
> so fix them according to the Arm ARM DDI 0487I.a, Table I2-4
> "CNTBaseN memory map" as follows:
>
> Offset Register Type Description
> 0x000 CNTPCT[31:0] RO Physical Count register.
> 0x004 CNTPCT[63:32] RO
> 0x008 CNTVCT[31:0] RO Virtual Count register.
> 0x00C CNTVCT[63:32] RO
>
> Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL")
> Cc: [email protected]
> Cc: Daniel Lezcano <[email protected]>
> Cc: Thomas Gleixner <[email protected]>
> Cc: Marc Zyngier <[email protected]>
> Cc: Mark Rutland <[email protected]>
> Acked-by: Marc Zyngier <[email protected]>
> Signed-off-by: Yang Guo <[email protected]>
> Signed-off-by: Shaokun Zhang <[email protected]>
> ---

Applied, thanks

> drivers/clocksource/arm_arch_timer.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index 9ab8221ee3c6..8122a1646925 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -44,8 +44,8 @@
> #define CNTACR_RWVT BIT(4)
> #define CNTACR_RWPT BIT(5)
>
> -#define CNTVCT_LO 0x00
> -#define CNTPCT_LO 0x08
> +#define CNTPCT_LO 0x00
> +#define CNTVCT_LO 0x08
> #define CNTFRQ 0x10
> #define CNTP_CVAL_LO 0x20
> #define CNTP_CTL 0x2c


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Subject: [tip: timers/core] clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value

The following commit has been merged into the timers/core branch of tip:

Commit-ID: af246cc6d0ed11318223606128bb0b09866c4c08
Gitweb: https://git.kernel.org/tip/af246cc6d0ed11318223606128bb0b09866c4c08
Author: Yang Guo <[email protected]>
AuthorDate: Tue, 27 Sep 2022 11:32:21 +08:00
Committer: Daniel Lezcano <[email protected]>
CommitterDate: Tue, 27 Sep 2022 11:30:53 +02:00

clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value

CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f883a7',
so fix them according to the Arm ARM DDI 0487I.a, Table I2-4
"CNTBaseN memory map" as follows:

Offset Register Type Description
0x000 CNTPCT[31:0] RO Physical Count register.
0x004 CNTPCT[63:32] RO
0x008 CNTVCT[31:0] RO Virtual Count register.
0x00C CNTVCT[63:32] RO

Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL")
Cc: [email protected]
Cc: Daniel Lezcano <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Marc Zyngier <[email protected]>
Cc: Mark Rutland <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Yang Guo <[email protected]>
Signed-off-by: Shaokun Zhang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Daniel Lezcano <[email protected]>
---
drivers/clocksource/arm_arch_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index ff935ef..a7ff775 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -44,8 +44,8 @@
#define CNTACR_RWVT BIT(4)
#define CNTACR_RWPT BIT(5)

-#define CNTVCT_LO 0x00
-#define CNTPCT_LO 0x08
+#define CNTPCT_LO 0x00
+#define CNTVCT_LO 0x08
#define CNTFRQ 0x10
#define CNTP_CVAL_LO 0x20
#define CNTP_CTL 0x2c