Hi,
Changes in v4:
- Addressed comment from Dmitry to move the gpios to the board file.
Changes in v3:
- Removing the applied patch.
- Addressing some of the compile time issues missed in v2.
Changes in v2:
- Addressing comments from Konrad and Dmitry.
- Rebased on top of 6.3-rc1.
This series adds the devicetree support for PCIe PHY and PCIe EP on SDX65.
The PCIe EP is enabled on SDX65 MTP board.
Thanks,
Rohit.
Rohit Agarwal (5):
dt-bindings: PCI: qcom: Add SDX65 SoC
ARM: dts: qcom: sdx65: Add support for PCIe PHY
ARM: dts: qcom: sdx65: Add support for PCIe EP
ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY
ARM: dts: qcom: sdx65-mtp: Enable PCIe EP
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 +
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 50 ++++++++++++-
arch/arm/boot/dts/qcom-sdx65.dtsi | 87 ++++++++++++++++++++++
3 files changed, 136 insertions(+), 3 deletions(-)
--
2.7.4
Add PCIe EP compatible string for SDX65 SoC.
Signed-off-by: Rohit Agarwal <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 89cfdee..096540b 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -13,6 +13,7 @@ properties:
compatible:
enum:
- qcom,sdx55-pcie-ep
+ - qcom,sdx65-pcie-ep
- qcom,sm8450-pcie-ep
reg:
@@ -109,6 +110,7 @@ allOf:
contains:
enum:
- qcom,sdx55-pcie-ep
+ - qcom,sdx65-pcie-ep
then:
properties:
clocks:
--
2.7.4
Add support for PCIe Endpoint controller on the
Qualcomm SDX65 platform.
Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 56 +++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 084daf8..a7d8ad9 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
@@ -293,6 +294,56 @@
status = "disabled";
};
+ pcie_ep: pcie-ep@1c00000 {
+ compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
+ reg = <0x01c00000 0x3000>,
+ <0x40000000 0xf1d>,
+ <0x40000f20 0xa8>,
+ <0x40001000 0x1000>,
+ <0x40200000 0x100000>,
+ <0x01c03000 0x3000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "addr_space",
+ "mmio";
+
+ qcom,perst-regs = <&tcsr 0xb258 0xb270>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_SLEEP_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "sleep",
+ "ref";
+
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global", "doorbell";
+
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "core";
+
+ power-domains = <&gcc PCIE_GDSC>;
+
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+
+ max-link-speed = <3>;
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
+
pcie_phy: phy@1c06000 {
compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
reg = <0x01c06000 0x2000>;
@@ -330,6 +381,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fcb000 {
+ compatible = "qcom,sdx65-tcsr", "syscon";
+ reg = <0x01fc0000 0x1000>;
+ };
+
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sdx55-mpss-pas";
reg = <0x04080000 0x4040>;
--
2.7.4
Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
used by the PCIe EP controller.
Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 192f9f9..084daf8 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -293,6 +293,37 @@
status = "disabled";
};
+ pcie_phy: phy@1c06000 {
+ compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
+ reg = <0x01c06000 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_EN>,
+ <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
+ <&gcc GCC_PCIE_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ resets = <&gcc GCC_PCIE_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01f40000 0x40000>;
--
2.7.4
On Fri, Mar 17, 2023 at 12:23:57PM +0530, Rohit Agarwal wrote:
> Add support for PCIe Endpoint controller on the
> Qualcomm SDX65 platform.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 56 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 084daf8..a7d8ad9 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -11,6 +11,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/gpio/gpio.h>
>
> / {
> #address-cells = <1>;
> @@ -293,6 +294,56 @@
> status = "disabled";
> };
>
> + pcie_ep: pcie-ep@1c00000 {
> + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
> + reg = <0x01c00000 0x3000>,
> + <0x40000000 0xf1d>,
> + <0x40000f20 0xa8>,
> + <0x40001000 0x1000>,
> + <0x40200000 0x100000>,
> + <0x01c03000 0x3000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "addr_space",
> + "mmio";
> +
> + qcom,perst-regs = <&tcsr 0xb258 0xb270>;
> +
> + clocks = <&gcc GCC_PCIE_AUX_CLK>,
> + <&gcc GCC_PCIE_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_PCIE_SLEEP_CLK>,
> + <&gcc GCC_PCIE_0_CLKREF_EN>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "sleep",
> + "ref";
> +
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "global", "doorbell";
> +
> + resets = <&gcc GCC_PCIE_BCR>;
> + reset-names = "core";
> +
> + power-domains = <&gcc PCIE_GDSC>;
> +
> + phys = <&pcie_phy>;
> + phy-names = "pcie-phy";
> +
> + max-link-speed = <3>;
> + num-lanes = <2>;
> +
> + status = "disabled";
> + };
> +
> pcie_phy: phy@1c06000 {
> compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
> reg = <0x01c06000 0x2000>;
> @@ -330,6 +381,11 @@
> #hwlock-cells = <1>;
> };
>
> + tcsr: syscon@1fcb000 {
> + compatible = "qcom,sdx65-tcsr", "syscon";
> + reg = <0x01fc0000 0x1000>;
> + };
> +
> remoteproc_mpss: remoteproc@4080000 {
> compatible = "qcom,sdx55-mpss-pas";
> reg = <0x04080000 0x4040>;
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
On Fri, Mar 17, 2023 at 12:23:55PM +0530, Rohit Agarwal wrote:
> Add PCIe EP compatible string for SDX65 SoC.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> Acked-by: Krzysztof Kozlowski <[email protected]>
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> index 89cfdee..096540b 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> @@ -13,6 +13,7 @@ properties:
> compatible:
> enum:
> - qcom,sdx55-pcie-ep
> + - qcom,sdx65-pcie-ep
> - qcom,sm8450-pcie-ep
>
> reg:
> @@ -109,6 +110,7 @@ allOf:
> contains:
> enum:
> - qcom,sdx55-pcie-ep
> + - qcom,sdx65-pcie-ep
> then:
> properties:
> clocks:
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
On 17.03.2023 07:53, Rohit Agarwal wrote:
> Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
> used by the PCIe EP controller.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm/boot/dts/qcom-sdx65.dtsi | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 192f9f9..084daf8 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -293,6 +293,37 @@
> status = "disabled";
> };
>
> + pcie_phy: phy@1c06000 {
> + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
> + reg = <0x01c06000 0x2000>;
> +
> + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
> + <&gcc GCC_PCIE_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_CLKREF_EN>,
> + <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
> + <&gcc GCC_PCIE_PIPE_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref",
> + "rchng",
> + "pipe";
> +
> + resets = <&gcc GCC_PCIE_PHY_BCR>;
> + reset-names = "phy";
> +
> + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc PCIE_GDSC>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x01f40000 0x40000>;
On 17.03.2023 07:53, Rohit Agarwal wrote:
> Add support for PCIe Endpoint controller on the
> Qualcomm SDX65 platform.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 56 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 084daf8..a7d8ad9 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -11,6 +11,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/gpio/gpio.h>
This should be sorted alphabetically
Other than that:
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
>
> / {
> #address-cells = <1>;
> @@ -293,6 +294,56 @@
> status = "disabled";
> };
>
> + pcie_ep: pcie-ep@1c00000 {
> + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
> + reg = <0x01c00000 0x3000>,
> + <0x40000000 0xf1d>,
> + <0x40000f20 0xa8>,
> + <0x40001000 0x1000>,
> + <0x40200000 0x100000>,
> + <0x01c03000 0x3000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "addr_space",
> + "mmio";
> +
> + qcom,perst-regs = <&tcsr 0xb258 0xb270>;
> +
> + clocks = <&gcc GCC_PCIE_AUX_CLK>,
> + <&gcc GCC_PCIE_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_PCIE_SLEEP_CLK>,
> + <&gcc GCC_PCIE_0_CLKREF_EN>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "sleep",
> + "ref";
> +
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "global", "doorbell";
> +
> + resets = <&gcc GCC_PCIE_BCR>;
> + reset-names = "core";
> +
> + power-domains = <&gcc PCIE_GDSC>;
> +
> + phys = <&pcie_phy>;
> + phy-names = "pcie-phy";
> +
> + max-link-speed = <3>;
> + num-lanes = <2>;
> +
> + status = "disabled";
> + };
> +
> pcie_phy: phy@1c06000 {
> compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
> reg = <0x01c06000 0x2000>;
> @@ -330,6 +381,11 @@
> #hwlock-cells = <1>;
> };
>
> + tcsr: syscon@1fcb000 {
> + compatible = "qcom,sdx65-tcsr", "syscon";
> + reg = <0x01fc0000 0x1000>;
> + };
> +
> remoteproc_mpss: remoteproc@4080000 {
> compatible = "qcom,sdx55-mpss-pas";
> reg = <0x04080000 0x4040>;