PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
are found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane
Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
This series adds support for enabling the same
DTS patch is based on the below series
https://lore.kernel.org/linux-arm-msm/[email protected]/
Changes in V2:
- Reordered the patches and splitted the board DT changes
into a separate patch as suggested
- Detailed change logs are added to the respective patches
Devi Priya (9):
dt-bindings: clock: Add PCIe pipe clock definitions
clk: qcom: gcc-ipq9574: Add PCIe pipe clocks
dt-bindings: phy: qcom,qmp-pcie: Add ipq9574 bindings
phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEs
dt-bindings: PCI: qcom: Add IPQ9574
dt-bindings: pinctrl: qcom: Add few missing functions
arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes
arm64: dts: qcom: ipq9574: Enable PCIe PHYs and controllers
PCI: qcom: Add support for IPQ9574
.../devicetree/bindings/pci/qcom,pcie.yaml | 48 +++
.../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 103 ++++-
.../bindings/pinctrl/qcom,ipq9574-tlmm.yaml | 6 +-
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 62 +++
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 375 +++++++++++++++++-
drivers/clk/qcom/gcc-ipq9574.c | 76 ++++
drivers/pci/controller/dwc/pcie-qcom.c | 62 ++-
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 332 ++++++++++++++++
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 26 +-
.../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 3 +
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 +
11 files changed, 1046 insertions(+), 51 deletions(-)
base-commit: 31bd35b66249699343d2416658f57e97314a433a
--
2.17.1
Added the missing functions cri_trng2, gpio and removed the
duplicate entry qdss_tracedata_b
Fixes: 5b63ccb69ee8 ("dt-bindings: pinctrl: qcom: Add support for IPQ9574")
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V2:
- Added the missing functions to pinctrl binding which was
spotted with dtbs_check upon adding the pinctrl definitions for
pcie perst gpio
.../devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
index f32239d08c32..673713debac2 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
@@ -74,15 +74,15 @@ $defs:
blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
- cri_trng1, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
- gcc_plltest, gcc_tlmm, mac, mdc, mdio, pcie0_clk, pcie0_wake,
+ cri_trng1, cri_trng2, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
+ gcc_plltest, gcc_tlmm, gpio, mac, mdc, mdio, pcie0_clk, pcie0_wake,
pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake, pcie3_clk, pcie3_wake,
prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, pta, pwm,
qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
- qdss_tracedata_b, qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
+ qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
wci20, wci21, wsa_swrm ]
--
2.34.1
Add the PCIe pipe clocks needed for enabling PCIe in IPQ9574
Co-developed-by: Anusha Rao <[email protected]>
Signed-off-by: Anusha Rao <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V2:
- Corrected the indentation for members of struct gcc_pcie1_pipe_clk
drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index ca40cb810a95..a4cf750043af 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -1522,6 +1522,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie0_pipe_clk = {
+ .halt_reg = 0x28044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x28044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
.reg = 0x29064,
.clkr = {
@@ -1536,6 +1554,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie1_pipe_clk = {
+ .halt_reg = 0x29044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x29044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
.reg = 0x2a064,
.clkr = {
@@ -1550,6 +1586,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie2_pipe_clk = {
+ .halt_reg = 0x2a044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2a044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie2_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie2_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
.reg = 0x2b064,
.clkr = {
@@ -1564,6 +1618,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie3_pipe_clk = {
+ .halt_reg = 0x2b044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2b044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie3_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie3_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
@@ -3878,9 +3950,13 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
+ [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
+ [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
--
2.17.1
Enable the PCIe controller and PHY nodes corresponding to
RDP 433
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V2:
- Moved the Board DT changes to a new patch as suggested
- Added pinctrl definitions for PCIe perst GPIOs
- Dropped the suffix denoting the lane config from pcie labels
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 62 +++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
index 7be578017bf7..3ae38cf327ea 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -8,6 +8,7 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "ipq9574.dtsi"
/ {
@@ -43,6 +44,42 @@
};
};
+&pcie1_phy {
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_1_pin>;
+
+ perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ status = "okay";
+};
+
+&pcie2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_2_pin>;
+
+ perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie3_phy {
+ status = "okay";
+};
+
+&pcie3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_3_pin>;
+
+ perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
@@ -60,6 +97,31 @@
};
&tlmm {
+
+ pcie_1_pin: pcie-1-state {
+ pins = "gpio26";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ output-low;
+ };
+
+ pcie_2_pin: pcie-2-state {
+ pins = "gpio29";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ output-low;
+ };
+
+ pcie_3_pin: pcie-3-state {
+ pins = "gpio32";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
+
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
--
2.17.1
Quoting Devi Priya (2023-04-04 09:48:21)
> Add the PCIe pipe clocks needed for enabling PCIe in IPQ9574
>
> Co-developed-by: Anusha Rao <[email protected]>
> Signed-off-by: Anusha Rao <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
Acked-by: Stephen Boyd <[email protected]>
On 04/04/2023 18:48, Devi Priya wrote:
> Added the missing functions cri_trng2, gpio and removed the
> duplicate entry qdss_tracedata_b
>
> Fixes: 5b63ccb69ee8 ("dt-bindings: pinctrl: qcom: Add support for IPQ9574")
Fixes are either separate patches or sent as first in the series. This
is not really related to PCI, so it should be separate patchset.
> Signed-off-by: Devi Priya <[email protected]>
> ---
> Changes in V2:
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 4/5/2023 12:28 PM, Krzysztof Kozlowski wrote:
> On 04/04/2023 18:48, Devi Priya wrote:
>> Added the missing functions cri_trng2, gpio and removed the
>> duplicate entry qdss_tracedata_b
>>
>> Fixes: 5b63ccb69ee8 ("dt-bindings: pinctrl: qcom: Add support for IPQ9574")
>
> Fixes are either separate patches or sent as first in the series. This
> is not really related to PCI, so it should be separate patchset.
Got it, will post it as a separate patch
>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> Changes in V2:
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
Thanks!
>
> Best regards,
> Krzysztof
>
Best Regards,
Devi Priya