--- drivers/ide/sl82c105.c 16 Aug 2001 13:50:23 -0000 1.3
+++ drivers/ide/sl82c105.c 17 Dec 2001 19:14:28 -0000
@@ -156,6 +156,29 @@
}
/*
+ * Reset the controller.
+ * If we are using INTC under a w83c553 we need to use a magic test
+ * bit to do this. Return zero if successful (or applicable).
+ *
+ */
+static int sl82c105_hard_reset(ide_drive_t *drive)
+{
+ ide_hwif_t *hwif = HWIF(drive);
+ struct pci_dev *dev = hwif->pci_dev;
+ unsigned int reg;
+
+ pci_read_config_dword(dev, 0x40, ®); /* LEGIRQ register */
+ if (reg & (1<<11)) { /* Using INTC? */
+ printk("sl82c105: resetting device\n");
+ pci_read_config_dword(dev, 0x7e, ®);
+ pci_write_config_word(dev, 0x7e, reg | (1<<2));
+ pci_write_config_word(dev, 0x7e, reg & (~(1<<2)));
+ return 0;
+ }
+ return 1;
+}
+
+/*
* Our own dmaproc, only to intercept ide_dma_check
*/
static int sl82c105_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
@@ -171,6 +194,11 @@
case ide_dma_off:
config_for_pio(drive, 4, 0);
break;
+ case ide_dma_lostirq:
+ case ide_dma_timeout:
+ if (sl82c105_hard_reset(drive) == 0)
+ return 0;
+ break;
default:
break;
}
On Mon, Dec 17, 2001 at 09:31:08PM -0600, Todd Inglett wrote:
> I have found that the IDE controller on a w83c553f (a sl82c105 function)
> can get into a hung state if the interrupt line is wired to INTC and a
> timeout occurs. The following patch implements a hard reset for the
> controller as documented in a Windbond engineering notice.
Thanks - I'll give it a whirl here.
Could you also get an lspci -v dump of the ISA bridge and the IDE function
please?
> This patch needs some testing and there appears to be no maintainer for
> the sl83c105 IDE driver :(.
I'm about the closest person to a maintainer for that; these chips are
used on every NetWinder...
> The conditions to repeat the problem are
> that the controller must be wired for PCI INTC, DMA must be in use, and
> a timeout error must occur (try mounting a music CD).
Does the Engineering notice give PCI INTC as a pre-condition?
> The patch should apply to 2.5.13 - 2.5.16 (at least).
I think you mean 2.4.13 - 2.4.16 8)
--
Russell King ([email protected]) The developer of ARM Linux
http://www.arm.linux.org.uk/personal/aboutme.html
Russell King wrote:
> Could you also get an lspci -v dump of the ISA bridge and the IDE function
> please?
Bus 0, device 11, function 0:
ISA bridge: Symphony Labs W83C553 (rev 16).
Bus 0, device 11, function 1:
IDE interface: Symphony Labs SL82c105 (rev 5).
IRQ 31.
Master Capable. Latency=72. Min Gnt=2.Max Lat=40.
I/O at 0xe000000001100800 [0xe000000001100807].
I/O at 0xe000000001100000 [0xe000000001100003].
I/O at 0xe000000001100c00 [0xe000000001100c07].
I/O at 0xe000000001100400 [0xe000000001100403].
I/O at 0xe000000001101000 [0xe00000000110100f].
I/O at 0xe000000001101400 [0xe00000000110140f].
> Does the Engineering notice give PCI INTC as a pre-condition?
Yes. When bit 11 (LEGIRQ) of the IDE control/status register is set IDE
IRQs are sent to INTC and/or INTD. This is a pre-condition. The
problem is that the controller gets confused on an unfinished DMA and
erroneously waits for ack on IRQA/B.
>>The patch should apply to 2.5.13 - 2.5.16 (at least).
>>
>
> I think you mean 2.4.13 - 2.4.16 8)
No kidding. A Monday I guess :(.
-todd