Just noticed this in "include/asm-i386/processor.h" :
--- snip ---
/* Prefetch instructions for Pentium III and AMD Athlon */
#ifdef CONFIG_MPENTIUMIII
#define ARCH_HAS_PREFETCH
extern inline void prefetch(const void *x)
{
__asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
}
#elif CONFIG_X86_USE_3DNOW
--- end snip ---
The P4 has SSE and prefetch or no ?
Margit
On Thu, Nov 28, 2002 at 03:17:53PM +0100, Margit Schubert-While wrote:
> Just noticed this in "include/asm-i386/processor.h" :
>
> --- snip ---
> /* Prefetch instructions for Pentium III and AMD Athlon */
> #ifdef CONFIG_MPENTIUMIII
> #define ARCH_HAS_PREFETCH
> extern inline void prefetch(const void *x)
> {
> __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
> }
> #elif CONFIG_X86_USE_3DNOW
> --- end snip ---
>
> The P4 has SSE and prefetch or no ?
It does. You seem to have found a bug.
Dave
--
| Dave Jones. http://www.codemonkey.org.uk
| SuSE Labs
On Thu, 28 Nov 2002, Dave Jones wrote:
> On Thu, Nov 28, 2002 at 03:17:53PM +0100, Margit Schubert-While wrote:
> > Just noticed this in "include/asm-i386/processor.h" :
> >
> > --- snip ---
> > /* Prefetch instructions for Pentium III and AMD Athlon */
> > #ifdef CONFIG_MPENTIUMIII
> > #define ARCH_HAS_PREFETCH
> > extern inline void prefetch(const void *x)
> > {
> > __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
> > }
> > #elif CONFIG_X86_USE_3DNOW
> > --- end snip ---
> >
> > The P4 has SSE and prefetch or no ?
>
> It does. You seem to have found a bug.
A bug? An inefficiency, obviously, but it should be functionally correct,
no? Or is there a problem I've missed other than performance?
--
bill davidsen <[email protected]>
CTO, TMR Associates, Inc
Doing interesting things with little computers since 1979.
On 2002.11.28 Dave Jones wrote:
>On Thu, Nov 28, 2002 at 03:17:53PM +0100, Margit Schubert-While wrote:
> > Just noticed this in "include/asm-i386/processor.h" :
> >
> > --- snip ---
> > /* Prefetch instructions for Pentium III and AMD Athlon */
> > #ifdef CONFIG_MPENTIUMIII
> > #define ARCH_HAS_PREFETCH
> > extern inline void prefetch(const void *x)
> > {
> > __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
> > }
> > #elif CONFIG_X86_USE_3DNOW
> > --- end snip ---
> >
> > The P4 has SSE and prefetch or no ?
>
>It does. You seem to have found a bug.
>
Two questions:
- I am trying to use gcc's __builtin_prefetch, and it is able to
spit different prefetch instructions depending on 'temporal
locality' of the data:
prefetchnta, prefetcht2, prefetcht1, prefetcht0
temp-loc: 0 1 2 3
0 means you can just discard after r or w, and 3 means you
are really interested in data lasting in cache.
Do not know if the use of prefetch in kernel is extensive,
but perhaps this is something to investigate...
- PII also supports the prefetches. Is it worth to add it ?
TIA
--
J.A. Magallon <[email protected]> \ Software is like sex:
werewolf.able.es \ It's better when it's free
Mandrake Linux release 9.1 (Cooker) for i586
Linux 2.4.20-rc4-jam0 (gcc 3.2 (Mandrake Linux 9.1 3.2-4mdk))
On Thu, 2002-11-28 at 11:12, Bill Davidsen wrote:
> On Thu, 28 Nov 2002, Dave Jones wrote:
>
> > On Thu, Nov 28, 2002 at 03:17:53PM +0100, Margit Schubert-While wrote:
> > > Just noticed this in "include/asm-i386/processor.h" :
> > >
> > > --- snip ---
> > > /* Prefetch instructions for Pentium III and AMD Athlon */
> > > #ifdef CONFIG_MPENTIUMIII
> > > #define ARCH_HAS_PREFETCH
> > > extern inline void prefetch(const void *x)
> > > {
> > > __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
> > > }
> > > #elif CONFIG_X86_USE_3DNOW
> > > --- end snip ---
> > >
> > > The P4 has SSE and prefetch or no ?
> >
> > It does. You seem to have found a bug.
>
> A bug? An inefficiency, obviously, but it should be functionally correct,
> no? Or is there a problem I've missed other than performance?
IMHO, when building systems, any deficiency I find, is logged as a bug.
I'd imagine, anything perceived as a problem, should be treated this
way. Imho, performance, or lack of, is a bug, if a potential fix is
available.
--The GrandMaster
On Fri, Nov 29, 2002 at 01:08:59AM +0100, J.A. Magallon wrote:
> - PII also supports the prefetches. Is it worth to add it ?
I think you are mistaken. The prefetch instructions came to
Intel CPUs with SSE. There are no (afair) no SSE Pentium II's.
Dave
--
| Dave Jones. http://www.codemonkey.org.uk
| SuSE Labs