Commits
- c52f61fcbdb2aa84f0e4d831ef07f375e6b99b2c
(x86: allow TSC clock source on AMD Fam10h and some cleanup)
- e30436f05d456efaff77611e4494f607b14c2782
(x86: move X86_FEATURE_CONSTANT_TSC into early cpu feature detection)
are supposed to fix the detection of contant TSC for AMD CPUs.
Unfortunately on x86_64 it does still not work with current x86/mm.
For a Phenom I still get:
...
TSC calibrated against PM_TIMER
Marking TSC unstable due to TSCs unsynchronized
time.c: Detected 2288.366 MHz processor.
...
We have to set c->x86_power in early_identify_cpu to properly detect
the CONSTANT_TSC bit in early_init_amd.
Attached patch fixes this issue. Following the relevant boot
messages when the fix is used:
...
TSC calibrated against PM_TIMER
time.c: Detected 2288.279 MHz processor.
...
Initializing CPU#1
...
checking TSC synchronization [CPU#0 -> CPU#1]: passed.
...
Initializing CPU#2
...
checking TSC synchronization [CPU#0 -> CPU#2]: passed.
...
Booting processor 3/4 APIC 0x3
...
checking TSC synchronization [CPU#0 -> CPU#3]: passed.
Brought up 4 CPUs
...
Patch is against x86/mm (v2.6.24-rc8-672-ga9f7faa).
Please apply.
Regards,
Andreas
---
x86_64: fix detection of CONSTANT_TSC bit for AMD CPUs
Set c->x86_power in early_identify_cpu. This ensures that
X86_FEATURE_CONSTANT_TSC can properly be set in early_init_amd.
Signed-off-by: Andreas Herrmann <[email protected]>
---
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index c8dcdd2..aeaa17d 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -1021,6 +1021,10 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
c->x86_capability[2] = cpuid_edx(0x80860001);
}
+ c->extended_cpuid_level = cpuid_eax(0x80000000);
+ if (c->extended_cpuid_level >= 0x80000007)
+ c->x86_power = cpuid_edx(0x80000007);
+
switch (c->x86_vendor) {
case X86_VENDOR_AMD:
early_init_amd(c);
@@ -1091,11 +1095,6 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
numa_add_cpu(smp_processor_id());
#endif
- c->extended_cpuid_level = cpuid_eax(0x80000000);
-
- if (c->extended_cpuid_level >= 0x80000007)
- c->x86_power = cpuid_edx(0x80000007);
-
switch (c->x86_vendor) {
case X86_VENDOR_AMD:
early_init_amd(c);
* Andreas Herrmann <[email protected]> wrote:
> Commits
> - c52f61fcbdb2aa84f0e4d831ef07f375e6b99b2c
> (x86: allow TSC clock source on AMD Fam10h and some cleanup)
> - e30436f05d456efaff77611e4494f607b14c2782
> (x86: move X86_FEATURE_CONSTANT_TSC into early cpu feature detection)
>
> are supposed to fix the detection of contant TSC for AMD CPUs.
> Unfortunately on x86_64 it does still not work with current x86/mm.
> For a Phenom I still get:
>
> ...
> TSC calibrated against PM_TIMER
> Marking TSC unstable due to TSCs unsynchronized
> time.c: Detected 2288.366 MHz processor.
> ...
>
> We have to set c->x86_power in early_identify_cpu to properly detect
> the CONSTANT_TSC bit in early_init_amd.
>
> Attached patch fixes this issue. Following the relevant boot
> messages when the fix is used:
>
> ...
> TSC calibrated against PM_TIMER
> time.c: Detected 2288.279 MHz processor.
> ...
> Initializing CPU#1
> ...
> checking TSC synchronization [CPU#0 -> CPU#1]: passed.
> ...
> Initializing CPU#2
> ...
> checking TSC synchronization [CPU#0 -> CPU#2]: passed.
> ...
> Booting processor 3/4 APIC 0x3
> ...
> checking TSC synchronization [CPU#0 -> CPU#3]: passed.
> Brought up 4 CPUs
> ...
>
> Patch is against x86/mm (v2.6.24-rc8-672-ga9f7faa).
> Please apply.
thanks, applied.
Ingo
> We have to set c->x86_power in early_identify_cpu to properly detect
> the CONSTANT_TSC bit in early_init_amd.
Hmm this definitely worked here when I wrote the patches. Must have been a merge
mistake later. I remember someone changed the early CPU init around severly
at some point and I might have not correctly forward merged my changes
with this. In general it is pretty tough to keep up with git-x86 currently.
Sorry about that.
-Andi