Impact: complete cache information for AMD CPUs
See "CPUID Specification" (AMD Publication #: 25481, Rev. 2.28, April 2008)
Signed-off-by: Andreas Herrmann <[email protected]>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 16 ++++++++++++----
1 files changed, 12 insertions(+), 4 deletions(-)
Please apply.
Thanks,
Andreas
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index c471eb1..8f5f084 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -207,10 +207,17 @@ union l3_cache {
};
static const unsigned short __cpuinitconst assocs[] = {
- [1] = 1, [2] = 2, [4] = 4, [6] = 8,
- [8] = 16, [0xa] = 32, [0xb] = 48,
+ [1] = 1,
+ [2] = 2,
+ [4] = 4,
+ [6] = 8,
+ [8] = 16,
+ [0xa] = 32,
+ [0xb] = 48,
[0xc] = 64,
- [0xf] = 0xffff // ??
+ [0xd] = 96,
+ [0xe] = 128,
+ [0xf] = 0xffff // fully associative - no way to show this currently
};
static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
@@ -271,7 +278,8 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
eax->split.type = types[leaf];
eax->split.level = levels[leaf];
if (leaf == 3)
- eax->split.num_threads_sharing = current_cpu_data.x86_max_cores - 1;
+ eax->split.num_threads_sharing =
+ current_cpu_data.x86_max_cores - 1;
else
eax->split.num_threads_sharing = 0;
eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
--
1.6.2
* Andreas Herrmann <[email protected]> wrote:
> Impact: complete cache information for AMD CPUs
>
> See "CPUID Specification" (AMD Publication #: 25481, Rev. 2.28, April 2008)
>
> Signed-off-by: Andreas Herrmann <[email protected]>
> ---
> arch/x86/kernel/cpu/intel_cacheinfo.c | 16 ++++++++++++----
> 1 files changed, 12 insertions(+), 4 deletions(-)
>
> Please apply.
Hm, the x86/cpu topic is marked broken and blocked by another AMD
patch from Mark Langsdorf:
45ca863: x86, cpu: conform L3 Cache Index Disable to Linux standards
We cannot queue up new patches there before this one is fixed. I've
attached below my last bugreport about it.
Ingo
----- Forwarded message from Ingo Molnar <[email protected]> -----
Date: Thu, 19 Mar 2009 09:18:37 +0100
From: Ingo Molnar <[email protected]>
To: Mark Langsdorf <[email protected]>
Subject: Re: [PATCH][retry 5] Conform L3 Cache Index Disable to Linux
Standards
Cc: Andrew Morton <[email protected]>, [email protected],
[email protected], [email protected]
* Mark Langsdorf <[email protected]> wrote:
> Add ABI Documentation entry and fix some /sys directory formating
> issues with the L3 Cache Index Disable feature for future AMD
> processors. Add a check to disable it for family 0x10 models
> that do not support it properly. Correct the disable algorithm
> to reflect erratum 388.
>
> Signed-off-by: Mark Langsdorf <[email protected]>
i'm still getting this build failure:
arch/x86/mm/built-in.o:(.bss+0x3640): multiple definition of `k8_northbridges'
i've reported this build failure before. I've excluded this commit
from tip:master for now.
Ingo
----- End forwarded message -----
On Thu, Apr 02, 2009 at 12:30:08PM +0200, Ingo Molnar wrote:
>
> * Andreas Herrmann <[email protected]> wrote:
>
> > Impact: complete cache information for AMD CPUs
> >
> > See "CPUID Specification" (AMD Publication #: 25481, Rev. 2.28, April 2008)
> >
> > Signed-off-by: Andreas Herrmann <[email protected]>
> > ---
> > arch/x86/kernel/cpu/intel_cacheinfo.c | 16 ++++++++++++----
> > 1 files changed, 12 insertions(+), 4 deletions(-)
> >
> > Please apply.
>
> Hm, the x86/cpu topic is marked broken and blocked by another AMD
> patch from Mark Langsdorf:
>
> 45ca863: x86, cpu: conform L3 Cache Index Disable to Linux standards
Oops, wasn't aware that you had applied this patch and I couldn't find
it in tip/master. Now I know why.
The code seems broken. Defining k8_northbridges in a header file is the
wrong thing to do. I'll look at it.
Andreas
--
Operating | Advanced Micro Devices GmbH
System | Karl-Hammerschmidt-Str. 34, 85609 Dornach b. M?nchen, Germany
Research | Gesch?ftsf?hrer: Jochen Polster, Thomas M. McCoy, Giuliano Meroni
Center | Sitz: Dornach, Gemeinde Aschheim, Landkreis M?nchen
(OSRC) | Registergericht M?nchen, HRB Nr. 43632
Impact: fix build error
Commit 45ca863 (x86, cpu: conform L3 Cache Index Disable to Linux standard)
introduced following build error with CONFIG_K8_NB=n
...
arch/x86/mm/built-in.o:(.bss+0x5c0): multiple definition of `k8_northbridges'
arch/x86/kernel/built-in.o:(.bss+0x18c8): first defined here
...
The patch deactivates cache_disable functionality for kernels with
CONFIG_K8_NB=n.
Signed-off-by: Andreas Herrmann <[email protected]>
---
arch/x86/include/asm/k8.h | 4 ----
arch/x86/kernel/cpu/intel_cacheinfo.c | 19 ++++++++++++++++---
2 files changed, 16 insertions(+), 7 deletions(-)
The real fix would be to enable cache index disable functionality also
for kernels with CONFIG_K8_NB=n but I don't have time to provide such
a patch today.
Ingo, please either apply this (compile tested) patch or revert Mark's
patch to avoid further blocking of tip/x86/cpu branch.
Thanks,
Andreas
diff --git a/arch/x86/include/asm/k8.h b/arch/x86/include/asm/k8.h
index 0d619c3..54c8cc5 100644
--- a/arch/x86/include/asm/k8.h
+++ b/arch/x86/include/asm/k8.h
@@ -6,11 +6,7 @@
extern struct pci_device_id k8_nb_ids[];
extern int early_is_k8_nb(u32 value);
-#ifdef CONFIG_K8_NB
extern struct pci_dev **k8_northbridges;
-#else
-struct pci_dev **k8_northbridges;
-#endif
extern int num_k8_northbridges;
extern int cache_k8_northbridges(void);
extern void k8_flush_garts(void);
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 6f4d2a3..63e4468 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -640,14 +640,23 @@ static ssize_t show_##file_name \
return sprintf (buf, "%lu\n", (unsigned long)this_leaf->object + val); \
}
+#ifndef CONFIG_K8_NB
+struct pci_dev **k8_northbridges = NULL;
+#endif
+
static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
unsigned int index)
{
int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
int node = cpu_to_node(cpu);
- struct pci_dev *dev = k8_northbridges[node];
+ struct pci_dev *dev;
unsigned int reg = 0;
+ if (!k8_northbridges)
+ return -EINVAL;
+
+ dev = k8_northbridges[node];
+
if (!this_leaf->can_disable)
return -EINVAL;
@@ -668,10 +677,15 @@ store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
{
int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
int node = cpu_to_node(cpu);
- struct pci_dev *dev = k8_northbridges[node];
+ struct pci_dev *dev;
unsigned long val = 0;
unsigned int scrubber = 0;
+ if (!k8_northbridges)
+ return -EINVAL;
+
+ dev = k8_northbridges[node];
+
if (!this_leaf->can_disable)
return -EINVAL;
@@ -786,7 +800,6 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
show_cache_disable_1, store_cache_disable_1);
-
static struct attribute * default_attrs[] = {
&type.attr,
&level.attr,
--
1.6.2
* Andreas Herrmann <[email protected]> wrote:
> Impact: fix build error
>
> Commit 45ca863 (x86, cpu: conform L3 Cache Index Disable to Linux standard)
> introduced following build error with CONFIG_K8_NB=n
> ...
> arch/x86/mm/built-in.o:(.bss+0x5c0): multiple definition of `k8_northbridges'
> arch/x86/kernel/built-in.o:(.bss+0x18c8): first defined here
> ...
>
> The patch deactivates cache_disable functionality for kernels with
> CONFIG_K8_NB=n.
>
> Signed-off-by: Andreas Herrmann <[email protected]>
> ---
> arch/x86/include/asm/k8.h | 4 ----
> arch/x86/kernel/cpu/intel_cacheinfo.c | 19 ++++++++++++++++---
> 2 files changed, 16 insertions(+), 7 deletions(-)
>
> The real fix would be to enable cache index disable functionality also
> for kernels with CONFIG_K8_NB=n but I don't have time to provide such
> a patch today.
>
> Ingo, please either apply this (compile tested) patch or revert Mark's
> patch to avoid further blocking of tip/x86/cpu branch.
>
>
> Thanks,
>
> Andreas
>
>
> diff --git a/arch/x86/include/asm/k8.h b/arch/x86/include/asm/k8.h
> index 0d619c3..54c8cc5 100644
> --- a/arch/x86/include/asm/k8.h
> +++ b/arch/x86/include/asm/k8.h
> @@ -6,11 +6,7 @@
> extern struct pci_device_id k8_nb_ids[];
>
> extern int early_is_k8_nb(u32 value);
> -#ifdef CONFIG_K8_NB
> extern struct pci_dev **k8_northbridges;
> -#else
> -struct pci_dev **k8_northbridges;
> -#endif
hm, what's wrong with the node_to_k8_dev() suggestion i made?
That would be a pretty clean interface, private to k8.c - and it
would map a 'return NULL' inline function in the !CONFIG_K8_NB case.
Ingo
See "CPUID Specification" (AMD Publication #: 25481, Rev. 2.28, April 2008)
Signed-off-by: Andreas Herrmann <[email protected]>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 16 ++++++++++++----
1 files changed, 12 insertions(+), 4 deletions(-)
This patch applies on top of the changes sent with
[PATCH 0/8] x86: cacheinfo: cache_disable fixes/cleanup
Please apply.
Thanks,
Andreas
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 47e4fb4..3329347 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -200,10 +200,17 @@ union l3_cache {
};
static const unsigned short __cpuinitconst assocs[] = {
- [1] = 1, [2] = 2, [4] = 4, [6] = 8,
- [8] = 16, [0xa] = 32, [0xb] = 48,
+ [1] = 1,
+ [2] = 2,
+ [4] = 4,
+ [6] = 8,
+ [8] = 16,
+ [0xa] = 32,
+ [0xb] = 48,
[0xc] = 64,
- [0xf] = 0xffff // ??
+ [0xd] = 96,
+ [0xe] = 128,
+ [0xf] = 0xffff // fully associative - no way to show this currently
};
static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
@@ -264,7 +271,8 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
eax->split.type = types[leaf];
eax->split.level = levels[leaf];
if (leaf == 3)
- eax->split.num_threads_sharing = current_cpu_data.x86_max_cores - 1;
+ eax->split.num_threads_sharing =
+ current_cpu_data.x86_max_cores - 1;
else
eax->split.num_threads_sharing = 0;
eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
--
1.6.2
Commit-ID: 6265ff19ca08df0d96c859ae5e4dc2d9ad07070e
Gitweb: http://git.kernel.org/tip/6265ff19ca08df0d96c859ae5e4dc2d9ad07070e
Author: Andreas Herrmann <[email protected]>
AuthorDate: Thu, 9 Apr 2009 15:47:10 +0200
Committer: Ingo Molnar <[email protected]>
CommitDate: Fri, 10 Apr 2009 15:41:18 +0200
x86: cacheinfo: complete L2/L3 Cache and TLB associativity field definitions
See "CPUID Specification" (AMD Publication #: 25481, Rev. 2.28, April 2008)
Signed-off-by: Andreas Herrmann <[email protected]>
Cc: Mark Langsdorf <[email protected]>
LKML-Reference: <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 16 ++++++++++++----
1 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index d46a849..789efe2 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -200,10 +200,17 @@ union l3_cache {
};
static const unsigned short __cpuinitconst assocs[] = {
- [1] = 1, [2] = 2, [4] = 4, [6] = 8,
- [8] = 16, [0xa] = 32, [0xb] = 48,
+ [1] = 1,
+ [2] = 2,
+ [4] = 4,
+ [6] = 8,
+ [8] = 16,
+ [0xa] = 32,
+ [0xb] = 48,
[0xc] = 64,
- [0xf] = 0xffff // ??
+ [0xd] = 96,
+ [0xe] = 128,
+ [0xf] = 0xffff /* fully associative - no way to show this currently */
};
static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
@@ -264,7 +271,8 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
eax->split.type = types[leaf];
eax->split.level = levels[leaf];
if (leaf == 3)
- eax->split.num_threads_sharing = current_cpu_data.x86_max_cores - 1;
+ eax->split.num_threads_sharing =
+ current_cpu_data.x86_max_cores - 1;
else
eax->split.num_threads_sharing = 0;
eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;