Hi,
I masked all the interrupts except keyboard interrupt before the instruction “hlt”, So the CPU ran nothing until I click the keyboard button. And I used “rdtscll” and “do_gettimeofday” to get the halt time. But the result of “do_gettimeofday” was longer than the one of “rdtscll” about 3s per minute. I don’t know why.
I timed some math job using the same way in contrary to the “hlt” instruction. The TSC was not correct either. In 3 minutes, the result of “do_gettimeofday” was longer than the one of “rdtscll” about 5s.
The processor is Intel Pentium M processor 750. From the software developer’s manual of Intel, the processor clock of Pentium M processors is impacted by Intel SpeedStep technology, while some other processors is not. Maybe this is another feature Pentium M processors own.
Pentium M processors support 5 C-states. I am sure the TSC doesn’t stop in C0 and C1 states. But I am not sure about other states. Maybe other states will stop the clock, and “hlt” instruction will make the CPU into deeper state.
These are my guess. I wanna the truth. Thank you.
Mao Yilu
Mao Yilu wrote:
> Hi,
>
> I masked all the interrupts except keyboard interrupt before the instruction “hlt”, So the CPU ran nothing until I click the keyboard button. And I used “rdtscll” and “do_gettimeofday” to get the halt time. But the result of “do_gettimeofday” was longer than the one of “rdtscll” about 3s per minute. I don’t know why.
> I timed some math job using the same way in contrary to the “hlt” instruction. The TSC was not correct either. In 3 minutes, the result of “do_gettimeofday” was longer than the one of “rdtscll” about 5s.
> The processor is Intel Pentium M processor 750. From the software developer’s manual of Intel, the processor clock of Pentium M processors is impacted by Intel SpeedStep technology, while some other processors is not. Maybe this is another feature Pentium M processors own.
> Pentium M processors support 5 C-states. I am sure the TSC doesn’t stop in C0 and C1 states. But I am not sure about other states. Maybe other states will stop the clock, and “hlt” instruction will make the CPU into deeper state.
> These are my guess. I wanna the truth. Thank you.
>
> Mao Yilu
>
On many processors the TSC will stop in various C-states, and also the
TSC frequency changes when CPU frequency changes. This is why using
rdtsc in userspace is not reliable, since the code can't know whether or
not TSC can be used on that CPU reliably or how to scale the results.
Thank you for your reply.
But I still don't know why the TSC is not correct in the C1 state (hlt instruction). Is there anything more to influence the TSC? What happened when the CPU is not running under hlt instruction?
Thank you.
Mao Yilu
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Robert Hancock
Sent: Thursday, April 30, 2009 7:50 AM
To: Mao Yilu
Cc: [email protected]
Subject: Re: TSC unstable on Intel Pentium M processor 750
Mao Yilu wrote:
> Hi,
>
> I masked all the interrupts except keyboard interrupt before the instruction “hlt”, So the CPU ran nothing until I click the keyboard button. And I used “rdtscll” and “do_gettimeofday” to get the halt time. But the result of “do_gettimeofday” was longer than the one of “rdtscll” about 3s per minute. I don’t know why.
> I timed some math job using the same way in contrary to the “hlt” instruction. The TSC was not correct either. In 3 minutes, the result of “do_gettimeofday” was longer than the one of “rdtscll” about 5s.
> The processor is Intel Pentium M processor 750. From the software developer’s manual of Intel, the processor clock of Pentium M processors is impacted by Intel SpeedStep technology, while some other processors is not. Maybe this is another feature Pentium M processors own.
> Pentium M processors support 5 C-states. I am sure the TSC doesn’t stop in C0 and C1 states. But I am not sure about other states. Maybe other states will stop the clock, and “hlt” instruction will make the CPU into deeper state.
> These are my guess. I wanna the truth. Thank you.
>
> Mao Yilu
>
On many processors the TSC will stop in various C-states, and also the
TSC frequency changes when CPU frequency changes. This is why using
rdtsc in userspace is not reliable, since the code can't know whether or
not TSC can be used on that CPU reliably or how to scale the results.
On Thu, 30 Apr 2009, Mao Yilu wrote:
> But I still don't know why the TSC is not correct in the C1 state (hlt
> instruction). Is there anything more to influence the TSC? What happened
> when the CPU is not running under hlt instruction?
SMIs? Laptops love that crap...
--
"One disk to rule them all, One disk to find them. One disk to bring
them all and in the darkness grind them. In the Land of Redmond
where the shadows lie." -- The Silicon Valley Tarot
Henrique Holschuh
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]] On Behalf Of Henrique de Moraes
> Holschuh
> Sent: Thursday, April 30, 2009 11:12 AM
> To: Mao Yilu
> Cc: 'Robert Hancock'; [email protected]
> Subject: Re: TSC unstable on Intel Pentium M processor 750
>
> On Thu, 30 Apr 2009, Mao Yilu wrote:
> > But I still don't know why the TSC is not correct in the C1 state (hlt
> > instruction). Is there anything more to influence the TSC? What happened
> > when the CPU is not running under hlt instruction?
>
> SMIs? Laptops love that crap...
What is SMIs?
On Thu, 30 Apr 2009, Mao Yilu wrote:
> > On Thu, 30 Apr 2009, Mao Yilu wrote:
> > > But I still don't know why the TSC is not correct in the C1 state (hlt
> > > instruction). Is there anything more to influence the TSC? What happened
> > > when the CPU is not running under hlt instruction?
> >
> > SMIs? Laptops love that crap...
>
> What is SMIs?
http://en.wikipedia.org/wiki/System_Management_Mode
--
"One disk to rule them all, One disk to find them. One disk to bring
them all and in the darkness grind them. In the Land of Redmond
where the shadows lie." -- The Silicon Valley Tarot
Henrique Holschuh
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On Thu, 30 Apr 2009 15:40:02 +0800
"Mao Yilu" <[email protected]> wrote:
> > -----Original Message-----
> > From: [email protected]
> > [mailto:[email protected]] On Behalf Of Henrique de Moraes
> > Holschuh
> > Sent: Thursday, April 30, 2009 11:12 AM
> > To: Mao Yilu
> > Cc: 'Robert Hancock'; [email protected]
> > Subject: Re: TSC unstable on Intel Pentium M processor 750
> >
> > On Thu, 30 Apr 2009, Mao Yilu wrote:
> > > But I still don't know why the TSC is not correct in the C1 state (hlt
> > > instruction). Is there anything more to influence the TSC? What happened
> > > when the CPU is not running under hlt instruction?
> >
> > SMIs? Laptops love that crap...
>
> What is SMIs?
>
>
System Management Interrupt. Usually handled by BIOS code and
completely invisible to Linux.
Laptops and big servers (rackmount/blades) typically have tons of SMIs
going off to do thermal management, statisics and remote management.
Clark
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