ARM: Common GIC entry macro code V3
[PATCH 01/07] ARM: Introduce asm/hardware/entry-macro-gic.S
[PATCH 02/07] ARM: Use shared GIC entry macros on CNS3XXX
[PATCH 03/07] ARM: Use shared GIC entry macros on Realview
[PATCH 04/07] ARM: Use shared GIC entry macros on Tegra
[PATCH 05/07] ARM: Use shared GIC entry macros on UX500
[PATCH 06/07] ARM: Use shared GIC entry macros on Vexpress
[PATCH 07/07] ARM: Use shared GIC entry macros on OMAP
Put GIC demux code in a common place to avoid duplicated code.
These patches are almost identical to 6284/1 in the RMKs
patch tracker. The main difference is that these ones require
each platform to specify base address using the macro
get_irqnr_preable. Both Tegra and OMAP are supported in V3.
The s5pv310 subarch is excluded due to the special "addne"
instruction in the get_irqnr_and_base macro.
The msm subarch is excluded as well since it treats PPIs
differently than other platforms and needs a different
version of the get_irqnr_and_base macro.
I intend to submit these patches to the RMK patch tracker
unless I hear any objections.
Signed-off-by: Magnus Damm <[email protected]>
---
arch/arm/include/asm/hardware/entry-macro-gic.S | 68 +++++++++++++++
arch/arm/mach-cns3xxx/include/mach/entry-macro.S | 61 -------------
arch/arm/mach-omap2/include/mach/entry-macro.S | 92 +++++++--------------
arch/arm/mach-realview/include/mach/entry-macro.S | 60 -------------
arch/arm/mach-tegra/include/mach/entry-macro.S | 64 --------------
arch/arm/mach-ux500/include/mach/entry-macro.S | 67 ---------------
arch/arm/mach-vexpress/include/mach/entry-macro.S | 57 -------------
7 files changed, 104 insertions(+), 365 deletions(-)
From: Magnus Damm <[email protected]>
This patch is the identical GIC demux implementation
merge V3. Instead of implementing same code over and
over simply share it in entry-macro-gic.S. The shared
code is based on the realview implementation.
Each GIC demux instance still has to setup the base address
of the controller using the get_irqnr_preamble macro. The
rest of the GIC specific code can be shared.
Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Srinidhi Kasagar<[email protected]>
---
Changes since V2:
- broke out patches into base + per sub-arch
arch/arm/include/asm/hardware/entry-macro-gic.S | 68 +++++++++++++++++++++++
1 file changed, 68 insertions(+)
--- /dev/null
+++ work/arch/arm/include/asm/hardware/entry-macro-gic.S 2010-11-12 15:57:05.000000000 +0900
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/include/asm/hardware/entry-macro-gic.S
+ *
+ * Low-level IRQ helper macros for GIC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/hardware/gic.h>
+
+/*
+ * The interrupt numbering scheme is defined in the
+ * interrupt controller spec. To wit:
+ *
+ * Interrupts 0-15 are IPI
+ * 16-28 are reserved
+ * 29-31 are local. We allow 30 to be used for the watchdog.
+ * 32-1020 are global
+ * 1021-1022 are reserved
+ * 1023 is "spurious" (no interrupt)
+ *
+ * For now, we ignore all local interrupts so only return an interrupt if it's
+ * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
+ *
+ * A simple read from the controller will tell us the number of the highest
+ * priority enabled interrupt. We then just need to check whether it is in the
+ * valid range for an IRQ (30-1020 inclusive).
+ */
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+ ldr \irqstat, [\base, #GIC_CPU_INTACK]
+ /* bits 12-10 = src CPU, 9-0 = int # */
+
+ ldr \tmp, =1021
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #29
+ cmpcc \irqnr, \irqnr
+ cmpne \irqnr, \tmp
+ cmpcs \irqnr, \irqnr
+ .endm
+
+/* We assume that irqstat (the raw value of the IRQ acknowledge
+ * register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of interrupt on the
+ * controller, since this requires the original irqstat value which
+ * we won't easily be able to recreate later.
+ */
+
+ .macro test_for_ipi, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #16
+ strcc \irqstat, [\base, #GIC_CPU_EOI]
+ cmpcs \irqnr, \irqnr
+ .endm
+
+/* As above, this assumes that irqstat and base are preserved.. */
+
+ .macro test_for_ltirq, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ mov \tmp, #0
+ cmp \irqnr, #29
+ moveq \tmp, #1
+ streq \irqstat, [\base, #GIC_CPU_EOI]
+ cmp \tmp, #0
+ .endm
From: Magnus Damm <[email protected]>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the Realview subarchitecture.
Signed-off-by: Magnus Damm <[email protected]>
---
arch/arm/mach-realview/include/mach/entry-macro.S | 60 ---------------------
1 file changed, 1 insertion(+), 59 deletions(-)
--- 0001/arch/arm/mach-realview/include/mach/entry-macro.S
+++ work/arch/arm/mach-realview/include/mach/entry-macro.S 2010-11-12 15:59:57.000000000 +0900
@@ -8,7 +8,7 @@
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
.macro disable_fiq
.endm
@@ -21,61 +21,3 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an interrupt if it's
- * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt. We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
-
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved.. */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
From: Magnus Damm <[email protected]>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the Tegra subarchitecture.
Signed-off-by: Magnus Damm <[email protected]>
---
arch/arm/mach-tegra/include/mach/entry-macro.S | 64 ------------------------
1 file changed, 1 insertion(+), 63 deletions(-)
--- 0001/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ work/arch/arm/mach-tegra/include/mach/entry-macro.S 2010-11-12 16:01:47.000000000 +0900
@@ -17,7 +17,7 @@
#if defined(CONFIG_ARM_GIC)
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
/* Uses the GIC interrupt controller built into the cpu */
#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
@@ -32,68 +32,6 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an interrupt
- * if it's between 30 and 1020. The test_for_ipi routine below will
- * pick up on IPIs.
- *
- * A simple read from the controller will tell us the number of the
- * highest priority enabled interrupt. We then just need to check
- * whether it is in the valid range for an IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- /* bits 12-10 = src CPU, 9-0 = int # */
- ldr \irqstat, [\base, #GIC_CPU_INTACK]
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
-
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved.. */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
-
#else
/* legacy interrupt controller for AP16 */
.macro disable_fiq
From: Magnus Damm <[email protected]>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the UX500 subarchitecture.
Signed-off-by: Magnus Damm <[email protected]>
---
arch/arm/mach-ux500/include/mach/entry-macro.S | 67 ------------------------
1 file changed, 1 insertion(+), 66 deletions(-)
--- 0001/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ work/arch/arm/mach-ux500/include/mach/entry-macro.S 2010-11-12 16:02:32.000000000 +0900
@@ -11,7 +11,7 @@
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
.macro disable_fiq
.endm
@@ -22,68 +22,3 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an
- * interrupt if it's between 30 and 1020. The test_for_ipi
- * routine below will pick up on IPIs.
- *
- * A simple read from the controller will tell us the number
- * of the highest priority enabled interrupt. We then just
- * need to check whether it is in the valid range for an
- * IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- /* bits 12-10 = src CPU, 9-0 = int # */
- ldr \irqstat, [\base, #GIC_CPU_INTACK]
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
-
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ
- * acknowledge register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of
- * interrupt on the controller, since this requires the
- * original irqstat value which we won't easily be able
- * to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base
- * are preserved..
- */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
From: Magnus Damm <[email protected]>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the Versatile Express subarchitecture.
Signed-off-by: Magnus Damm <[email protected]>
---
arch/arm/mach-vexpress/include/mach/entry-macro.S | 57 ---------------------
1 file changed, 1 insertion(+), 56 deletions(-)
--- 0001/arch/arm/mach-vexpress/include/mach/entry-macro.S
+++ work/arch/arm/mach-vexpress/include/mach/entry-macro.S 2010-11-12 16:03:56.000000000 +0900
@@ -1,4 +1,4 @@
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
.macro disable_fiq
.endm
@@ -10,58 +10,3 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an interrupt if it's
- * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt. We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
- ldr \tmp, =1021
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved.. */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
-
From: Magnus Damm <[email protected]>
Common GIC entry macro for omap
Signed-off-by: Tony Lindgren <[email protected]>
Signed-off-by: Magnus Damm <[email protected]>
---
arch/arm/mach-omap2/include/mach/entry-macro.S | 92 ++++++++----------------
1 file changed, 31 insertions(+), 61 deletions(-)
--- 0001/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ work/arch/arm/mach-omap2/include/mach/entry-macro.S 2010-11-12 16:10:51.000000000 +0900
@@ -105,6 +105,35 @@ omap_irq_base: .word 0
9999:
.endm
+#ifdef CONFIG_SMP
+ /* We assume that irqstat (the raw value of the IRQ acknowledge
+ * register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of interrupt
+ * on the controller, since this requires the original irqstat
+ * value which we won't easily be able to recreate later.
+ */
+
+ .macro test_for_ipi, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #16
+ it cc
+ strcc \irqstat, [\base, #GIC_CPU_EOI]
+ it cs
+ cmpcs \irqnr, \irqnr
+ .endm
+
+ /* As above, this assumes that irqstat and base are preserved */
+
+ .macro test_for_ltirq, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ mov \tmp, #0
+ cmp \irqnr, #29
+ itt eq
+ moveq \tmp, #1
+ streq \irqstat, [\base, #GIC_CPU_EOI]
+ cmp \tmp, #0
+ .endm
+#endif /* CONFIG_SMP */
#else /* MULTI_OMAP2 */
@@ -141,74 +170,15 @@ omap_irq_base: .word 0
#ifdef CONFIG_ARCH_OMAP4
+#include <asm/hardware/entry-macro-gic.S>
.macro get_irqnr_preamble, base, tmp
ldr \base, =OMAP4_IRQ_BASE
.endm
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an
- * interrupt if it's between 30 and 1020. The test_for_ipi
- * routine below will pick up on IPIs.
- * A simple read from the controller will tell us the number
- * of the highest priority enabled interrupt.
- * We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, [\base, #GIC_CPU_INTACK]
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
- .endm
#endif
-#endif /* MULTI_OMAP2 */
-
-#ifdef CONFIG_SMP
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt
- * on the controller, since this requires the original irqstat
- * value which we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- it cc
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- it cs
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved */
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- itt eq
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
-#endif /* CONFIG_SMP */
+#endif /* MULTI_OMAP2 */
.macro irq_prio_table
.endm
> -----Original Message-----
> From: Magnus Damm [mailto:[email protected]]
> Sent: Friday, November 12, 2010 1:52 PM
> To: [email protected]
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; linux-
> [email protected]; [email protected]; [email protected];
> Shilimkar, Santosh; [email protected]; [email protected]; Magnus Damm;
> [email protected]
> Subject: [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP
>
> From: Magnus Damm <[email protected]>
>
> Common GIC entry macro for omap
>
> Signed-off-by: Tony Lindgren <[email protected]>
> Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
> ---
>
> arch/arm/mach-omap2/include/mach/entry-macro.S | 92 ++++++++-----------
> -----
> 1 file changed, 31 insertions(+), 61 deletions(-)
>
> --- 0001/arch/arm/mach-omap2/include/mach/entry-macro.S
> +++ work/arch/arm/mach-omap2/include/mach/entry-macro.S 2010-11-12
> 16:10:51.000000000 +0900
> @@ -105,6 +105,35 @@ omap_irq_base: .word 0
> 9999:
> .endm
>
> +#ifdef CONFIG_SMP
> + /* We assume that irqstat (the raw value of the IRQ
> acknowledge
> + * register) is preserved from the macro above.
> + * If there is an IPI, we immediately signal end of interrupt
> + * on the controller, since this requires the original irqstat
> + * value which we won't easily be able to recreate later.
> + */
> +
> + .macro test_for_ipi, irqnr, irqstat, base, tmp
> + bic \irqnr, \irqstat, #0x1c00
> + cmp \irqnr, #16
> + it cc
> + strcc \irqstat, [\base, #GIC_CPU_EOI]
> + it cs
> + cmpcs \irqnr, \irqnr
> + .endm
> +
> + /* As above, this assumes that irqstat and base are preserved
> */
> +
> + .macro test_for_ltirq, irqnr, irqstat, base, tmp
> + bic \irqnr, \irqstat, #0x1c00
> + mov \tmp, #0
> + cmp \irqnr, #29
> + itt eq
> + moveq \tmp, #1
> + streq \irqstat, [\base, #GIC_CPU_EOI]
> + cmp \tmp, #0
> + .endm
> +#endif /* CONFIG_SMP */
>
> #else /* MULTI_OMAP2 */
>
> @@ -141,74 +170,15 @@ omap_irq_base: .word 0
>
>
> #ifdef CONFIG_ARCH_OMAP4
> +#include <asm/hardware/entry-macro-gic.S>
>
> .macro get_irqnr_preamble, base, tmp
> ldr \base, =OMAP4_IRQ_BASE
> .endm
>
> - /*
> - * The interrupt numbering scheme is defined in the
> - * interrupt controller spec. To wit:
> - *
> - * Interrupts 0-15 are IPI
> - * 16-28 are reserved
> - * 29-31 are local. We allow 30 to be used for the watchdog.
> - * 32-1020 are global
> - * 1021-1022 are reserved
> - * 1023 is "spurious" (no interrupt)
> - *
> - * For now, we ignore all local interrupts so only return an
> - * interrupt if it's between 30 and 1020. The test_for_ipi
> - * routine below will pick up on IPIs.
> - * A simple read from the controller will tell us the number
> - * of the highest priority enabled interrupt.
> - * We then just need to check whether it is in the
> - * valid range for an IRQ (30-1020 inclusive).
> - */
> - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
> - ldr \irqstat, [\base, #GIC_CPU_INTACK]
> -
> - ldr \tmp, =1021
> -
> - bic \irqnr, \irqstat, #0x1c00
> -
> - cmp \irqnr, #29
> - cmpcc \irqnr, \irqnr
> - cmpne \irqnr, \tmp
> - cmpcs \irqnr, \irqnr
> - .endm
> #endif
> -#endif /* MULTI_OMAP2 */
> -
> -#ifdef CONFIG_SMP
> - /* We assume that irqstat (the raw value of the IRQ
> acknowledge
> - * register) is preserved from the macro above.
> - * If there is an IPI, we immediately signal end of interrupt
> - * on the controller, since this requires the original irqstat
> - * value which we won't easily be able to recreate later.
> - */
> -
> - .macro test_for_ipi, irqnr, irqstat, base, tmp
> - bic \irqnr, \irqstat, #0x1c00
> - cmp \irqnr, #16
> - it cc
> - strcc \irqstat, [\base, #GIC_CPU_EOI]
> - it cs
> - cmpcs \irqnr, \irqnr
> - .endm
> -
> - /* As above, this assumes that irqstat and base are preserved
> */
>
> - .macro test_for_ltirq, irqnr, irqstat, base, tmp
> - bic \irqnr, \irqstat, #0x1c00
> - mov \tmp, #0
> - cmp \irqnr, #29
> - itt eq
> - moveq \tmp, #1
> - streq \irqstat, [\base, #GIC_CPU_EOI]
> - cmp \tmp, #0
> - .endm
> -#endif /* CONFIG_SMP */
> +#endif /* MULTI_OMAP2 */
>
> .macro irq_prio_table
> .endm
On Friday 12 November 2010, Magnus Damm wrote:
> ARM: Common GIC entry macro code V3
>
> [PATCH 01/07] ARM: Introduce asm/hardware/entry-macro-gic.S
> [PATCH 02/07] ARM: Use shared GIC entry macros on CNS3XXX
> [PATCH 03/07] ARM: Use shared GIC entry macros on Realview
> [PATCH 04/07] ARM: Use shared GIC entry macros on Tegra
> [PATCH 05/07] ARM: Use shared GIC entry macros on UX500
> [PATCH 06/07] ARM: Use shared GIC entry macros on Vexpress
> [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP
>
> Put GIC demux code in a common place to avoid duplicated code.
>
Looks like a very nice cleanup!
Arnd
On Fri, Nov 12, 2010 at 05:21:41PM +0900, Magnus Damm wrote:
> From: Magnus Damm <[email protected]>
>
> Use the GIC demux code in asm/hardware/entry-macro-gic.S
> on the Tegra subarchitecture.
>
> Signed-off-by: Magnus Damm <[email protected]>
Acked-by: Olof Johansson <[email protected]>
-Olof
* Shilimkar, Santosh <[email protected]> [101112 00:16]:
> > -----Original Message-----
> > From: Magnus Damm [mailto:[email protected]]
> > Sent: Friday, November 12, 2010 1:52 PM
> > To: [email protected]
> > Cc: [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]; linux-
> > [email protected]; [email protected]; [email protected];
> > Shilimkar, Santosh; [email protected]; [email protected]; Magnus Damm;
> > [email protected]
> > Subject: [PATCH 07/07] ARM: Use shared GIC entry macros on OMAP
> >
> > From: Magnus Damm <[email protected]>
> >
> > Common GIC entry macro for omap
> >
> > Signed-off-by: Tony Lindgren <[email protected]>
> > Signed-off-by: Magnus Damm <[email protected]>
> Acked-by: Santosh Shilimkar <[email protected]>
Looks like the From: field got trashed on this one assuming you're
using the patch I posted earlier :)
Tony