From: David Daney <[email protected]>
Changes from v1: Fix breakage in non-OCTEON builds of 8250_dw.c
1) Fix OCTEON's UART clock rate.
2) Make minor patches to 8250_dw so it can be used by OCTEON
3) Rip out the OCTEON serial code.
4) Update defconfig so we default to having a usable serial port.
Since the patches are all interdependent, we might want to merge them
via a single tree (perhaps Ralf's MIPS tree as OKed by Greg K-H).
David Daney (4):
MIPS: OCTEON: Set proper UART clock in internal device trees.
tty/8250_dw: Add support for OCTEON UARTS.
MIPS: OCTEON: Remove custom serial setup code.
MIPS: Update cavium_octeon_defconfig
arch/mips/cavium-octeon/Makefile | 2 +-
arch/mips/cavium-octeon/octeon-platform.c | 9 ++-
arch/mips/cavium-octeon/serial.c | 109 ------------------------------
arch/mips/configs/cavium_octeon_defconfig | 4 +-
drivers/tty/serial/8250/8250_dw.c | 108 ++++++++++++++++++-----------
5 files changed, 79 insertions(+), 153 deletions(-)
delete mode 100644 arch/mips/cavium-octeon/serial.c
--
1.7.11.7
From: David Daney <[email protected]>
Following patch to use generic 8250 drivers will need proper clock
information. So when using the internal device tree, populate the
"clock-frequency" property with the correct value.
Signed-off-by: David Daney <[email protected]>
---
arch/mips/cavium-octeon/octeon-platform.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 389512e..7b746e7 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -490,8 +490,15 @@ int __init octeon_prune_device_tree(void)
if (alias_prop) {
uart = fdt_path_offset(initial_boot_params, alias_prop);
- if (uart_mask & (1 << i))
+ if (uart_mask & (1 << i)) {
+ __be32 f;
+
+ f = cpu_to_be32(octeon_get_io_clock_rate());
+ fdt_setprop_inplace(initial_boot_params,
+ uart, "clock-frequency",
+ &f, sizeof(f));
continue;
+ }
pr_debug("Deleting uart%d\n", i);
fdt_nop_node(initial_boot_params, uart);
fdt_nop_property(initial_boot_params, aliases,
--
1.7.11.7
From: David Daney <[email protected]>
We will use 8250_dw instead.
Signed-off-by: David Daney <[email protected]>
---
arch/mips/cavium-octeon/Makefile | 2 +-
arch/mips/cavium-octeon/serial.c | 109 ---------------------------------------
2 files changed, 1 insertion(+), 110 deletions(-)
delete mode 100644 arch/mips/cavium-octeon/serial.c
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index e3fd50c..4e95204 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -12,7 +12,7 @@
CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt
CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
-obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y += dma-octeon.o
obj-y += octeon-memcpy.o
obj-y += executive/
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
deleted file mode 100644
index f393f65..0000000
--- a/arch/mips/cavium-octeon/serial.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004-2007 Cavium Networks
- */
-#include <linux/console.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_reg.h>
-#include <linux/tty.h>
-#include <linux/irq.h>
-
-#include <asm/time.h>
-
-#include <asm/octeon/octeon.h>
-
-#define DEBUG_UART 1
-
-unsigned int octeon_serial_in(struct uart_port *up, int offset)
-{
- int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
- if (offset == UART_IIR && (rv & 0xf) == 7) {
- /* Busy interrupt, read the USR (39) and try again. */
- cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
- rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
- }
- return rv;
-}
-
-void octeon_serial_out(struct uart_port *up, int offset, int value)
-{
- /*
- * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
- * working.
- */
- if (offset == UART_LCR)
- value &= 0x9f;
- cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
-}
-
-static int octeon_serial_probe(struct platform_device *pdev)
-{
- int irq, res;
- struct resource *res_mem;
- struct uart_8250_port up;
-
- /* All adaptors have an irq. */
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
-
- memset(&up, 0, sizeof(up));
-
- up.port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
- up.port.type = PORT_OCTEON;
- up.port.iotype = UPIO_MEM;
- up.port.regshift = 3;
- up.port.dev = &pdev->dev;
-
- if (octeon_is_simulation())
- /* Make simulator output fast*/
- up.port.uartclk = 115200 * 16;
- else
- up.port.uartclk = octeon_get_io_clock_rate();
-
- up.port.serial_in = octeon_serial_in;
- up.port.serial_out = octeon_serial_out;
- up.port.irq = irq;
-
- res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res_mem == NULL) {
- dev_err(&pdev->dev, "found no memory resource\n");
- return -ENXIO;
- }
- up.port.mapbase = res_mem->start;
- up.port.membase = ioremap(res_mem->start, resource_size(res_mem));
-
- res = serial8250_register_8250_port(&up);
-
- return res >= 0 ? 0 : res;
-}
-
-static struct of_device_id octeon_serial_match[] = {
- {
- .compatible = "cavium,octeon-3860-uart",
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, octeon_serial_match);
-
-static struct platform_driver octeon_serial_driver = {
- .probe = octeon_serial_probe,
- .driver = {
- .owner = THIS_MODULE,
- .name = "octeon_serial",
- .of_match_table = octeon_serial_match,
- },
-};
-
-static int __init octeon_serial_init(void)
-{
- return platform_driver_register(&octeon_serial_driver);
-}
-late_initcall(octeon_serial_init);
--
1.7.11.7
From: David Daney <[email protected]>
The serial port changes make it advisable to enable the proper UART
drivers.
Signed-off-by: David Daney <[email protected]>
---
arch/mips/configs/cavium_octeon_defconfig | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig
index 1888e5f..dace582 100644
--- a/arch/mips/configs/cavium_octeon_defconfig
+++ b/arch/mips/configs/cavium_octeon_defconfig
@@ -1,13 +1,11 @@
CONFIG_CAVIUM_OCTEON_SOC=y
CONFIG_CAVIUM_CN63XXP1=y
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
-CONFIG_SPARSEMEM_MANUAL=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_SMP=y
CONFIG_NR_CPUS=32
CONFIG_HZ_100=y
CONFIG_PREEMPT=y
-CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
@@ -50,7 +48,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
# CONFIG_MTD_OF_PARTS is not set
-CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
@@ -114,6 +111,7 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_OCTEON=y
--
1.7.11.7
From: David Daney <[email protected]>
A few differences needed by OCTEON:
o These are DWC UARTS, but have USR at a different offset.
o Internal SoC buses require reading back from registers to maintain
write ordering.
o 8250 on OCTEON appears with 64-bit wide registers, so when using
readb/writeb in big endian mode we have to adjust the membase to hit
the proper part of the register.
o No UCV register, so we hard code some properties.
Because OCTEON doesn't have a UCV register, I change where
dw8250_setup_port(), which reads the UCV, is called by pushing it in
to the OF and ACPI probe functions, and move unchanged
dw8250_setup_port() earlier in the file.
Signed-off-by: David Daney <[email protected]>
Acked-by: Greg Kroah-Hartman <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Heikki Krogerus <[email protected]>
---
drivers/tty/serial/8250/8250_dw.c | 108 ++++++++++++++++++++++++--------------
1 file changed, 69 insertions(+), 39 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index d07b6af..76a8daa 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -29,6 +29,8 @@
#include <linux/clk.h>
#include <linux/pm_runtime.h>
+#include <asm/byteorder.h>
+
#include "8250.h"
/* Offsets for the DesignWare specific registers */
@@ -57,6 +59,7 @@ struct dw8250_data {
int last_lcr;
int line;
struct clk *clk;
+ u8 usr_reg;
};
static void dw8250_serial_out(struct uart_port *p, int offset, int value)
@@ -77,6 +80,13 @@ static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
return readb(p->membase + offset);
}
+/* Read Back (rb) version to ensure register access ording. */
+static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
+{
+ dw8250_serial_out(p, offset, value);
+ dw8250_serial_in(p, UART_LCR);
+}
+
static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
{
struct dw8250_data *d = p->private_data;
@@ -104,7 +114,7 @@ static int dw8250_handle_irq(struct uart_port *p)
return 1;
} else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
/* Clear the USR and write the LCR again. */
- (void)p->serial_in(p, DW_UART_USR);
+ (void)p->serial_in(p, d->usr_reg);
p->serial_out(p, UART_LCR, d->last_lcr);
return 1;
@@ -125,12 +135,60 @@ dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
pm_runtime_put_sync_suspend(port->dev);
}
-static int dw8250_probe_of(struct uart_port *p)
+static void dw8250_setup_port(struct uart_8250_port *up)
+{
+ struct uart_port *p = &up->port;
+ u32 reg = readl(p->membase + DW_UART_UCV);
+
+ /*
+ * If the Component Version Register returns zero, we know that
+ * ADDITIONAL_FEATURES are not enabled. No need to go any further.
+ */
+ if (!reg)
+ return;
+
+ dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
+ (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
+
+ reg = readl(p->membase + DW_UART_CPR);
+ if (!reg)
+ return;
+
+ /* Select the type based on fifo */
+ if (reg & DW_UART_CPR_FIFO_MODE) {
+ p->type = PORT_16550A;
+ p->flags |= UPF_FIXED_TYPE;
+ p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
+ up->tx_loadsz = p->fifosize;
+ up->capabilities = UART_CAP_FIFO;
+ }
+
+ if (reg & DW_UART_CPR_AFCE_MODE)
+ up->capabilities |= UART_CAP_AFE;
+}
+
+static int dw8250_probe_of(struct uart_port *p,
+ struct dw8250_data *data)
{
struct device_node *np = p->dev->of_node;
u32 val;
-
- if (!of_property_read_u32(np, "reg-io-width", &val)) {
+ bool has_ucv = true;
+
+ if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
+#ifdef __BIG_ENDIAN
+ /*
+ * Low order bits of these 64-bit registers, when
+ * accessed as a byte, are 7 bytes further down in the
+ * address space in big endian mode.
+ */
+ p->membase += 7;
+#endif
+ p->serial_out = dw8250_serial_out_rb;
+ p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
+ p->type = PORT_OCTEON;
+ data->usr_reg = 0x27;
+ has_ucv = false;
+ } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
switch (val) {
case 1:
break;
@@ -144,6 +202,8 @@ static int dw8250_probe_of(struct uart_port *p)
return -EINVAL;
}
}
+ if (has_ucv)
+ dw8250_setup_port(container_of(p, struct uart_8250_port, port));
if (!of_property_read_u32(np, "reg-shift", &val))
p->regshift = val;
@@ -168,6 +228,8 @@ static int dw8250_probe_acpi(struct uart_8250_port *up)
const struct acpi_device_id *id;
struct uart_port *p = &up->port;
+ dw8250_setup_port(up);
+
id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
if (!id)
return -ENODEV;
@@ -196,38 +258,6 @@ static inline int dw8250_probe_acpi(struct uart_8250_port *up)
}
#endif /* CONFIG_ACPI */
-static void dw8250_setup_port(struct uart_8250_port *up)
-{
- struct uart_port *p = &up->port;
- u32 reg = readl(p->membase + DW_UART_UCV);
-
- /*
- * If the Component Version Register returns zero, we know that
- * ADDITIONAL_FEATURES are not enabled. No need to go any further.
- */
- if (!reg)
- return;
-
- dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
- (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
-
- reg = readl(p->membase + DW_UART_CPR);
- if (!reg)
- return;
-
- /* Select the type based on fifo */
- if (reg & DW_UART_CPR_FIFO_MODE) {
- p->type = PORT_16550A;
- p->flags |= UPF_FIXED_TYPE;
- p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
- up->tx_loadsz = p->fifosize;
- up->capabilities = UART_CAP_FIFO;
- }
-
- if (reg & DW_UART_CPR_AFCE_MODE)
- up->capabilities |= UART_CAP_AFE;
-}
-
static int dw8250_probe(struct platform_device *pdev)
{
struct uart_8250_port uart = {};
@@ -259,6 +289,7 @@ static int dw8250_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
+ data->usr_reg = DW_UART_USR;
data->clk = devm_clk_get(&pdev->dev, NULL);
if (!IS_ERR(data->clk)) {
clk_prepare_enable(data->clk);
@@ -270,10 +301,8 @@ static int dw8250_probe(struct platform_device *pdev)
uart.port.serial_out = dw8250_serial_out;
uart.port.private_data = data;
- dw8250_setup_port(&uart);
-
if (pdev->dev.of_node) {
- err = dw8250_probe_of(&uart.port);
+ err = dw8250_probe_of(&uart.port, data);
if (err)
return err;
} else if (ACPI_HANDLE(&pdev->dev)) {
@@ -362,6 +391,7 @@ static const struct dev_pm_ops dw8250_pm_ops = {
static const struct of_device_id dw8250_of_match[] = {
{ .compatible = "snps,dw-apb-uart" },
+ { .compatible = "cavium,octeon-3860-uart" },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dw8250_of_match);
--
1.7.11.7
On Wednesday 19 June 2013, David Daney wrote:
> From: David Daney <[email protected]>
>
> A few differences needed by OCTEON:
>
> o These are DWC UARTS, but have USR at a different offset.
>
> o Internal SoC buses require reading back from registers to maintain
> write ordering.
>
> o 8250 on OCTEON appears with 64-bit wide registers, so when using
> readb/writeb in big endian mode we have to adjust the membase to hit
> the proper part of the register.
>
> o No UCV register, so we hard code some properties.
>
> Because OCTEON doesn't have a UCV register, I change where
> dw8250_setup_port(), which reads the UCV, is called by pushing it in
> to the OF and ACPI probe functions, and move unchanged
> dw8250_setup_port() earlier in the file.
>
> Signed-off-by: David Daney <[email protected]>
> Acked-by: Greg Kroah-Hartman <[email protected]>
> Cc: Arnd Bergmann <[email protected]>
> Cc: Heikki Krogerus <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
On Wed, Jun 19, 2013 at 02:37:27PM -0700, David Daney wrote:
> From: David Daney <[email protected]>
>
> A few differences needed by OCTEON:
>
> o These are DWC UARTS, but have USR at a different offset.
>
> o Internal SoC buses require reading back from registers to maintain
> write ordering.
>
> o 8250 on OCTEON appears with 64-bit wide registers, so when using
> readb/writeb in big endian mode we have to adjust the membase to hit
> the proper part of the register.
>
> o No UCV register, so we hard code some properties.
>
> Because OCTEON doesn't have a UCV register, I change where
> dw8250_setup_port(), which reads the UCV, is called by pushing it in
> to the OF and ACPI probe functions, and move unchanged
> dw8250_setup_port() earlier in the file.
>
> Signed-off-by: David Daney <[email protected]>
> Acked-by: Greg Kroah-Hartman <[email protected]>
> Cc: Arnd Bergmann <[email protected]>
> Cc: Heikki Krogerus <[email protected]>
Reviewed-by: Heikki Krogerus <[email protected]>
--
heikki