This patch set catches up with latest Berlin improvements provided
by Antoine - in particular SATA PHY support and AHCI generic for
Berlin BG2.
Marvell BSP code for BG2 suggests more differences between the two
PHY revisions found on BG2 and BG2Q, but the only important one seems
to be the PHY_BASE used in AHCI vendor-specific registers. I also
confirmed that power_off does indeed power off the PHY on BG2, too
(It wasn't very clear in BSP code).
Anyway, I have tested this on BG2-based Sony NSZ-GS7 and attached
SATA HDD is successfully detected and partitions are displayed.
The patches are currently based on next-20141009 and I plan to resend
once v3.18-rc1 drops. A branch based on next-20141009 with this patches
applied can be found on
git://git.infradead.org/users/hesselba/linux-berlin.git devel/bg2-sata-v1
Patch 1 prepares phy-berlin-sata to support different PHY_BASE addresses
by moving the constant to driver private data.
Patches 2 and 3 add a new compatible to driver and DT documentation that
reflects the differences between BG2Q and BG2 SATA PHY.
Patches 4 and 5 finally add DT nodes to both Berlin2 SoC dtsi and Sony
NSZ-GS7 board DT file. SATA plug on NSZ-GS7 is unpopulated but can be
very easily equipped with SATA receptable and some 0402 caps. I decided
to enable SATA by default although not all users may populate it.
Sebastian
Sebastian Hesselbarth (5):
phy: berlin-sata: Move PHY_BASE into private data struct
phy: berlin-sata: Add support for BG2 SATA PHY
phy: berlin-sata: Document BG2 compatible
ARM: berlin: Add AHCI and SATA PHY nodes to BG2
ARM: berlin: Enable SATA on Sony NSZ-GS7
.../devicetree/bindings/phy/berlin-sata-phy.txt | 4 +-
arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 7 ++++
arch/arm/boot/dts/berlin2.dtsi | 40 ++++++++++++++++++
drivers/phy/phy-berlin-sata.c | 48 +++++++++++++++-------
4 files changed, 84 insertions(+), 15 deletions(-)
---
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
--
2.1.1
Marvell Berlin BG2 based Sony NSZ-GS7 has an unpopulated SATA plug
on its PCB solder side. As it is quite easy to populate and I have
done it, enable AHCI and SATA by default.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
index c72bfd468d10..0a13e8a5da15 100644
--- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -26,4 +26,11 @@
};
};
+&ahci { status = "okay"; };
+
+/* Unpopulated SATA plug on solder side */
+&sata0 { status = "okay"; };
+
+&sata_phy { status = "okay"; };
+
&uart0 { status = "okay"; };
--
2.1.1
Add DT nodes for the AHCI controller and SATA PHY found on Marvell
Berlin2 SoCs.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/berlin2.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index d7e81e124de0..7bfe51986a35 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -246,6 +246,46 @@
};
};
+ ahci: sata@e90000 {
+ compatible = "marvell,berlin2-ahci", "generic-ahci";
+ reg = <0xe90000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&chip CLKID_SATA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy 0>;
+ status = "disabled";
+ };
+
+ sata1: sata-port@1 {
+ reg = <1>;
+ phys = <&sata_phy 1>;
+ status = "disabled";
+ };
+ };
+
+ sata_phy: phy@e900a0 {
+ compatible = "marvell,berlin2-sata-phy";
+ reg = <0xe900a0 0x200>;
+ clocks = <&chip CLKID_SATA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ sata-phy@0 {
+ reg = <0>;
+ };
+
+ sata-phy@1 {
+ reg = <1>;
+ };
+ };
+
chip: chip-control@ea0000 {
compatible = "marvell,berlin2-chip-ctrl";
#clock-cells = <1>;
--
2.1.1
Currently, Berlin SATA PHY driver assumes PHY_BASE address being
constant. While this PHY_BASE is correct for BG2Q, older BG2 PHY_BASE
is different. Prepare the driver for BG2 support by moving the phy_base
into private driver data.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/phy/phy-berlin-sata.c | 42 ++++++++++++++++++++++++++++--------------
1 file changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/phy/phy-berlin-sata.c b/drivers/phy/phy-berlin-sata.c
index 69ced52d72aa..9682b0f66177 100644
--- a/drivers/phy/phy-berlin-sata.c
+++ b/drivers/phy/phy-berlin-sata.c
@@ -30,7 +30,7 @@
#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
-#define PHY_BASE 0x200
+#define BG2Q_PHY_BASE 0x200
/* register 0x01 */
#define REF_FREF_SEL_25 BIT(0)
@@ -61,15 +61,16 @@ struct phy_berlin_priv {
struct clk *clk;
struct phy_berlin_desc **phys;
unsigned nphys;
+ u32 phy_base;
};
-static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, u32 reg,
- u32 mask, u32 val)
+static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
+ u32 phy_base, u32 reg, u32 mask, u32 val)
{
u32 regval;
/* select register */
- writel(PHY_BASE + reg, ctrl_reg + PORT_VSR_ADDR);
+ writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
/* set bits */
regval = readl(ctrl_reg + PORT_VSR_DATA);
@@ -103,17 +104,20 @@ static int phy_berlin_sata_power_on(struct phy *phy)
writel(regval, priv->base + HOST_VSA_DATA);
/* set PHY mode and ref freq to 25 MHz */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x1, 0xff,
- REF_FREF_SEL_25 | PHY_MODE_SATA);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
+ 0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA);
/* set PHY up to 6 Gbps */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x25, 0xc00, PHY_GEN_MAX_6_0);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
+ 0x0c00, PHY_GEN_MAX_6_0);
/* set 40 bits width */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x23, 0xc00, DATA_BIT_WIDTH_40);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
+ 0x0c00, DATA_BIT_WIDTH_40);
/* use max pll rate */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x2, 0x0, USE_MAX_PLL_RATE);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
+ 0x0000, USE_MAX_PLL_RATE);
/* set Gen3 controller speed */
regval = readl(ctrl_reg + PORT_SCR_CTL);
@@ -182,9 +186,22 @@ static u32 phy_berlin_power_down_bits[] = {
POWER_DOWN_PHY1,
};
+static u32 bg2q_sata_phy_base = BG2Q_PHY_BASE;
+
+static const struct of_device_id phy_berlin_sata_of_match[] = {
+ {
+ .compatible = "marvell,berlin2q-sata-phy",
+ .data = &bg2q_sata_phy_base,
+ },
+ { },
+};
+
static int phy_berlin_sata_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ const struct of_device_id *match =
+ of_match_node(phy_berlin_sata_of_match, dev->of_node);
+ const u32 *phy_base = match->data;
struct device_node *child;
struct phy *phy;
struct phy_provider *phy_provider;
@@ -218,6 +235,8 @@ static int phy_berlin_sata_probe(struct platform_device *pdev)
if (!priv->phys)
return -ENOMEM;
+ priv->phy_base = *phy_base;
+
dev_set_drvdata(dev, priv);
spin_lock_init(&priv->lock);
@@ -264,11 +283,6 @@ static int phy_berlin_sata_probe(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id phy_berlin_sata_of_match[] = {
- { .compatible = "marvell,berlin2q-sata-phy" },
- { },
-};
-
static struct platform_driver phy_berlin_sata_driver = {
.probe = phy_berlin_sata_probe,
.driver = {
--
2.1.1
Berlin BG2 also has a SATA PHY compatible with the current driver
except different PHY_BASE. Add a new compatible to the driver
reflecting the different PHY_BASE.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/phy/phy-berlin-sata.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/phy/phy-berlin-sata.c b/drivers/phy/phy-berlin-sata.c
index 9682b0f66177..71568f5444ac 100644
--- a/drivers/phy/phy-berlin-sata.c
+++ b/drivers/phy/phy-berlin-sata.c
@@ -30,6 +30,7 @@
#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
+#define BG2_PHY_BASE 0x080
#define BG2Q_PHY_BASE 0x200
/* register 0x01 */
@@ -186,10 +187,15 @@ static u32 phy_berlin_power_down_bits[] = {
POWER_DOWN_PHY1,
};
+static u32 bg2_sata_phy_base = BG2_PHY_BASE;
static u32 bg2q_sata_phy_base = BG2Q_PHY_BASE;
static const struct of_device_id phy_berlin_sata_of_match[] = {
{
+ .compatible = "marvell,berlin2-sata-phy",
+ .data = &bg2_sata_phy_base,
+ },
+ {
.compatible = "marvell,berlin2q-sata-phy",
.data = &bg2q_sata_phy_base,
},
--
2.1.1
Berlin BG2 SATA PHY is slightly different from currently supported
BG2Q SATA PHY. Document the new compatible for BG2's PHY.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: "Antoine Ténart" <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
Documentation/devicetree/bindings/phy/berlin-sata-phy.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
index 88f8c23384c0..c0155f842f62 100644
--- a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
+++ b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
@@ -2,7 +2,9 @@ Berlin SATA PHY
---------------
Required properties:
-- compatible: should be "marvell,berlin2q-sata-phy"
+- compatible: should be one of
+ "marvell,berlin2-sata-phy"
+ "marvell,berlin2q-sata-phy"
- address-cells: should be 1
- size-cells: should be 0
- phy-cells: from the generic PHY bindings, must be 1
--
2.1.1
Hi Sebastian,
On Sat, Oct 11, 2014 at 05:41:12PM +0200, Sebastian Hesselbarth wrote:
>
> + ahci: sata@e90000 {
> + compatible = "marvell,berlin2-ahci", "generic-ahci";
> + reg = <0xe90000 0x1000>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&chip CLKID_SATA>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
The ahci generic driver actually returns -ENODEV if no port is
activated. There is no need to disable it from there.
> +
> + sata0: sata-port@0 {
> + reg = <0>;
> + phys = <&sata_phy 0>;
> + status = "disabled";
> + };
> +
> + sata1: sata-port@1 {
> + reg = <1>;
> + phys = <&sata_phy 1>;
> + status = "disabled";
> + };
> + };
Antoine
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Hi Sebastian,
On Sat, Oct 11, 2014 at 05:41:08PM +0200, Sebastian Hesselbarth wrote:
> This patch set catches up with latest Berlin improvements provided
> by Antoine - in particular SATA PHY support and AHCI generic for
> Berlin BG2.
>
> Marvell BSP code for BG2 suggests more differences between the two
> PHY revisions found on BG2 and BG2Q, but the only important one seems
> to be the PHY_BASE used in AHCI vendor-specific registers. I also
> confirmed that power_off does indeed power off the PHY on BG2, too
> (It wasn't very clear in BSP code).
>
> Anyway, I have tested this on BG2-based Sony NSZ-GS7 and attached
> SATA HDD is successfully detected and partitions are displayed.
>
> The patches are currently based on next-20141009 and I plan to resend
> once v3.18-rc1 drops. A branch based on next-20141009 with this patches
> applied can be found on
>
> git://git.infradead.org/users/hesselba/linux-berlin.git devel/bg2-sata-v1
>
> Patch 1 prepares phy-berlin-sata to support different PHY_BASE addresses
> by moving the constant to driver private data.
>
> Patches 2 and 3 add a new compatible to driver and DT documentation that
> reflects the differences between BG2Q and BG2 SATA PHY.
>
> Patches 4 and 5 finally add DT nodes to both Berlin2 SoC dtsi and Sony
> NSZ-GS7 board DT file. SATA plug on NSZ-GS7 is unpopulated but can be
> very easily equipped with SATA receptable and some 0402 caps. I decided
> to enable SATA by default although not all users may populate it.
Apart for the little comment, you can add:
Acked-by : Antoine Tenart <[email protected]>
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com