From: Matt Fleming <[email protected]>
This patch series adds a new PMU driver for the Intel Cache Monitoring
hardware feature available in Intel Xeon processors, which allows
monitoring of LLC occupancy on a task, group or system-wide basis.
The first few patches modify tools/perf to handle per-package counters,
which necessitates discarding some values when doing per-cpu reads to
avoid getting duplicate data. The rest add support for the new PMU code.
I've left a notoriously funky bit of code as the last patch, the RMID
rotation code, in an attempt to simplify things. Doing the rotation
provides the ability to multiplex the RMIDs and basically overcome the
hardware limitation, but the rest of the patches work fine without it.
But there are a number of scenarios where being able to monitor more
tasks than RMIDs is extremely useful.
The series is based on tip/perf/core.
Jiri Olsa (1):
perf tools: Implement snapshot event file logic
Changes in v3:
- Dropped patches that have been applied in tip/perf/core
- Upated commit message in PATCH 3 based on Peter's feedback
- Simplified PATCH 5 by only using int cgroup_fd as param
- Added a new patch (11) to perform internal scheduling on conflict
monitoring events
- Make RMIDs wait in limbo for a minimium queue time to avoid IPIs
wherever possible
- Provide a user-configurable upper bound on the recycling threshold
- Reduce the size of a preemption disabled section (pointed out by
Thomas Gleixner)
- Reduce the limbo bitmap size due to worries of mass memory
consumption on larg CPU systems (Peter Zijlstra)
- Picked a patch (2) from Jiri to fix the -I (interval) mode of perf
stat with CQM
Changes in v2:
- Added Jiri Olsa's Acked-by to PATCH 02/11.
- Use x86_match_cpu() in intel_cqm_init() and make sure we grab the
hotplug lock to prevent races as pointed out by Andi Kleen in
PATCH 08/11.
- Delete a stale comment in commit message of PATCH 10/11.
Jiri Olsa (1):
perf tools: Implement snapshot event file logic
Matt Fleming (9):
perf tools: Parse event per-package info files
perf: Make perf_cgroup_from_task() global
perf: Add ->count() function to read per-package counters
perf: Move cgroup init before PMU ->event_init()
perf/x86/intel: Add Intel Cache QoS Monitoring support
perf/x86/intel: Implement LRU monitoring ID allocation for CQM
perf/x86/intel: Support task events with Intel CQM
perf/x86/intel: Perform rotation on Intel CQM RMIDs
perf/x86/intel: Enable conflicting event scheduling for CQM
Peter P Waskiewicz Jr (1):
x86: Add support for Intel Cache QoS Monitoring (CQM) detection
arch/x86/include/asm/cpufeature.h | 9 +-
arch/x86/include/asm/processor.h | 3 +
arch/x86/kernel/cpu/Makefile | 2 +-
arch/x86/kernel/cpu/common.c | 39 +
arch/x86/kernel/cpu/perf_event_intel_cqm.c | 1340 ++++++++++++++++++++++++++++
include/linux/perf_event.h | 48 +
include/uapi/linux/perf_event.h | 1 +
kernel/events/core.c | 63 +-
tools/perf/builtin-stat.c | 88 +-
tools/perf/util/evsel.c | 12 +-
tools/perf/util/evsel.h | 9 +-
tools/perf/util/parse-events.c | 2 +
tools/perf/util/pmu.c | 74 +-
tools/perf/util/pmu.h | 4 +
14 files changed, 1634 insertions(+), 60 deletions(-)
create mode 100644 arch/x86/kernel/cpu/perf_event_intel_cqm.c
--
1.9.3
From: Jiri Olsa <[email protected]>
Adding support to parse and read the snapshot file,
and using this information to omit the compute_delta
function logic.
Signed-off-by: Jiri Olsa <[email protected]>
---
tools/perf/util/evsel.c | 6 ++++--
tools/perf/util/evsel.h | 1 +
tools/perf/util/parse-events.c | 1 +
tools/perf/util/pmu.c | 47 ++++++++++++++++++++++++++++++++----------
tools/perf/util/pmu.h | 2 ++
5 files changed, 44 insertions(+), 13 deletions(-)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index a748e5e16533..bbbebbb49c3a 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -902,7 +902,8 @@ int __perf_evsel__read_on_cpu(struct perf_evsel *evsel,
if (readn(FD(evsel, cpu, thread), &count, nv * sizeof(u64)) < 0)
return -errno;
- compute_deltas(evsel, cpu, &count);
+ if (!evsel->snapshot)
+ compute_deltas(evsel, cpu, &count);
if (scale) {
if (count.run == 0)
@@ -949,7 +950,8 @@ int __perf_evsel__read(struct perf_evsel *evsel,
}
}
- compute_deltas(evsel, -1, aggr);
+ if (!evsel->snapshot)
+ compute_deltas(evsel, -1, aggr);
evsel->counts->scaled = 0;
if (scale) {
diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h
index 13ca8a7693e4..d9fa85e203f8 100644
--- a/tools/perf/util/evsel.h
+++ b/tools/perf/util/evsel.h
@@ -73,6 +73,7 @@ struct perf_evsel {
char *name;
double scale;
const char *unit;
+ bool snapshot;
struct event_format *tp_format;
union {
void *priv;
diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
index 5a373483f0e4..77b43fe43d55 100644
--- a/tools/perf/util/parse-events.c
+++ b/tools/perf/util/parse-events.c
@@ -682,6 +682,7 @@ int parse_events_add_pmu(struct list_head *list, int *idx,
evsel->unit = info.unit;
evsel->scale = info.scale;
evsel->per_pkg = info.per_pkg;
+ evsel->snapshot = info.snapshot;
}
return evsel ? 0 : -ENOMEM;
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index f003b5a9e059..5c9c4947cfb4 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -181,6 +181,23 @@ perf_pmu__parse_per_pkg(struct perf_pmu_alias *alias, char *dir, char *name)
return 0;
}
+static int perf_pmu__parse_snapshot(struct perf_pmu_alias *alias,
+ char *dir, char *name)
+{
+ char path[PATH_MAX];
+ int fd;
+
+ snprintf(path, PATH_MAX, "%s/%s.snapshot", dir, name);
+
+ fd = open(path, O_RDONLY);
+ if (fd == -1)
+ return -1;
+
+ alias->snapshot = true;
+ close(fd);
+ return 0;
+}
+
static int perf_pmu__new_alias(struct list_head *list, char *dir, char *name, FILE *file)
{
struct perf_pmu_alias *alias;
@@ -214,6 +231,7 @@ static int perf_pmu__new_alias(struct list_head *list, char *dir, char *name, FI
perf_pmu__parse_unit(alias, dir, name);
perf_pmu__parse_scale(alias, dir, name);
perf_pmu__parse_per_pkg(alias, dir, name);
+ perf_pmu__parse_snapshot(alias, dir, name);
list_add_tail(&alias->list, list);
@@ -231,6 +249,8 @@ static inline bool pmu_alias_info_file(char *name)
return true;
if (len > 8 && !strcmp(name + len - 8, ".per-pkg"))
return true;
+ if (len > 9 && !strcmp(name + len - 9, ".snapshot"))
+ return true;
return false;
}
@@ -639,23 +659,27 @@ static struct perf_pmu_alias *pmu_find_alias(struct perf_pmu *pmu,
}
-static int check_unit_scale(struct perf_pmu_alias *alias,
- const char **unit, double *scale)
+static int check_info_data(struct perf_pmu_alias *alias,
+ struct perf_pmu_info *info)
{
/*
* Only one term in event definition can
- * define unit and scale, fail if there's
- * more than one.
+ * define unit, scale and snapshot, fail
+ * if there's more than one.
*/
- if ((*unit && alias->unit) ||
- (*scale && alias->scale))
+ if ((info->unit && alias->unit) ||
+ (info->scale && alias->scale) ||
+ (info->snapshot && alias->snapshot))
return -EINVAL;
if (alias->unit)
- *unit = alias->unit;
+ info->unit = alias->unit;
if (alias->scale)
- *scale = alias->scale;
+ info->scale = alias->scale;
+
+ if (alias->snapshot)
+ info->snapshot = alias->snapshot;
return 0;
}
@@ -677,8 +701,9 @@ int perf_pmu__check_alias(struct perf_pmu *pmu, struct list_head *head_terms,
* Mark unit and scale as not set
* (different from default values, see below)
*/
- info->unit = NULL;
- info->scale = 0.0;
+ info->unit = NULL;
+ info->scale = 0.0;
+ info->snapshot = false;
list_for_each_entry_safe(term, h, head_terms, list) {
alias = pmu_find_alias(pmu, term);
@@ -688,7 +713,7 @@ int perf_pmu__check_alias(struct perf_pmu *pmu, struct list_head *head_terms,
if (ret)
return ret;
- ret = check_unit_scale(alias, &info->unit, &info->scale);
+ ret = check_info_data(alias, info);
if (ret)
return ret;
diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h
index c3a74e0e17a2..6b1249fbdb5f 100644
--- a/tools/perf/util/pmu.h
+++ b/tools/perf/util/pmu.h
@@ -30,6 +30,7 @@ struct perf_pmu_info {
const char *unit;
double scale;
bool per_pkg;
+ bool snapshot;
};
#define UNIT_MAX_LEN 31 /* max length for event unit name */
@@ -41,6 +42,7 @@ struct perf_pmu_alias {
char unit[UNIT_MAX_LEN+1];
double scale;
bool per_pkg;
+ bool snapshot;
};
struct perf_pmu *perf_pmu__find(const char *name);
--
1.9.3
From: Peter P Waskiewicz Jr <[email protected]>
This patch adds support for the new Cache QoS Monitoring (CQM)
feature found in future Intel Xeon processors. It includes the
new values to track CQM resources to the cpuinfo_x86 structure,
plus the CPUID detection routines for CQM.
CQM allows a process, or set of processes, to be tracked by the CPU
to determine the cache usage of that task group. Using this data
from the CPU, software can be written to extract this data and
report cache usage and occupancy for a particular process, or
group of processes.
More information about Cache QoS Monitoring can be found in the
Intel (R) x86 Architecture Software Developer Manual, section 17.14.
Signed-off-by: Peter P Waskiewicz Jr <[email protected]>
Signed-off-by: Matt Fleming <[email protected]>
---
arch/x86/include/asm/cpufeature.h | 9 ++++++++-
arch/x86/include/asm/processor.h | 3 +++
arch/x86/kernel/cpu/common.c | 39 +++++++++++++++++++++++++++++++++++++++
3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 0bb1335313b2..a57d98b3e5dd 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -12,7 +12,7 @@
#include <asm/disabled-features.h>
#endif
-#define NCAPINTS 11 /* N 32-bit words worth of info */
+#define NCAPINTS 13 /* N 32-bit words worth of info */
#define NBUGINTS 1 /* N 32-bit bug flags */
/*
@@ -220,6 +220,7 @@
#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
@@ -236,6 +237,12 @@
#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */
#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
+/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
+#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
+
+/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
+#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
+
/*
* BUG word(s)
*/
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index eb71ec794732..2c3a46af3334 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -109,6 +109,9 @@ struct cpuinfo_x86 {
/* in KB - valid for CPUS which support this call: */
int x86_cache_size;
int x86_cache_alignment; /* In bytes */
+ /* Cache QoS architectural values: */
+ int x86_cache_max_rmid; /* max index */
+ int x86_cache_occ_scale; /* scale to bytes */
int x86_power;
unsigned long loops_per_jiffy;
/* cpuid returned max cores value: */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 4b4f78c9ba19..4230745fdcf8 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -642,6 +642,30 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
c->x86_capability[10] = eax;
}
+ /* Additional Intel-defined flags: level 0x0000000F */
+ if (c->cpuid_level >= 0x0000000F) {
+ u32 eax, ebx, ecx, edx;
+
+ /* QoS sub-leaf, EAX=0Fh, ECX=0 */
+ cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
+ c->x86_capability[11] = edx;
+ if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
+ /* will be overridden if occupancy monitoring exists */
+ c->x86_cache_max_rmid = ebx;
+
+ /* QoS sub-leaf, EAX=0Fh, ECX=1 */
+ cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
+ c->x86_capability[12] = edx;
+ if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) {
+ c->x86_cache_max_rmid = ecx;
+ c->x86_cache_occ_scale = ebx;
+ }
+ } else {
+ c->x86_cache_max_rmid = -1;
+ c->x86_cache_occ_scale = -1;
+ }
+ }
+
/* AMD-defined flags: level 0x80000001 */
xlvl = cpuid_eax(0x80000000);
c->extended_cpuid_level = xlvl;
@@ -830,6 +854,20 @@ static void generic_identify(struct cpuinfo_x86 *c)
detect_nopl(c);
}
+static void x86_init_cache_qos(struct cpuinfo_x86 *c)
+{
+ /*
+ * The heavy lifting of max_rmid and cache_occ_scale are handled
+ * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
+ * in case CQM bits really aren't there in this CPU.
+ */
+ if (c != &boot_cpu_data) {
+ boot_cpu_data.x86_cache_max_rmid =
+ min(boot_cpu_data.x86_cache_max_rmid,
+ c->x86_cache_max_rmid);
+ }
+}
+
/*
* This does the hard work of actually picking apart the CPU stuff...
*/
@@ -919,6 +957,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
init_hypervisor(c);
x86_init_rdrand(c);
+ x86_init_cache_qos(c);
/*
* Clear/Set all flags overriden by options, need do it
--
1.9.3
From: Matt Fleming <[email protected]>
For PMU drivers that record per-package counters, the ->count variable
cannot be used to record an accurate aggregated value, since it's not
possible to perform SMP cross-calls to cpus on other packages from the
context in which we update ->count.
Introduce a new optional ->count() accessor function that can be used to
customize how values are collected. If a PMU driver doesn't provide a
->count() function, we fallback to the existing code.
There is necessarily a window of staleness with this approach because
the task that generated the counter value may not have been scheduled by
the cpu recently.
An alternative and more complex approach would be to use a hrtimer to
periodically refresh the values from a more permissive scheduling
context. So, we're trading off complexity for accuracy.
Cc: Jiri Olsa <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Signed-off-by: Matt Fleming <[email protected]>
---
include/linux/perf_event.h | 10 ++++++++++
kernel/events/core.c | 5 ++++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 1a4e2846d6fb..1bf06b6fd5dc 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -264,6 +264,11 @@ struct pmu {
* flush branch stack on context-switches (needed in cpu-wide mode)
*/
void (*flush_branch_stack) (void);
+
+ /*
+ * Return the count value for a counter.
+ */
+ u64 (*count) (struct perf_event *event); /*optional*/
};
/**
@@ -743,6 +748,11 @@ static inline void perf_event_task_sched_out(struct task_struct *prev,
__perf_event_task_sched_out(prev, next);
}
+static inline u64 __perf_event_count(struct perf_event *event)
+{
+ return local64_read(&event->count) + atomic64_read(&event->child_count);
+}
+
extern void perf_event_mmap(struct vm_area_struct *vma);
extern struct perf_guest_info_callbacks *perf_guest_cbs;
extern int perf_register_guest_info_callbacks(struct perf_guest_info_callbacks *callbacks);
diff --git a/kernel/events/core.c b/kernel/events/core.c
index a65f4c47eb56..a2ea4a52dbbf 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -3074,7 +3074,10 @@ static void __perf_event_read(void *info)
static inline u64 perf_event_count(struct perf_event *event)
{
- return local64_read(&event->count) + atomic64_read(&event->child_count);
+ if (event->pmu->count)
+ return event->pmu->count(event);
+
+ return __perf_event_count(event);
}
static u64 perf_event_read(struct perf_event *event)
--
1.9.3
From: Matt Fleming <[email protected]>
Add support for task events as well as system-wide events. This change
has a big impact on the way that we gather LLC occupancy values in
intel_cqm_event_read().
Currently, for system-wide (per-cpu) events we defer processing to
userspace which knows how to discard all but one cpu result per package.
Things aren't so simple for task events because we need to do the value
aggregation ourselves. To do this, we defer updating the LLC occupancy
value in event->count from intel_cqm_event_read() and do an SMP
cross-call to read values for all packages in intel_cqm_event_count().
We need to ensure that we only do this for one task event per cache
group, otherwise we'll report duplicate values.
If we're a system-wide event we want to fallback to the default
perf_event_count() implementation. Refactor this into a common function
so that we don't duplicate the code.
Also, introduce PERF_TYPE_INTEL_CQM, since we need a way to track an
event's task (if the event isn't per-cpu) inside of the Intel CQM PMU
driver. This task information is only availble in the upper layers of
the perf infrastructure.
Other perf backends stash the target task in event->hw.*target so we
need to do something similar. The task is used to determine whether
events should share a cache group and an RMID.
Cc: Jiri Olsa <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Signed-off-by: Matt Fleming <[email protected]>
---
arch/x86/kernel/cpu/perf_event_intel_cqm.c | 187 +++++++++++++++++++++++++----
include/linux/perf_event.h | 1 +
include/uapi/linux/perf_event.h | 1 +
kernel/events/core.c | 2 +
4 files changed, 170 insertions(+), 21 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
index 60e0043ca922..ffbda0fd4997 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -182,23 +182,124 @@ fail:
/*
* Determine if @a and @b measure the same set of tasks.
+ *
+ * If @a and @b measure the same set of tasks then we want to share a
+ * single RMID.
*/
static bool __match_event(struct perf_event *a, struct perf_event *b)
{
+ /* Per-cpu and task events don't mix */
if ((a->attach_state & PERF_ATTACH_TASK) !=
(b->attach_state & PERF_ATTACH_TASK))
return false;
- /* not task */
+#ifdef CONFIG_CGROUP_PERF
+ if (a->cgrp != b->cgrp)
+ return false;
+#endif
+
+ /* If not task event, we're machine wide */
+ if (!(b->attach_state & PERF_ATTACH_TASK))
+ return true;
- return true; /* if not task, we're machine wide */
+ /*
+ * Events that target same task are placed into the same cache group.
+ */
+ if (a->hw.cqm_target == b->hw.cqm_target)
+ return true;
+
+ /*
+ * Are we an inherited event?
+ */
+ if (b->parent == a)
+ return true;
+
+ return false;
+}
+
+#ifdef CONFIG_CGROUP_PERF
+static inline struct perf_cgroup *event_to_cgroup(struct perf_event *event)
+{
+ if (event->attach_state & PERF_ATTACH_TASK)
+ return perf_cgroup_from_task(event->hw.cqm_target);
+
+ return event->cgrp;
}
+#endif
/*
* Determine if @a's tasks intersect with @b's tasks
+ *
+ * There are combinations of events that we explicitly prohibit,
+ *
+ * PROHIBITS
+ * system-wide -> cgroup and task
+ * cgroup -> system-wide
+ * -> task in cgroup
+ * task -> system-wide
+ * -> task in cgroup
+ *
+ * Call this function before allocating an RMID.
*/
static bool __conflict_event(struct perf_event *a, struct perf_event *b)
{
+#ifdef CONFIG_CGROUP_PERF
+ /*
+ * We can have any number of cgroups but only one system-wide
+ * event at a time.
+ */
+ if (a->cgrp && b->cgrp) {
+ struct perf_cgroup *ac = a->cgrp;
+ struct perf_cgroup *bc = b->cgrp;
+
+ /*
+ * This condition should have been caught in
+ * __match_event() and we should be sharing an RMID.
+ */
+ WARN_ON_ONCE(ac == bc);
+
+ if (cgroup_is_descendant(ac->css.cgroup, bc->css.cgroup) ||
+ cgroup_is_descendant(bc->css.cgroup, ac->css.cgroup))
+ return true;
+
+ return false;
+ }
+
+ if (a->cgrp || b->cgrp) {
+ struct perf_cgroup *ac, *bc;
+
+ /*
+ * cgroup and system-wide events are mutually exclusive
+ */
+ if ((a->cgrp && !(b->attach_state & PERF_ATTACH_TASK)) ||
+ (b->cgrp && !(a->attach_state & PERF_ATTACH_TASK)))
+ return true;
+
+ /*
+ * Ensure neither event is part of the other's cgroup
+ */
+ ac = event_to_cgroup(a);
+ bc = event_to_cgroup(b);
+ if (ac == bc)
+ return true;
+
+ /*
+ * Must have cgroup and non-intersecting task events.
+ */
+ if (!ac || !bc)
+ return false;
+
+ /*
+ * We have cgroup and task events, and the task belongs
+ * to a cgroup. Check for for overlap.
+ */
+ if (cgroup_is_descendant(ac->css.cgroup, bc->css.cgroup) ||
+ cgroup_is_descendant(bc->css.cgroup, ac->css.cgroup))
+ return true;
+
+ return false;
+ }
+#endif
/*
* If one of them is not a task, same story as above with cgroups.
*/
@@ -245,9 +346,16 @@ static int intel_cqm_setup_event(struct perf_event *event,
static void intel_cqm_event_read(struct perf_event *event)
{
- unsigned long rmid = event->hw.cqm_rmid;
+ unsigned long rmid;
u64 val;
+ /*
+ * Task events are handled by intel_cqm_event_count().
+ */
+ if (event->cpu == -1)
+ return;
+
+ rmid = event->hw.cqm_rmid;
val = __rmid_read(rmid);
/*
@@ -259,6 +367,55 @@ static void intel_cqm_event_read(struct perf_event *event)
local64_set(&event->count, val);
}
+static void __intel_cqm_event_count(void *info)
+{
+ struct perf_event *event = info;
+ u64 val;
+
+ val = __rmid_read(event->hw.cqm_rmid);
+
+ if (val & (RMID_VAL_ERROR | RMID_VAL_UNAVAIL))
+ return;
+
+ local64_add(val, &event->count);
+}
+
+static inline bool cqm_group_leader(struct perf_event *event)
+{
+ return !list_empty(&event->hw.cqm_groups_entry);
+}
+
+static u64 intel_cqm_event_count(struct perf_event *event)
+{
+ /*
+ * We only need to worry about task events. System-wide events
+ * are handled like usual, i.e. entirely with
+ * intel_cqm_event_read().
+ */
+ if (event->cpu != -1)
+ return __perf_event_count(event);
+
+ /*
+ * Only the group leader gets to report values. This stops us
+ * reporting duplicate values to userspace, and gives us a clear
+ * rule for which task gets to report the values.
+ *
+ * Note that it is impossible to attribute these values to
+ * specific packages - we forfeit that ability when we create
+ * task events.
+ */
+ if (!cqm_group_leader(event))
+ return 0;
+
+ local64_set(&event->count, 0);
+
+ preempt_disable()
+ smp_call_function_many(&cqm_cpumask, __intel_cqm_event_count, event, 1);
+ preempt_enable();
+
+ return __perf_event_count(event);
+}
+
static void intel_cqm_event_start(struct perf_event *event, int mode)
{
struct intel_cqm_state *state = &__get_cpu_var(cqm_state);
@@ -344,7 +501,7 @@ static void intel_cqm_event_destroy(struct perf_event *event)
/*
* And we're the group leader..
*/
- if (!list_empty(&event->hw.cqm_groups_entry)) {
+ if (cqm_group_leader(event)) {
/*
* If there was a group_other, make that leader, otherwise
* destroy the group and return the RMID.
@@ -364,17 +521,6 @@ static void intel_cqm_event_destroy(struct perf_event *event)
static struct pmu intel_cqm_pmu;
-/*
- * XXX there's a bit of a problem in that we cannot simply do the one
- * event per node as one would want, since that one event would one get
- * scheduled on the one cpu. But we want to 'schedule' the RMID on all
- * CPUs.
- *
- * This means we want events for each CPU, however, that generates a lot
- * of duplicate values out to userspace -- this is not to be helped
- * unless we want to change the core code in some way. Fore more info,
- * see intel_cqm_event_read().
- */
static int intel_cqm_event_init(struct perf_event *event)
{
struct perf_event *group = NULL;
@@ -386,9 +532,6 @@ static int intel_cqm_event_init(struct perf_event *event)
if (event->attr.config & ~QOS_EVENT_MASK)
return -EINVAL;
- if (event->cpu == -1)
- return -EINVAL;
-
/* unsupported modes and filters */
if (event->attr.exclude_user ||
event->attr.exclude_kernel ||
@@ -406,7 +549,8 @@ static int intel_cqm_event_init(struct perf_event *event)
mutex_lock(&cache_mutex);
- err = intel_cqm_setup_event(event, &group); /* will also set rmid */
+ /* Will also set rmid */
+ err = intel_cqm_setup_event(event, &group);
if (err)
goto out;
@@ -469,6 +613,7 @@ static struct pmu intel_cqm_pmu = {
.start = intel_cqm_event_start,
.stop = intel_cqm_event_stop,
.read = intel_cqm_event_read,
+ .count = intel_cqm_event_count,
};
static inline void cqm_pick_event_reader(int cpu)
@@ -597,8 +742,8 @@ static int __init intel_cqm_init(void)
__perf_cpu_notifier(intel_cqm_cpu_notifier);
- ret = perf_pmu_register(&intel_cqm_pmu, "intel_cqm", -1);
-
+ ret = perf_pmu_register(&intel_cqm_pmu, "intel_cqm",
+ PERF_TYPE_INTEL_CQM);
if (ret)
pr_err("Intel CQM perf registration failed: %d\n", ret);
else
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 50ceb0665cda..4cb6e1e668a1 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -134,6 +134,7 @@ struct hw_perf_event {
struct list_head cqm_events_entry;
struct list_head cqm_groups_entry;
struct list_head cqm_group_entry;
+ struct task_struct *cqm_target;
};
#ifdef CONFIG_HAVE_HW_BREAKPOINT
struct { /* breakpoint */
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 9d845404d875..0706ed0a0bf2 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -32,6 +32,7 @@ enum perf_type_id {
PERF_TYPE_HW_CACHE = 3,
PERF_TYPE_RAW = 4,
PERF_TYPE_BREAKPOINT = 5,
+ PERF_TYPE_INTEL_CQM = 6,
PERF_TYPE_MAX, /* non-ABI */
};
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 540d995322dd..31469c739216 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -6949,6 +6949,8 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu,
else if (attr->type == PERF_TYPE_BREAKPOINT)
event->hw.bp_target = task;
#endif
+ else if (attr->type == PERF_TYPE_INTEL_CQM)
+ event->hw.cqm_target = task;
}
if (!overflow_handler && parent_event) {
--
1.9.3
From: Matt Fleming <[email protected]>
We can leverage the workqueue that we use for RMID rotation to support
scheduling of conflicting monitoring events. Allowing events that
monitor conflicting things is done at various other places in the perf
subsystem, so there's precedent there.
An example of two conflicting events would be monitoring a cgroup and
simultaneously monitoring a task within that cgroup.
This uses the cache_groups list as a queuing mechanism, where every
event that reaches the front of the list gets the chance to be scheduled
in, possibly descheduling any conflicting events that are running.
Cc: Peter Zijlstra <[email protected]>
Signed-off-by: Matt Fleming <[email protected]>
---
arch/x86/kernel/cpu/perf_event_intel_cqm.c | 161 ++++++++++++++++++++---------
1 file changed, 115 insertions(+), 46 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
index 661ce4d70e4f..c06ba467b1ee 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -455,6 +455,35 @@ static void intel_cqm_stable(void *arg)
}
}
+/*
+ * If we have group events waiting for an RMID that don't conflict with
+ * events already running, assign @rmid.
+ */
+static bool intel_cqm_sched_in_event(unsigned int rmid)
+{
+ struct perf_event *leader, *event;
+
+ lockdep_assert_held(&cache_mutex);
+
+ leader = list_first_entry(&cache_groups, struct perf_event,
+ hw.cqm_groups_entry);
+ event = leader;
+
+ list_for_each_entry_continue(event, &cache_groups,
+ hw.cqm_groups_entry) {
+ if (__rmid_valid(event->hw.cqm_rmid))
+ continue;
+
+ if (__conflict_event(event, leader))
+ continue;
+
+ intel_cqm_xchg_rmid(event, rmid);
+ return true;
+ }
+
+ return false;
+}
+
static unsigned int __rotation_period = 250; /* ms */
/*
@@ -480,7 +509,6 @@ static bool intel_cqm_rmid_stabilize(bool *available)
{
struct cqm_rmid_entry *entry;
unsigned int nr_bits;
- struct perf_event *event;
lockdep_assert_held(&cache_mutex);
@@ -554,19 +582,9 @@ static bool intel_cqm_rmid_stabilize(bool *available)
/*
* If we have groups waiting for RMIDs, hand
- * them one now.
+ * them one now provided they don't conflict.
*/
- list_for_each_entry(event, &cache_groups,
- hw.cqm_groups_entry) {
- if (__rmid_valid(event->hw.cqm_rmid))
- continue;
-
- intel_cqm_xchg_rmid(event, i);
- entry = NULL;
- break;
- }
-
- if (!entry)
+ if (intel_cqm_sched_in_event(i))
continue;
/*
@@ -581,25 +599,75 @@ static bool intel_cqm_rmid_stabilize(bool *available)
/*
* Pick a victim group and move it to the tail of the group list.
+ * @next: The first group without an RMID
*/
-static struct perf_event *
-__intel_cqm_pick_and_rotate(void)
+static void __intel_cqm_pick_and_rotate(struct perf_event *next)
{
struct perf_event *rotor;
+ unsigned int rmid;
lockdep_assert_held(&cache_mutex);
- lockdep_assert_held(&cache_lock);
rotor = list_first_entry(&cache_groups, struct perf_event,
hw.cqm_groups_entry);
+
+ /*
+ * The group at the front of the list should always have a valid
+ * RMID. If it doesn't then no groups have RMIDs assigned and we
+ * don't need to rotate the list.
+ */
+ if (next == rotor)
+ return;
+
+ rmid = intel_cqm_xchg_rmid(rotor, INVALID_RMID);
+ __put_rmid(rmid);
+
list_rotate_left(&cache_groups);
+}
- return rotor;
+/*
+ * Deallocate the RMIDs from any events that conflict with @event, and
+ * place them on the back of the group list.
+ */
+static void intel_cqm_sched_out_events(struct perf_event *event)
+{
+ struct perf_event *group, *g;
+ unsigned int rmid;
+
+ lockdep_assert_held(&cache_mutex);
+
+ list_for_each_entry_safe(group, g, &cache_groups, hw.cqm_groups_entry) {
+ if (group == event)
+ continue;
+
+ rmid = group->hw.cqm_rmid;
+
+ /*
+ * Skip events that don't have a valid RMID.
+ */
+ if (!__rmid_valid(rmid))
+ continue;
+
+ /*
+ * No conflict? No problem! Leave the event alone.
+ */
+ if (!__conflict_event(group, event))
+ continue;
+
+ intel_cqm_xchg_rmid(group, INVALID_RMID);
+ __put_rmid(rmid);
+
+ list_move_tail(&group->hw.cqm_groups_entry, &cache_groups);
+ }
}
/*
* Attempt to rotate the groups and assign new RMIDs.
*
+ * We rotate for two reasons,
+ * 1. To handle the scheduling of conflicting events
+ * 2. To recycle RMIDs
+ *
* Rotating RMIDs is complicated because the hardware doesn't give us
* any clues.
*
@@ -619,9 +687,8 @@ __intel_cqm_pick_and_rotate(void)
*/
static bool __intel_cqm_rmid_rotate(void)
{
- struct perf_event *group, *rotor, *start = NULL;
+ struct perf_event *group, *start = NULL;
unsigned int nr_needed = 0;
- unsigned int rmid;
bool rotated = false;
bool available;
@@ -654,7 +721,9 @@ again:
goto stabilize;
/*
- * We have more event groups without RMIDs than available RMIDs.
+ * We have more event groups without RMIDs than available RMIDs,
+ * or we have event groups that conflict with the ones currently
+ * scheduled.
*
* We force deallocate the rmid of the group at the head of
* cache_groups. The first event group without an RMID then gets
@@ -664,15 +733,7 @@ again:
* Rotate the cache_groups list so the previous head is now the
* tail.
*/
- rotor = __intel_cqm_pick_and_rotate();
- rmid = intel_cqm_xchg_rmid(rotor, INVALID_RMID);
-
- /*
- * The group at the front of the list should always have a valid
- * RMID. If it doesn't then no groups have RMIDs assigned.
- */
- if (!__rmid_valid(rmid))
- goto stabilize;
+ __intel_cqm_pick_and_rotate(start);
/*
* If the rotation is going to succeed, reduce the threshold so
@@ -680,14 +741,14 @@ again:
*/
if (__rmid_valid(intel_cqm_rotation_rmid)) {
intel_cqm_xchg_rmid(start, intel_cqm_rotation_rmid);
- intel_cqm_rotation_rmid = INVALID_RMID;
+ intel_cqm_rotation_rmid = __get_rmid();
+
+ intel_cqm_sched_out_events(start);
if (__intel_cqm_threshold)
__intel_cqm_threshold--;
}
- __put_rmid(rmid);
-
rotated = true;
stabilize:
@@ -731,25 +792,37 @@ static void intel_cqm_rmid_rotate(struct work_struct *work)
*
* If we're part of a group, we use the group's RMID.
*/
-static int intel_cqm_setup_event(struct perf_event *event,
- struct perf_event **group)
+static void intel_cqm_setup_event(struct perf_event *event,
+ struct perf_event **group)
{
struct perf_event *iter;
+ unsigned int rmid;
+ bool conflict = false;
list_for_each_entry(iter, &cache_groups, hw.cqm_groups_entry) {
+ rmid = iter->hw.cqm_rmid;
+
if (__match_event(iter, event)) {
/* All tasks in a group share an RMID */
- event->hw.cqm_rmid = iter->hw.cqm_rmid;
+ event->hw.cqm_rmid = rmid;
*group = iter;
- return 0;
+ return;
}
- if (__conflict_event(iter, event))
- return -EBUSY;
+ /*
+ * We only care about conflicts for events that are
+ * actually scheduled in (and hence have a valid RMID).
+ */
+ if (__conflict_event(iter, event) && __rmid_valid(rmid))
+ conflict = true;
}
- event->hw.cqm_rmid = __get_rmid();
- return 0;
+ if (conflict)
+ rmid = INVALID_RMID;
+ else
+ rmid = __get_rmid();
+
+ event->hw.cqm_rmid = rmid;
}
static void intel_cqm_event_read(struct perf_event *event)
@@ -971,7 +1044,6 @@ static int intel_cqm_event_init(struct perf_event *event)
{
struct perf_event *group = NULL;
bool rotate = false;
- int err;
if (event->attr.type != intel_cqm_pmu.type)
return -ENOENT;
@@ -997,9 +1069,7 @@ static int intel_cqm_event_init(struct perf_event *event)
mutex_lock(&cache_mutex);
/* Will also set rmid */
- err = intel_cqm_setup_event(event, &group);
- if (err)
- goto out;
+ intel_cqm_setup_event(event, &group);
if (group) {
list_add_tail(&event->hw.cqm_group_entry,
@@ -1019,13 +1089,12 @@ static int intel_cqm_event_init(struct perf_event *event)
rotate = true;
}
-out:
mutex_unlock(&cache_mutex);
if (rotate)
schedule_delayed_work(&intel_cqm_rmid_work, 0);
- return err;
+ return 0;
}
EVENT_ATTR_STR(llc_occupancy, intel_cqm_llc, "event=0x01");
--
1.9.3
From: Matt Fleming <[email protected]>
It's possible to run into issues with re-using unused monitoring IDs
because there may be stale cachelines associated with that ID from a
previous allocation. This can cause the LLC occupancy values to be
inaccurate.
To attempt to mitigate this problem we place the IDs on a least recently
used list, essentially a FIFO. The basic idea is that the longer the
time period between ID re-use the lower the probability that stale
cachelines exist in the cache.
Cc: Jiri Olsa <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Signed-off-by: Matt Fleming <[email protected]>
---
arch/x86/kernel/cpu/perf_event_intel_cqm.c | 100 ++++++++++++++++++++++++++---
1 file changed, 92 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
index b16458ff274e..60e0043ca922 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -25,7 +25,7 @@ struct intel_cqm_state {
static DEFINE_PER_CPU(struct intel_cqm_state, cqm_state);
/*
- * Protects cache_cgroups.
+ * Protects cache_cgroups and cqm_rmid_lru.
*/
static DEFINE_MUTEX(cache_mutex);
@@ -64,36 +64,120 @@ static u64 __rmid_read(unsigned long rmid)
return val;
}
-static unsigned long *cqm_rmid_bitmap;
+struct cqm_rmid_entry {
+ u64 rmid;
+ struct list_head list;
+};
+
+/*
+ * A least recently used list of RMIDs.
+ *
+ * Oldest entry at the head, newest (most recently used) entry at the
+ * tail. This list is never traversed, it's only used to keep track of
+ * the lru order. That is, we only pick entries of the head or insert
+ * them on the tail.
+ *
+ * All entries on the list are 'free', and their RMIDs are not currently
+ * in use. To mark an RMID as in use, remove its entry from the lru
+ * list.
+ *
+ * This list is protected by cache_mutex.
+ */
+static LIST_HEAD(cqm_rmid_lru);
+
+/*
+ * We use a simple array of pointers so that we can lookup a struct
+ * cqm_rmid_entry in O(1). This alleviates the callers of __get_rmid()
+ * and __put_rmid() from having to worry about dealing with struct
+ * cqm_rmid_entry - they just deal with rmids, i.e. integers.
+ *
+ * Once this array is initialized it is read-only. No locks are required
+ * to access it.
+ *
+ * All entries for all RMIDs can be looked up in the this array at all
+ * times.
+ */
+static struct cqm_rmid_entry **cqm_rmid_ptrs;
+
+static inline struct cqm_rmid_entry *__rmid_entry(int rmid)
+{
+ struct cqm_rmid_entry *entry;
+
+ entry = cqm_rmid_ptrs[rmid];
+ WARN_ON(entry->rmid != rmid);
+
+ return entry;
+}
/*
* Returns < 0 on fail.
+ *
+ * We expect to be called with cache_mutex held.
*/
static int __get_rmid(void)
{
- return bitmap_find_free_region(cqm_rmid_bitmap, cqm_max_rmid, 0);
+ struct cqm_rmid_entry *entry;
+
+ lockdep_assert_held(&cache_mutex);
+
+ if (list_empty(&cqm_rmid_lru))
+ return -EAGAIN;
+
+ entry = list_first_entry(&cqm_rmid_lru, struct cqm_rmid_entry, list);
+ list_del(&entry->list);
+
+ return entry->rmid;
}
static void __put_rmid(int rmid)
{
- bitmap_release_region(cqm_rmid_bitmap, rmid, 0);
+ struct cqm_rmid_entry *entry;
+
+ lockdep_assert_held(&cache_mutex);
+
+ entry = __rmid_entry(rmid);
+
+ list_add_tail(&entry->list, &cqm_rmid_lru);
}
static int intel_cqm_setup_rmid_cache(void)
{
- cqm_rmid_bitmap = kmalloc(sizeof(long) * BITS_TO_LONGS(cqm_max_rmid), GFP_KERNEL);
- if (!cqm_rmid_bitmap)
+ struct cqm_rmid_entry *entry;
+ int r;
+
+ cqm_rmid_ptrs = kmalloc(sizeof(struct cqm_rmid_entry *) *
+ (cqm_max_rmid + 1), GFP_KERNEL);
+ if (!cqm_rmid_ptrs)
return -ENOMEM;
- bitmap_zero(cqm_rmid_bitmap, cqm_max_rmid);
+ for (r = 0; r <= cqm_max_rmid; r++) {
+ struct cqm_rmid_entry *entry;
+
+ entry = kmalloc(sizeof(*entry), GFP_KERNEL);
+ if (!entry)
+ goto fail;
+
+ INIT_LIST_HEAD(&entry->list);
+ entry->rmid = r;
+ cqm_rmid_ptrs[r] = entry;
+
+ list_add_tail(&entry->list, &cqm_rmid_lru);
+ }
/*
* RMID 0 is special and is always allocated. It's used for all
* tasks that are not monitored.
*/
- bitmap_allocate_region(cqm_rmid_bitmap, 0, 0);
+ entry = __rmid_entry(0);
+ list_del(&entry->list);
return 0;
+fail:
+ while (r--)
+ kfree(cqm_rmid_ptrs[r]);
+
+ kfree(cqm_rmid_ptrs);
+ return -ENOMEM;
}
/*
--
1.9.3
From: Matt Fleming <[email protected]>
The Intel QoS PMU needs to know whether an event is part of a cgroup
during ->event_init(), because tasks in the same cgroup share a
monitoring ID.
Move the cgroup initialisation before calling into the PMU driver.
Cc: Jiri Olsa <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Signed-off-by: Matt Fleming <[email protected]>
---
Changes in v3:
- Only use 'int cgroup_fd' to pass cgroup file descriptor instead of
'bool cgroup, pid_t cgroup_fd'
kernel/events/core.c | 28 ++++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/kernel/events/core.c b/kernel/events/core.c
index a2ea4a52dbbf..540d995322dd 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -6884,7 +6884,7 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu,
struct perf_event *group_leader,
struct perf_event *parent_event,
perf_overflow_handler_t overflow_handler,
- void *context)
+ void *context, int cgroup_fd)
{
struct pmu *pmu;
struct perf_event *event;
@@ -6977,6 +6977,12 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu,
if (attr->inherit && (attr->read_format & PERF_FORMAT_GROUP))
goto err_ns;
+ if (cgroup_fd != -1) {
+ err = perf_cgroup_connect(cgroup_fd, event, attr, group_leader);
+ if (err)
+ goto err_ns;
+ }
+
pmu = perf_init_event(event);
if (!pmu)
goto err_ns;
@@ -7000,6 +7006,8 @@ err_pmu:
event->destroy(event);
module_put(pmu->module);
err_ns:
+ if (is_cgroup_event(event))
+ perf_detach_cgroup(event);
if (event->ns)
put_pid_ns(event->ns);
kfree(event);
@@ -7207,6 +7215,7 @@ SYSCALL_DEFINE5(perf_event_open,
int move_group = 0;
int err;
int f_flags = O_RDWR;
+ int cgroup_fd = -1;
/* for future expandability... */
if (flags & ~PERF_FLAG_ALL)
@@ -7272,21 +7281,16 @@ SYSCALL_DEFINE5(perf_event_open,
get_online_cpus();
+ if (flags & PERF_FLAG_PID_CGROUP)
+ cgroup_fd = pid;
+
event = perf_event_alloc(&attr, cpu, task, group_leader, NULL,
- NULL, NULL);
+ NULL, NULL, cgroup_fd);
if (IS_ERR(event)) {
err = PTR_ERR(event);
goto err_cpus;
}
- if (flags & PERF_FLAG_PID_CGROUP) {
- err = perf_cgroup_connect(pid, event, &attr, group_leader);
- if (err) {
- __free_event(event);
- goto err_cpus;
- }
- }
-
if (is_sampling_event(event)) {
if (event->pmu->capabilities & PERF_PMU_CAP_NO_INTERRUPT) {
err = -ENOTSUPP;
@@ -7486,7 +7490,7 @@ perf_event_create_kernel_counter(struct perf_event_attr *attr, int cpu,
*/
event = perf_event_alloc(attr, cpu, task, NULL, NULL,
- overflow_handler, context);
+ overflow_handler, context, -1);
if (IS_ERR(event)) {
err = PTR_ERR(event);
goto err;
@@ -7812,7 +7816,7 @@ inherit_event(struct perf_event *parent_event,
parent_event->cpu,
child,
group_leader, parent_event,
- NULL, NULL);
+ NULL, NULL, -1);
if (IS_ERR(child_event))
return child_event;
--
1.9.3
From: Matt Fleming <[email protected]>
Move perf_cgroup_from_task() from kernel/events/ to include/linux/ along
with the necessary struct definitions, so that it can be used by the PMU
code.
When the upcoming Intel Cache Monitoring PMU driver assigns monitoring
IDs to perf events, it needs to be able to check whether any two
monitoring events overlap (say, a cgroup and task event), which means we
need to be able to lookup the cgroup associated with a task (if any).
Cc: Jiri Olsa <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Signed-off-by: Matt Fleming <[email protected]>
---
include/linux/perf_event.h | 30 ++++++++++++++++++++++++++++++
kernel/events/core.c | 28 +---------------------------
2 files changed, 31 insertions(+), 27 deletions(-)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 893a0d07986f..1a4e2846d6fb 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -53,6 +53,7 @@ struct perf_guest_info_callbacks {
#include <linux/sysfs.h>
#include <linux/perf_regs.h>
#include <linux/workqueue.h>
+#include <linux/cgroup.h>
#include <asm/local.h>
struct perf_callchain_entry {
@@ -544,6 +545,35 @@ struct perf_output_handle {
int page;
};
+#ifdef CONFIG_CGROUP_PERF
+
+/*
+ * perf_cgroup_info keeps track of time_enabled for a cgroup.
+ * This is a per-cpu dynamically allocated data structure.
+ */
+struct perf_cgroup_info {
+ u64 time;
+ u64 timestamp;
+};
+
+struct perf_cgroup {
+ struct cgroup_subsys_state css;
+ struct perf_cgroup_info __percpu *info;
+};
+
+/*
+ * Must ensure cgroup is pinned (css_get) before calling
+ * this function. In other words, we cannot call this function
+ * if there is no cgroup event for the current CPU context.
+ */
+static inline struct perf_cgroup *
+perf_cgroup_from_task(struct task_struct *task)
+{
+ return container_of(task_css(task, perf_event_cgrp_id),
+ struct perf_cgroup, css);
+}
+#endif /* CONFIG_CGROUP_PERF */
+
#ifdef CONFIG_PERF_EVENTS
extern int perf_pmu_register(struct pmu *pmu, const char *name, int type);
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 2b02c9fda790..a65f4c47eb56 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -34,11 +34,11 @@
#include <linux/syscalls.h>
#include <linux/anon_inodes.h>
#include <linux/kernel_stat.h>
+#include <linux/cgroup.h>
#include <linux/perf_event.h>
#include <linux/ftrace_event.h>
#include <linux/hw_breakpoint.h>
#include <linux/mm_types.h>
-#include <linux/cgroup.h>
#include <linux/module.h>
#include <linux/mman.h>
#include <linux/compat.h>
@@ -351,32 +351,6 @@ static void perf_ctx_unlock(struct perf_cpu_context *cpuctx,
#ifdef CONFIG_CGROUP_PERF
-/*
- * perf_cgroup_info keeps track of time_enabled for a cgroup.
- * This is a per-cpu dynamically allocated data structure.
- */
-struct perf_cgroup_info {
- u64 time;
- u64 timestamp;
-};
-
-struct perf_cgroup {
- struct cgroup_subsys_state css;
- struct perf_cgroup_info __percpu *info;
-};
-
-/*
- * Must ensure cgroup is pinned (css_get) before calling
- * this function. In other words, we cannot call this function
- * if there is no cgroup event for the current CPU context.
- */
-static inline struct perf_cgroup *
-perf_cgroup_from_task(struct task_struct *task)
-{
- return container_of(task_css(task, perf_event_cgrp_id),
- struct perf_cgroup, css);
-}
-
static inline bool
perf_cgroup_match(struct perf_event *event)
{
--
1.9.3
From: Matt Fleming <[email protected]>
In preparation for upcoming PMU drivers that support system-wide,
per-package counters and hence report duplicate values, add support for
parsing the .per-pkg file.
An event can export this info file to indicate that all but one value
per socket should be discarded.
The discarding is much easier to do in userspace than inside the kernel
because the kernel cannot infer what userspace is going to do with the
reported values, what order it will read them in, etc.
Cc: Jiri Olsa <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Signed-off-by: Matt Fleming <[email protected]>
---
tools/perf/builtin-stat.c | 88 +++++++++++++++++++++++++++++++++++++++++-
tools/perf/util/evsel.c | 6 ++-
tools/perf/util/evsel.h | 8 ++--
tools/perf/util/parse-events.c | 1 +
tools/perf/util/pmu.c | 27 +++++++++++++
tools/perf/util/pmu.h | 2 +
6 files changed, 127 insertions(+), 5 deletions(-)
diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c
index 055ce9232c9e..fa5264668187 100644
--- a/tools/perf/builtin-stat.c
+++ b/tools/perf/builtin-stat.c
@@ -389,17 +389,92 @@ static void update_shadow_stats(struct perf_evsel *counter, u64 *count)
}
/*
+ * If 'evsel' is a per-socket event we may get duplicate values
+ * reported. We need to discard all but one per-socket value.
+ */
+static bool counter_per_socket_skip(struct perf_evsel *evsel, int cpu, u64 val)
+{
+ struct cpu_map *map;
+ int i, ncpus;
+ int s1, s2;
+
+ if (!evsel->system_wide)
+ return false;
+
+ map = perf_evsel__cpus(evsel);
+ ncpus = map->nr;
+
+ s1 = cpu_map__get_socket(evsel_list->cpus, map->map[cpu]);
+
+ /*
+ * Read all CPUs for this socket and see if any already have
+ * value assigned.
+ */
+ for (i = 0; i < ncpus; i++) {
+ s2 = cpu_map__get_socket(evsel_list->cpus, map->map[i]);
+ if (s1 != s2)
+ continue;
+
+ if (evsel->counts->cpu[i].val)
+ return true;
+ }
+
+ /* Stash the counter value in unused ->counts */
+ evsel->counts->cpu[cpu].val = val;
+ return false;
+}
+
+static bool aggr_per_socket_skip(struct perf_evsel *evsel, int cpu)
+{
+ struct cpu_map *map;
+ int leader_cpu = -1;
+ int i, ncpus;
+ int s1, s2;
+
+ map = perf_evsel__cpus(evsel);
+ ncpus = map->nr;
+
+ s1 = cpu_map__get_socket(evsel_list->cpus, map->map[cpu]);
+
+ /*
+ * Find the first enabled counter for this socket and skip
+ * everything else.
+ */
+ for (i = 0; i < ncpus; i++) {
+ s2 = cpu_map__get_socket(evsel_list->cpus, map->map[i]);
+ if (s1 != s2)
+ continue;
+
+ if (!evsel->counts->cpu[i].ena)
+ continue;
+
+ leader_cpu = i;
+ break;
+ }
+
+ if (cpu == leader_cpu)
+ return false;
+
+ return true;
+}
+
+/*
* Read out the results of a single counter:
* aggregate counts across CPUs in system-wide mode
*/
static int read_counter_aggr(struct perf_evsel *counter)
{
struct perf_stat *ps = counter->priv;
+ bool (*f_skip)(struct perf_evsel *evsel, int cpu, u64 val) = NULL;
u64 *count = counter->counts->aggr.values;
int i;
+ if (counter->per_pkg)
+ f_skip = counter_per_socket_skip;
+
if (__perf_evsel__read(counter, perf_evsel__nr_cpus(counter),
- thread_map__nr(evsel_list->threads), scale) < 0)
+ thread_map__nr(evsel_list->threads),
+ scale, f_skip) < 0)
return -1;
for (i = 0; i < 3; i++)
@@ -451,12 +526,18 @@ static void print_interval(void)
evlist__for_each(evsel_list, counter) {
ps = counter->priv;
memset(ps->res_stats, 0, sizeof(ps->res_stats));
+ memset(counter->counts->cpu, 0,
+ sizeof(struct perf_counts_values) *
+ perf_evsel__nr_cpus(counter));
read_counter_aggr(counter);
}
} else {
evlist__for_each(evsel_list, counter) {
ps = counter->priv;
memset(ps->res_stats, 0, sizeof(ps->res_stats));
+ memset(counter->counts->cpu, 0,
+ sizeof(struct perf_counts_values) *
+ perf_evsel__nr_cpus(counter));
read_counter(counter);
}
}
@@ -1130,6 +1211,11 @@ static void print_aggr(char *prefix)
val = ena = run = 0;
nr = 0;
for (cpu = 0; cpu < perf_evsel__nr_cpus(counter); cpu++) {
+ if (counter->per_pkg) {
+ if (aggr_per_socket_skip(counter, cpu))
+ continue;
+ }
+
cpu2 = perf_evsel__cpus(counter)->map[cpu];
s2 = aggr_get_id(evsel_list->cpus, cpu2);
if (s2 != id)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index 2f9e68025ede..a748e5e16533 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -917,7 +917,8 @@ int __perf_evsel__read_on_cpu(struct perf_evsel *evsel,
}
int __perf_evsel__read(struct perf_evsel *evsel,
- int ncpus, int nthreads, bool scale)
+ int ncpus, int nthreads, bool scale,
+ bool (*f_skip)(struct perf_evsel *evsel, int cpu, u64 val))
{
size_t nv = scale ? 3 : 1;
int cpu, thread;
@@ -937,6 +938,9 @@ int __perf_evsel__read(struct perf_evsel *evsel,
&count, nv * sizeof(u64)) < 0)
return -errno;
+ if (f_skip && f_skip(evsel, cpu, count.val))
+ continue;
+
aggr->val += count.val;
if (scale) {
aggr->ena += count.ena;
diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h
index 979790951bfb..13ca8a7693e4 100644
--- a/tools/perf/util/evsel.h
+++ b/tools/perf/util/evsel.h
@@ -91,6 +91,7 @@ struct perf_evsel {
bool immediate;
bool system_wide;
bool tracking;
+ bool per_pkg;
/* parse modifier helper */
int exclude_GH;
int nr_members;
@@ -257,7 +258,8 @@ static inline int perf_evsel__read_on_cpu_scaled(struct perf_evsel *evsel,
}
int __perf_evsel__read(struct perf_evsel *evsel, int ncpus, int nthreads,
- bool scale);
+ bool scale,
+ bool (*f_skip)(struct perf_evsel *evsel, int cpu, u64 val));
/**
* perf_evsel__read - Read the aggregate results on all CPUs
@@ -269,7 +271,7 @@ int __perf_evsel__read(struct perf_evsel *evsel, int ncpus, int nthreads,
static inline int perf_evsel__read(struct perf_evsel *evsel,
int ncpus, int nthreads)
{
- return __perf_evsel__read(evsel, ncpus, nthreads, false);
+ return __perf_evsel__read(evsel, ncpus, nthreads, false, NULL);
}
/**
@@ -282,7 +284,7 @@ static inline int perf_evsel__read(struct perf_evsel *evsel,
static inline int perf_evsel__read_scaled(struct perf_evsel *evsel,
int ncpus, int nthreads)
{
- return __perf_evsel__read(evsel, ncpus, nthreads, true);
+ return __perf_evsel__read(evsel, ncpus, nthreads, true, NULL);
}
int perf_evsel__parse_sample(struct perf_evsel *evsel, union perf_event *event,
diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
index c659a3ca1283..5a373483f0e4 100644
--- a/tools/perf/util/parse-events.c
+++ b/tools/perf/util/parse-events.c
@@ -681,6 +681,7 @@ int parse_events_add_pmu(struct list_head *list, int *idx,
if (evsel) {
evsel->unit = info.unit;
evsel->scale = info.scale;
+ evsel->per_pkg = info.per_pkg;
}
return evsel ? 0 : -ENOMEM;
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index 881b75490533..f003b5a9e059 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -163,6 +163,24 @@ error:
return -1;
}
+static int
+perf_pmu__parse_per_pkg(struct perf_pmu_alias *alias, char *dir, char *name)
+{
+ char path[PATH_MAX];
+ int fd;
+
+ snprintf(path, PATH_MAX, "%s/%s.per-pkg", dir, name);
+
+ fd = open(path, O_RDONLY);
+ if (fd == -1)
+ return -1;
+
+ close(fd);
+
+ alias->per_pkg = true;
+ return 0;
+}
+
static int perf_pmu__new_alias(struct list_head *list, char *dir, char *name, FILE *file)
{
struct perf_pmu_alias *alias;
@@ -181,6 +199,7 @@ static int perf_pmu__new_alias(struct list_head *list, char *dir, char *name, FI
INIT_LIST_HEAD(&alias->terms);
alias->scale = 1.0;
alias->unit[0] = '\0';
+ alias->per_pkg = false;
ret = parse_events_terms(&alias->terms, buf);
if (ret) {
@@ -194,6 +213,7 @@ static int perf_pmu__new_alias(struct list_head *list, char *dir, char *name, FI
*/
perf_pmu__parse_unit(alias, dir, name);
perf_pmu__parse_scale(alias, dir, name);
+ perf_pmu__parse_per_pkg(alias, dir, name);
list_add_tail(&alias->list, list);
@@ -209,6 +229,8 @@ static inline bool pmu_alias_info_file(char *name)
return true;
if (len > 6 && !strcmp(name + len - 6, ".scale"))
return true;
+ if (len > 8 && !strcmp(name + len - 8, ".per-pkg"))
+ return true;
return false;
}
@@ -649,6 +671,8 @@ int perf_pmu__check_alias(struct perf_pmu *pmu, struct list_head *head_terms,
struct perf_pmu_alias *alias;
int ret;
+ info->per_pkg = false;
+
/*
* Mark unit and scale as not set
* (different from default values, see below)
@@ -668,6 +692,9 @@ int perf_pmu__check_alias(struct perf_pmu *pmu, struct list_head *head_terms,
if (ret)
return ret;
+ if (alias->per_pkg)
+ info->per_pkg = true;
+
list_del(&term->list);
free(term);
}
diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h
index 8092de78e818..c3a74e0e17a2 100644
--- a/tools/perf/util/pmu.h
+++ b/tools/perf/util/pmu.h
@@ -29,6 +29,7 @@ struct perf_pmu {
struct perf_pmu_info {
const char *unit;
double scale;
+ bool per_pkg;
};
#define UNIT_MAX_LEN 31 /* max length for event unit name */
@@ -39,6 +40,7 @@ struct perf_pmu_alias {
struct list_head list; /* ELEM */
char unit[UNIT_MAX_LEN+1];
double scale;
+ bool per_pkg;
};
struct perf_pmu *perf_pmu__find(const char *name);
--
1.9.3
From: Matt Fleming <[email protected]>
Future Intel Xeon processors support a Cache QoS Monitoring feature that
allows tracking of the LLC occupancy for a task or task group, i.e. the
amount of data in pulled into the LLC for the task (group).
Currently the PMU only supports per-cpu events. We create an event for
each cpu and read out all the LLC occupancy values.
Because this results in duplicate values being written out to userspace,
we also export a .per-pkg event file so that the perf tools only
accumulate values for one cpu per package.
Cc: Jiri Olsa <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Signed-off-by: Matt Fleming <[email protected]>
---
Changes in v3:
- Export bytes and scale attributes for use by perf tools
- Wire up 'snapshot' attribute to support perf stat -I
Changes in v2:
- Use x86_match_cpu() to detect cpu feature.
- Grab the hotplug lock while we traverse the online cpumask in
intel_cqm_init().
arch/x86/kernel/cpu/Makefile | 2 +-
arch/x86/kernel/cpu/perf_event_intel_cqm.c | 528 +++++++++++++++++++++++++++++
include/linux/perf_event.h | 7 +
3 files changed, 536 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/kernel/cpu/perf_event_intel_cqm.c
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index e27b49d7c922..18e5341bb3fd 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -39,7 +39,7 @@ obj-$(CONFIG_CPU_SUP_AMD) += perf_event_amd_iommu.o
endif
obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_p6.o perf_event_knc.o perf_event_p4.o
obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o
-obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_rapl.o
+obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_rapl.o perf_event_intel_cqm.o
obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) += perf_event_intel_uncore.o \
perf_event_intel_uncore_snb.o \
diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
new file mode 100644
index 000000000000..b16458ff274e
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -0,0 +1,528 @@
+/*
+ * Intel Cache Quality-of-Service Monitoring (CQM) support.
+ *
+ * Based very, very heavily on work by Peter Zijlstra.
+ */
+
+#include <linux/perf_event.h>
+#include <linux/slab.h>
+#include <asm/cpu_device_id.h>
+#include "perf_event.h"
+
+#define MSR_IA32_PQR_ASSOC 0x0c8f
+#define MSR_IA32_QM_CTR 0x0c8e
+#define MSR_IA32_QM_EVTSEL 0x0c8d
+
+static unsigned int cqm_max_rmid = -1;
+static unsigned int cqm_l3_scale; /* supposedly cacheline size */
+
+struct intel_cqm_state {
+ raw_spinlock_t lock;
+ int rmid;
+ int cnt;
+};
+
+static DEFINE_PER_CPU(struct intel_cqm_state, cqm_state);
+
+/*
+ * Protects cache_cgroups.
+ */
+static DEFINE_MUTEX(cache_mutex);
+
+/*
+ * Groups of events that have the same target(s), one RMID per group.
+ */
+static LIST_HEAD(cache_groups);
+
+/*
+ * Mask of CPUs for reading CQM values. We only need one per-socket.
+ */
+static cpumask_t cqm_cpumask;
+
+#define RMID_VAL_ERROR (1ULL << 63)
+#define RMID_VAL_UNAVAIL (1ULL << 62)
+
+#define QOS_L3_OCCUP_EVENT_ID (1 << 0)
+
+#define QOS_EVENT_MASK QOS_L3_OCCUP_EVENT_ID
+
+static u64 __rmid_read(unsigned long rmid)
+{
+ u64 val;
+
+ /*
+ * Ignore the SDM, this thing is _NOTHING_ like a regular perfcnt,
+ * it just says that to increase confusion.
+ */
+ wrmsr(MSR_IA32_QM_EVTSEL, QOS_L3_OCCUP_EVENT_ID, rmid);
+ rdmsrl(MSR_IA32_QM_CTR, val);
+
+ /*
+ * Aside from the ERROR and UNAVAIL bits, assume this thing returns
+ * the number of cachelines tagged with @rmid.
+ */
+ return val;
+}
+
+static unsigned long *cqm_rmid_bitmap;
+
+/*
+ * Returns < 0 on fail.
+ */
+static int __get_rmid(void)
+{
+ return bitmap_find_free_region(cqm_rmid_bitmap, cqm_max_rmid, 0);
+}
+
+static void __put_rmid(int rmid)
+{
+ bitmap_release_region(cqm_rmid_bitmap, rmid, 0);
+}
+
+static int intel_cqm_setup_rmid_cache(void)
+{
+ cqm_rmid_bitmap = kmalloc(sizeof(long) * BITS_TO_LONGS(cqm_max_rmid), GFP_KERNEL);
+ if (!cqm_rmid_bitmap)
+ return -ENOMEM;
+
+ bitmap_zero(cqm_rmid_bitmap, cqm_max_rmid);
+
+ /*
+ * RMID 0 is special and is always allocated. It's used for all
+ * tasks that are not monitored.
+ */
+ bitmap_allocate_region(cqm_rmid_bitmap, 0, 0);
+
+ return 0;
+}
+
+/*
+ * Determine if @a and @b measure the same set of tasks.
+ */
+static bool __match_event(struct perf_event *a, struct perf_event *b)
+{
+ if ((a->attach_state & PERF_ATTACH_TASK) !=
+ (b->attach_state & PERF_ATTACH_TASK))
+ return false;
+
+ /* not task */
+
+ return true; /* if not task, we're machine wide */
+}
+
+/*
+ * Determine if @a's tasks intersect with @b's tasks
+ */
+static bool __conflict_event(struct perf_event *a, struct perf_event *b)
+{
+ /*
+ * If one of them is not a task, same story as above with cgroups.
+ */
+ if (!(a->attach_state & PERF_ATTACH_TASK) ||
+ !(b->attach_state & PERF_ATTACH_TASK))
+ return true;
+
+ /*
+ * Must be non-overlapping.
+ */
+ return false;
+}
+
+/*
+ * Find a group and setup RMID.
+ *
+ * If we're part of a group, we use the group's RMID.
+ */
+static int intel_cqm_setup_event(struct perf_event *event,
+ struct perf_event **group)
+{
+ struct perf_event *iter;
+ int rmid;
+
+ list_for_each_entry(iter, &cache_groups, hw.cqm_groups_entry) {
+ if (__match_event(iter, event)) {
+ /* All tasks in a group share an RMID */
+ event->hw.cqm_rmid = iter->hw.cqm_rmid;
+ *group = iter;
+ return 0;
+ }
+
+ if (__conflict_event(iter, event))
+ return -EBUSY;
+ }
+
+ rmid = __get_rmid();
+ if (rmid < 0)
+ return rmid;
+
+ event->hw.cqm_rmid = rmid;
+ return 0;
+}
+
+static void intel_cqm_event_read(struct perf_event *event)
+{
+ unsigned long rmid = event->hw.cqm_rmid;
+ u64 val;
+
+ val = __rmid_read(rmid);
+
+ /*
+ * Ignore this reading on error states and do not update the value.
+ */
+ if (val & (RMID_VAL_ERROR | RMID_VAL_UNAVAIL))
+ return;
+
+ local64_set(&event->count, val);
+}
+
+static void intel_cqm_event_start(struct perf_event *event, int mode)
+{
+ struct intel_cqm_state *state = &__get_cpu_var(cqm_state);
+ unsigned long rmid = event->hw.cqm_rmid;
+ unsigned long flags;
+
+ if (!(event->hw.cqm_state & PERF_HES_STOPPED))
+ return;
+
+ event->hw.cqm_state &= ~PERF_HES_STOPPED;
+
+ raw_spin_lock_irqsave(&state->lock, flags);
+
+ if (state->cnt++)
+ WARN_ON_ONCE(state->rmid != rmid);
+ else
+ WARN_ON_ONCE(state->rmid);
+
+ state->rmid = rmid;
+ wrmsrl(MSR_IA32_PQR_ASSOC, state->rmid);
+
+ raw_spin_unlock_irqrestore(&state->lock, flags);
+}
+
+static void intel_cqm_event_stop(struct perf_event *event, int mode)
+{
+ struct intel_cqm_state *state = &__get_cpu_var(cqm_state);
+ unsigned long flags;
+
+ if (event->hw.cqm_state & PERF_HES_STOPPED)
+ return;
+
+ event->hw.cqm_state |= PERF_HES_STOPPED;
+
+ raw_spin_lock_irqsave(&state->lock, flags);
+ intel_cqm_event_read(event);
+
+ if (!--state->cnt) {
+ state->rmid = 0;
+ wrmsrl(MSR_IA32_PQR_ASSOC, 0);
+ } else {
+ WARN_ON_ONCE(!state->rmid);
+ }
+
+ raw_spin_unlock_irqrestore(&state->lock, flags);
+}
+
+static int intel_cqm_event_add(struct perf_event *event, int mode)
+{
+ int rmid;
+
+ event->hw.cqm_state = PERF_HES_STOPPED;
+ rmid = event->hw.cqm_rmid;
+ WARN_ON_ONCE(!rmid);
+
+ if (mode & PERF_EF_START)
+ intel_cqm_event_start(event, mode);
+
+ return 0;
+}
+
+static void intel_cqm_event_del(struct perf_event *event, int mode)
+{
+ intel_cqm_event_stop(event, mode);
+}
+
+static void intel_cqm_event_destroy(struct perf_event *event)
+{
+ struct perf_event *group_other = NULL;
+
+ mutex_lock(&cache_mutex);
+
+ /*
+ * If there's another event in this group...
+ */
+ if (!list_empty(&event->hw.cqm_group_entry)) {
+ group_other = list_first_entry(&event->hw.cqm_group_entry,
+ struct perf_event,
+ hw.cqm_group_entry);
+ list_del(&event->hw.cqm_group_entry);
+ }
+
+ /*
+ * And we're the group leader..
+ */
+ if (!list_empty(&event->hw.cqm_groups_entry)) {
+ /*
+ * If there was a group_other, make that leader, otherwise
+ * destroy the group and return the RMID.
+ */
+ if (group_other) {
+ list_replace(&event->hw.cqm_groups_entry,
+ &group_other->hw.cqm_groups_entry);
+ } else {
+ int rmid = event->hw.cqm_rmid;
+ __put_rmid(rmid);
+ list_del(&event->hw.cqm_groups_entry);
+ }
+ }
+
+ mutex_unlock(&cache_mutex);
+}
+
+static struct pmu intel_cqm_pmu;
+
+/*
+ * XXX there's a bit of a problem in that we cannot simply do the one
+ * event per node as one would want, since that one event would one get
+ * scheduled on the one cpu. But we want to 'schedule' the RMID on all
+ * CPUs.
+ *
+ * This means we want events for each CPU, however, that generates a lot
+ * of duplicate values out to userspace -- this is not to be helped
+ * unless we want to change the core code in some way. Fore more info,
+ * see intel_cqm_event_read().
+ */
+static int intel_cqm_event_init(struct perf_event *event)
+{
+ struct perf_event *group = NULL;
+ int err;
+
+ if (event->attr.type != intel_cqm_pmu.type)
+ return -ENOENT;
+
+ if (event->attr.config & ~QOS_EVENT_MASK)
+ return -EINVAL;
+
+ if (event->cpu == -1)
+ return -EINVAL;
+
+ /* unsupported modes and filters */
+ if (event->attr.exclude_user ||
+ event->attr.exclude_kernel ||
+ event->attr.exclude_hv ||
+ event->attr.exclude_idle ||
+ event->attr.exclude_host ||
+ event->attr.exclude_guest ||
+ event->attr.sample_period) /* no sampling */
+ return -EINVAL;
+
+ INIT_LIST_HEAD(&event->hw.cqm_group_entry);
+ INIT_LIST_HEAD(&event->hw.cqm_groups_entry);
+
+ event->destroy = intel_cqm_event_destroy;
+
+ mutex_lock(&cache_mutex);
+
+ err = intel_cqm_setup_event(event, &group); /* will also set rmid */
+ if (err)
+ goto out;
+
+ if (group) {
+ list_add_tail(&event->hw.cqm_group_entry,
+ &group->hw.cqm_group_entry);
+ } else {
+ list_add_tail(&event->hw.cqm_groups_entry,
+ &cache_groups);
+ }
+
+out:
+ mutex_unlock(&cache_mutex);
+ return err;
+}
+
+EVENT_ATTR_STR(llc_occupancy, intel_cqm_llc, "event=0x01");
+EVENT_ATTR_STR(llc_occupancy.per-pkg, intel_cqm_llc_pkg, "1");
+EVENT_ATTR_STR(llc_occupancy.unit, intel_cqm_llc_unit, "Bytes");
+EVENT_ATTR_STR(llc_occupancy.scale, intel_cqm_llc_scale, NULL);
+EVENT_ATTR_STR(llc_occupancy.snapshot, intel_cqm_llc_snapshot, "1");
+
+static struct attribute *intel_cqm_events_attr[] = {
+ EVENT_PTR(intel_cqm_llc),
+ EVENT_PTR(intel_cqm_llc_pkg),
+ EVENT_PTR(intel_cqm_llc_unit),
+ EVENT_PTR(intel_cqm_llc_scale),
+ EVENT_PTR(intel_cqm_llc_snapshot),
+ NULL,
+};
+
+static struct attribute_group intel_cqm_events_group = {
+ .name = "events",
+ .attrs = intel_cqm_events_attr,
+};
+
+PMU_FORMAT_ATTR(event, "config:0-7");
+static struct attribute *intel_cqm_formats_attr[] = {
+ &format_attr_event.attr,
+ NULL,
+};
+
+static struct attribute_group intel_cqm_format_group = {
+ .name = "format",
+ .attrs = intel_cqm_formats_attr,
+};
+
+static const struct attribute_group *intel_cqm_attr_groups[] = {
+ &intel_cqm_events_group,
+ &intel_cqm_format_group,
+ NULL,
+};
+
+static struct pmu intel_cqm_pmu = {
+ .attr_groups = intel_cqm_attr_groups,
+ .task_ctx_nr = perf_sw_context,
+ .event_init = intel_cqm_event_init,
+ .add = intel_cqm_event_add,
+ .del = intel_cqm_event_del,
+ .start = intel_cqm_event_start,
+ .stop = intel_cqm_event_stop,
+ .read = intel_cqm_event_read,
+};
+
+static inline void cqm_pick_event_reader(int cpu)
+{
+ int phys_id = topology_physical_package_id(cpu);
+ int i;
+
+ for_each_cpu(i, &cqm_cpumask) {
+ if (phys_id == topology_physical_package_id(i))
+ return; /* already got reader for this socket */
+ }
+
+ cpumask_set_cpu(cpu, &cqm_cpumask);
+}
+
+static void intel_cqm_cpu_prepare(unsigned int cpu)
+{
+ struct intel_cqm_state *state = &per_cpu(cqm_state, cpu);
+ struct cpuinfo_x86 *c = &cpu_data(cpu);
+
+ raw_spin_lock_init(&state->lock);
+ state->rmid = 0;
+
+ WARN_ON(c->x86_cache_max_rmid != cqm_max_rmid);
+ WARN_ON(c->x86_cache_occ_scale != cqm_l3_scale);
+}
+
+static void intel_cqm_cpu_exit(unsigned int cpu)
+{
+ int phys_id = topology_physical_package_id(cpu);
+ int i;
+
+ /*
+ * Is @cpu a designated cqm reader?
+ */
+ if (!cpumask_test_and_clear_cpu(cpu, &cqm_cpumask))
+ return;
+
+ for_each_online_cpu(i) {
+ if (i == cpu)
+ continue;
+
+ if (phys_id == topology_physical_package_id(i)) {
+ cpumask_set_cpu(i, &cqm_cpumask);
+ break;
+ }
+ }
+}
+
+static int intel_cqm_cpu_notifier(struct notifier_block *nb,
+ unsigned long action, void *hcpu)
+{
+ unsigned int cpu = (unsigned long)hcpu;
+
+ switch (action & ~CPU_TASKS_FROZEN) {
+ case CPU_UP_PREPARE:
+ intel_cqm_cpu_prepare(cpu);
+ break;
+ case CPU_DOWN_PREPARE:
+ intel_cqm_cpu_exit(cpu);
+ break;
+ case CPU_STARTING:
+ cqm_pick_event_reader(cpu);
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static const struct x86_cpu_id intel_cqm_match[] = {
+ { .vendor = X86_VENDOR_INTEL, .feature = X86_FEATURE_CQM_OCCUP_LLC },
+ {}
+};
+
+static int __init intel_cqm_init(void)
+{
+ char *str, scale[20];
+ int i, cpu, ret;
+
+ if (!x86_match_cpu(intel_cqm_match))
+ return -ENODEV;
+
+ cqm_l3_scale = boot_cpu_data.x86_cache_occ_scale;
+
+ /*
+ * It's possible that not all resources support the same number
+ * of RMIDs. Instead of making scheduling much more complicated
+ * (where we have to match a task's RMID to a cpu that supports
+ * that many RMIDs) just find the minimum RMIDs supported across
+ * all cpus.
+ *
+ * Also, check that the scales match on all cpus.
+ */
+ cpu_notifier_register_begin();
+
+ for_each_online_cpu(cpu) {
+ struct cpuinfo_x86 *c = &cpu_data(cpu);
+
+ if (c->x86_cache_max_rmid < cqm_max_rmid)
+ cqm_max_rmid = c->x86_cache_max_rmid;
+
+ if (c->x86_cache_occ_scale != cqm_l3_scale) {
+ pr_err("Multiple LLC scale values, disabling\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ }
+
+ snprintf(scale, sizeof(scale), "%u", cqm_l3_scale);
+ str = kstrdup(scale, GFP_KERNEL);
+ if (!str) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ event_attr_intel_cqm_llc_scale.event_str = str;
+
+ ret = intel_cqm_setup_rmid_cache();
+ if (ret)
+ goto out;
+
+ for_each_online_cpu(i) {
+ intel_cqm_cpu_prepare(i);
+ cqm_pick_event_reader(i);
+ }
+
+ __perf_cpu_notifier(intel_cqm_cpu_notifier);
+
+ ret = perf_pmu_register(&intel_cqm_pmu, "intel_cqm", -1);
+
+ if (ret)
+ pr_err("Intel CQM perf registration failed: %d\n", ret);
+ else
+ pr_info("Intel CQM monitoring enabled\n");
+
+out:
+ cpu_notifier_register_done();
+
+ return ret;
+}
+device_initcall(intel_cqm_init);
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 1bf06b6fd5dc..50ceb0665cda 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -128,6 +128,13 @@ struct hw_perf_event {
/* for tp_event->class */
struct list_head tp_list;
};
+ struct { /* intel_cqm */
+ int cqm_state;
+ int cqm_rmid;
+ struct list_head cqm_events_entry;
+ struct list_head cqm_groups_entry;
+ struct list_head cqm_group_entry;
+ };
#ifdef CONFIG_HAVE_HW_BREAKPOINT
struct { /* breakpoint */
/*
--
1.9.3
From: Matt Fleming <[email protected]>
There are many use cases where people will want to monitor more tasks
than there exist RMIDs in the hardware, meaning that we have to perform
some kind of multiplexing.
We do this by "rotating" the RMIDs in a workqueue, and assigning an RMID
to a waiting event when the RMID becomes unused.
This scheme reserves one RMID at all times for rotation. When we need to
schedule a new event we give it the reserved RMID, pick a victim event
from the front of the global CQM list and wait for the victim's RMID to
drop to zero occupancy, before it becomes the new reserved RMID.
We put the victim's RMID onto the limbo list, where it resides for a
"minimum queue time", which is intended to save ourselves an expensive
smp IPI when the RMID is unlikely to have a occupancy value below
__intel_cqm_threshold.
If we fail to recycle an RMID, even after waiting the minimum queue time
then we need to increment __intel_cqm_threshold. There is an upper bound
on this threshold, __intel_cqm_max_threshold, which is programmable from
userland as /sys/devices/intel_cqm/max_recycling_threshold.
The comments above __intel_cqm_rmid_rotate() have more details.
Cc: Peter Zijlstra <[email protected]>
Signed-off-by: Matt Fleming <[email protected]>
---
Changes in v3:
- Queue RMIDs for a minimum queue time to avoid expensive IPIs
- Allow upper bound to be specified for maximum recycling threshold
- Reduce preempt disabled section size in intel_cqm_rmid_stabilize()
- Reduce the limbo bitmap memory allocation sizes
Changes in v2:
- Update commit message to not make bogus claims like "all tasks in a
thread group are tracked together".
arch/x86/kernel/cpu/perf_event_intel_cqm.c | 582 +++++++++++++++++++++++++++--
1 file changed, 548 insertions(+), 34 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
index ffbda0fd4997..661ce4d70e4f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -16,6 +16,9 @@
static unsigned int cqm_max_rmid = -1;
static unsigned int cqm_l3_scale; /* supposedly cacheline size */
+static unsigned long *cqm_limbo_bitmap;
+static unsigned long *cqm_free_bitmap;
+
struct intel_cqm_state {
raw_spinlock_t lock;
int rmid;
@@ -25,9 +28,13 @@ struct intel_cqm_state {
static DEFINE_PER_CPU(struct intel_cqm_state, cqm_state);
/*
- * Protects cache_cgroups and cqm_rmid_lru.
+ * Protects cache_cgroups and cqm_rmid_free_lru and cqm_rmid_limbo_lru.
+ * Also protects event->hw.cqm_rmid
+ *
+ * Hold either for stability, both for modification of ->hw.cqm_rmid.
*/
static DEFINE_MUTEX(cache_mutex);
+static DEFINE_RAW_SPINLOCK(cache_lock);
/*
* Groups of events that have the same target(s), one RMID per group.
@@ -46,7 +53,34 @@ static cpumask_t cqm_cpumask;
#define QOS_EVENT_MASK QOS_L3_OCCUP_EVENT_ID
-static u64 __rmid_read(unsigned long rmid)
+/*
+ * This is central to the rotation algorithm in __intel_cqm_rmid_rotate().
+ *
+ * This rmid is always free and is guaranteed to have an associated
+ * near-zero occupancy value, i.e. no cachelines are tagged with this
+ * RMID, once __intel_cqm_rmid_rotate() returns.
+ */
+static unsigned int intel_cqm_rotation_rmid;
+
+#define INVALID_RMID (-1)
+
+/*
+ * Is @rmid valid for programming the hardware?
+ *
+ * rmid 0 is reserved by the hardware for all non-monitored tasks, which
+ * means that we should never come across an rmid with that value.
+ * Likewise, an rmid value of -1 is used to indicate "no rmid currently
+ * assigned" and is used as part of the rotation code.
+ */
+static inline bool __rmid_valid(unsigned int rmid)
+{
+ if (!rmid || rmid == INVALID_RMID)
+ return false;
+
+ return true;
+}
+
+static u64 __rmid_read(unsigned int rmid)
{
u64 val;
@@ -65,12 +99,13 @@ static u64 __rmid_read(unsigned long rmid)
}
struct cqm_rmid_entry {
- u64 rmid;
+ unsigned int rmid;
struct list_head list;
+ unsigned long queue_time;
};
/*
- * A least recently used list of RMIDs.
+ * cqm_rmid_free_lru - A least recently used list of RMIDs.
*
* Oldest entry at the head, newest (most recently used) entry at the
* tail. This list is never traversed, it's only used to keep track of
@@ -81,9 +116,18 @@ struct cqm_rmid_entry {
* in use. To mark an RMID as in use, remove its entry from the lru
* list.
*
- * This list is protected by cache_mutex.
+ *
+ * cqm_rmid_limbo_lru - list of currently unused but (potentially) dirty RMIDs.
+ *
+ * This list is contains RMIDs that no one is currently using but that
+ * may have a non-zero occupancy value associated with them. The
+ * rotation worker moves RMIDs from the limbo list to the free list once
+ * the occupancy value drops below __intel_cqm_threshold.
+ *
+ * Both lists are protected by cache_mutex.
*/
-static LIST_HEAD(cqm_rmid_lru);
+static LIST_HEAD(cqm_rmid_free_lru);
+static LIST_HEAD(cqm_rmid_limbo_lru);
/*
* We use a simple array of pointers so that we can lookup a struct
@@ -120,37 +164,51 @@ static int __get_rmid(void)
lockdep_assert_held(&cache_mutex);
- if (list_empty(&cqm_rmid_lru))
- return -EAGAIN;
+ if (list_empty(&cqm_rmid_free_lru))
+ return INVALID_RMID;
- entry = list_first_entry(&cqm_rmid_lru, struct cqm_rmid_entry, list);
+ entry = list_first_entry(&cqm_rmid_free_lru, struct cqm_rmid_entry, list);
list_del(&entry->list);
return entry->rmid;
}
-static void __put_rmid(int rmid)
+static void __put_rmid(unsigned int rmid)
{
struct cqm_rmid_entry *entry;
lockdep_assert_held(&cache_mutex);
+ WARN_ON(!__rmid_valid(rmid));
entry = __rmid_entry(rmid);
- list_add_tail(&entry->list, &cqm_rmid_lru);
+ entry->queue_time = jiffies;
+ list_add_tail(&entry->list, &cqm_rmid_limbo_lru);
}
static int intel_cqm_setup_rmid_cache(void)
{
struct cqm_rmid_entry *entry;
- int r;
+ unsigned int nr_rmids;
+ int r = 0;
+ nr_rmids = cqm_max_rmid + 1;
cqm_rmid_ptrs = kmalloc(sizeof(struct cqm_rmid_entry *) *
- (cqm_max_rmid + 1), GFP_KERNEL);
+ nr_rmids, GFP_KERNEL);
if (!cqm_rmid_ptrs)
return -ENOMEM;
- for (r = 0; r <= cqm_max_rmid; r++) {
+ cqm_free_bitmap = kmalloc(sizeof(long) * BITS_TO_LONGS(nr_rmids),
+ GFP_KERNEL);
+ if (!cqm_free_bitmap)
+ goto fail;
+
+ cqm_limbo_bitmap = kmalloc(sizeof(long) * BITS_TO_LONGS(nr_rmids),
+ GFP_KERNEL);
+ if (!cqm_limbo_bitmap)
+ goto fail;
+
+ for (; r <= cqm_max_rmid; r++) {
struct cqm_rmid_entry *entry;
entry = kmalloc(sizeof(*entry), GFP_KERNEL);
@@ -161,7 +219,7 @@ static int intel_cqm_setup_rmid_cache(void)
entry->rmid = r;
cqm_rmid_ptrs[r] = entry;
- list_add_tail(&entry->list, &cqm_rmid_lru);
+ list_add_tail(&entry->list, &cqm_rmid_free_lru);
}
/*
@@ -171,11 +229,17 @@ static int intel_cqm_setup_rmid_cache(void)
entry = __rmid_entry(0);
list_del(&entry->list);
+ mutex_lock(&cache_mutex);
+ intel_cqm_rotation_rmid = __get_rmid();
+ mutex_unlock(&cache_mutex);
+
return 0;
fail:
while (r--)
kfree(cqm_rmid_ptrs[r]);
+ kfree(cqm_limbo_bitmap);
+ kfree(cqm_free_bitmap);
kfree(cqm_rmid_ptrs);
return -ENOMEM;
}
@@ -313,6 +377,355 @@ static bool __conflict_event(struct perf_event *a, struct perf_event *b)
return false;
}
+struct intel_cqm_count_info {
+ struct perf_event *event;
+ bool rmid_valid;
+};
+
+static void __intel_cqm_event_count(void *info);
+
+/*
+ * Exchange the RMID of a group of events.
+ */
+static unsigned int
+intel_cqm_xchg_rmid(struct perf_event *group, unsigned int rmid)
+{
+ struct perf_event *event;
+ unsigned int old_rmid = group->hw.cqm_rmid;
+ struct list_head *head = &group->hw.cqm_group_entry;
+
+ lockdep_assert_held(&cache_mutex);
+
+ /*
+ * If our RMID is being deallocated, perform a read now.
+ */
+ if (__rmid_valid(old_rmid) && !__rmid_valid(rmid)) {
+ struct intel_cqm_count_info info;
+
+ local64_set(&group->count, 0);
+ info.event = group;
+
+ preempt_disable();
+ smp_call_function_many(&cqm_cpumask, __intel_cqm_event_count,
+ &info, 1);
+ preempt_enable();
+ }
+
+ raw_spin_lock_irq(&cache_lock);
+
+ group->hw.cqm_rmid = rmid;
+ list_for_each_entry(event, head, hw.cqm_group_entry)
+ event->hw.cqm_rmid = rmid;
+
+ raw_spin_unlock_irq(&cache_lock);
+
+ return old_rmid;
+}
+
+/*
+ * If we fail to assign a new RMID for intel_cqm_rotation_rmid because
+ * cachelines are still tagged with RMIDs in limbo, we progressively
+ * increment the threshold until we find an RMID in limbo with <=
+ * __intel_cqm_threshold lines tagged. This is designed to mitigate the
+ * problem where cachelines tagged with an RMID are not steadily being
+ * evicted.
+ *
+ * On successful rotations we decrease the threshold back towards zero.
+ *
+ * __intel_cqm_max_threshold provides an upper bound on the threshold,
+ * and is measured in bytes because it's exposed to userland.
+ */
+static unsigned int __intel_cqm_threshold;
+static unsigned int __intel_cqm_max_threshold = -1;
+
+/*
+ * Test whether an RMID has a zero occupancy value on this cpu.
+ */
+static void intel_cqm_stable(void *arg)
+{
+ unsigned int nr_bits;
+ int i = -1;
+
+ nr_bits = cqm_max_rmid + 1;
+
+ for (; i = find_next_bit(cqm_limbo_bitmap, nr_bits, i+1),
+ i < nr_bits;) {
+ if (__rmid_read(i) > __intel_cqm_threshold)
+ clear_bit(i, cqm_free_bitmap);
+ }
+}
+
+static unsigned int __rotation_period = 250; /* ms */
+
+/*
+ * intel_cqm_rmid_stabilize - move RMIDs from limbo to free list
+ * @available: are there freeable RMIDs on the limbo list?
+ *
+ * Quiescent state; wait for all 'freed' RMIDs to become unused, i.e. no
+ * cachelines are tagged with those RMIDs. After this we can reuse them
+ * and know that the current set of active RMIDs is stable.
+ *
+ * Return %true or %false depending on whether we were able to stabilize
+ * an RMID for intel_cqm_rotation_rmid.
+ *
+ * If we return %false then @available is updated to indicate the reason
+ * we couldn't stabilize any RMIDs. @available is %false if no suitable
+ * RMIDs were found on the limbo list to recycle, i.e. no RMIDs had been
+ * on the list for the minimum queue time. If @available is %true then,
+ * we found suitable RMIDs to recycle but none had an associated
+ * occupancy value below __intel_cqm_threshold and the threshold should
+ * be increased and stabilization reattempted.
+ */
+static bool intel_cqm_rmid_stabilize(bool *available)
+{
+ struct cqm_rmid_entry *entry;
+ unsigned int nr_bits;
+ struct perf_event *event;
+
+ lockdep_assert_held(&cache_mutex);
+
+ nr_bits = cqm_max_rmid + 1;
+
+ bitmap_zero(cqm_limbo_bitmap, nr_bits);
+ bitmap_zero(cqm_free_bitmap, nr_bits);
+
+ list_for_each_entry(entry, &cqm_rmid_limbo_lru, list) {
+ unsigned long min_queue_time;
+ unsigned long now = jiffies;
+
+ /*
+ * We hold RMIDs placed into limbo for a minimum queue
+ * time. Before the minimum queue time has elapsed we do
+ * not recycle RMIDs.
+ *
+ * The reasoning is that until a sufficient time has
+ * passed since we stopped using an RMID, any RMID
+ * placed onto the limbo list will likely still have
+ * data tagged in the cache, which means we'll probably
+ * fail to recycle it anyway.
+ *
+ * We can save ourselves an expensive IPI by skipping
+ * any RMIDs that have not been queued for the minimum
+ * time.
+ */
+ min_queue_time = entry->queue_time +
+ msecs_to_jiffies(__rotation_period);
+
+ if (time_after(min_queue_time, now))
+ continue;
+
+ set_bit(entry->rmid, cqm_limbo_bitmap);
+ set_bit(entry->rmid, cqm_free_bitmap);
+ }
+
+ /*
+ * Fast return if none of the RMIDs on the limbo list have been
+ * sitting on the queue for the minimum queue time.
+ */
+ *available = !bitmap_empty(cqm_limbo_bitmap, nr_bits);
+ if (!*available)
+ return false;
+
+ /*
+ * Test whether an RMID is free for each package.
+ */
+ preempt_disable();
+ smp_call_function_many(&cqm_cpumask, intel_cqm_stable, NULL, true);
+ preempt_enable();
+
+ if (!bitmap_empty(cqm_free_bitmap, nr_bits)) {
+ int i = -1;
+
+ for (; i = find_next_bit(cqm_free_bitmap, nr_bits, i+1),
+ i < nr_bits;) {
+ entry = __rmid_entry(i);
+
+ list_del(&entry->list); /* remove from limbo */
+
+ /*
+ * The rotation RMID gets priority if it's
+ * currently invalid. In which case, skip adding
+ * the RMID to the the free lru.
+ */
+ if (!__rmid_valid(intel_cqm_rotation_rmid)) {
+ intel_cqm_rotation_rmid = i;
+ continue;
+ }
+
+ /*
+ * If we have groups waiting for RMIDs, hand
+ * them one now.
+ */
+ list_for_each_entry(event, &cache_groups,
+ hw.cqm_groups_entry) {
+ if (__rmid_valid(event->hw.cqm_rmid))
+ continue;
+
+ intel_cqm_xchg_rmid(event, i);
+ entry = NULL;
+ break;
+ }
+
+ if (!entry)
+ continue;
+
+ /*
+ * Otherwise place it onto the free list.
+ */
+ list_add_tail(&entry->list, &cqm_rmid_free_lru);
+ }
+ }
+
+ return __rmid_valid(intel_cqm_rotation_rmid);
+}
+
+/*
+ * Pick a victim group and move it to the tail of the group list.
+ */
+static struct perf_event *
+__intel_cqm_pick_and_rotate(void)
+{
+ struct perf_event *rotor;
+
+ lockdep_assert_held(&cache_mutex);
+ lockdep_assert_held(&cache_lock);
+
+ rotor = list_first_entry(&cache_groups, struct perf_event,
+ hw.cqm_groups_entry);
+ list_rotate_left(&cache_groups);
+
+ return rotor;
+}
+
+/*
+ * Attempt to rotate the groups and assign new RMIDs.
+ *
+ * Rotating RMIDs is complicated because the hardware doesn't give us
+ * any clues.
+ *
+ * There's problems with the hardware interface; when you change the
+ * task:RMID map cachelines retain their 'old' tags, giving a skewed
+ * picture. In order to work around this, we must always keep one free
+ * RMID - intel_cqm_rotation_rmid.
+ *
+ * Rotation works by taking away an RMID from a group (the old RMID),
+ * and assigning the free RMID to another group (the new RMID). We must
+ * then wait for the old RMID to not be used (no cachelines tagged).
+ * This ensure that all cachelines are tagged with 'active' RMIDs. At
+ * this point we can start reading values for the new RMID and treat the
+ * old RMID as the free RMID for the next rotation.
+ *
+ * Return %true or %false depending on whether we did any rotating.
+ */
+static bool __intel_cqm_rmid_rotate(void)
+{
+ struct perf_event *group, *rotor, *start = NULL;
+ unsigned int nr_needed = 0;
+ unsigned int rmid;
+ bool rotated = false;
+ bool available;
+
+ mutex_lock(&cache_mutex);
+
+again:
+ /*
+ * Fast path through this function if there are no groups and no
+ * RMIDs that need cleaning.
+ */
+ if (list_empty(&cache_groups) && list_empty(&cqm_rmid_limbo_lru))
+ goto out;
+
+ list_for_each_entry(group, &cache_groups, hw.cqm_groups_entry) {
+ if (!__rmid_valid(group->hw.cqm_rmid)) {
+ if (!start)
+ start = group;
+ nr_needed++;
+ }
+ }
+
+ /*
+ * We have some event groups, but they all have RMIDs assigned
+ * and no RMIDs need cleaning.
+ */
+ if (!nr_needed && list_empty(&cqm_rmid_limbo_lru))
+ goto out;
+
+ if (!nr_needed)
+ goto stabilize;
+
+ /*
+ * We have more event groups without RMIDs than available RMIDs.
+ *
+ * We force deallocate the rmid of the group at the head of
+ * cache_groups. The first event group without an RMID then gets
+ * assigned intel_cqm_rotation_rmid. This ensures we always make
+ * forward progress.
+ *
+ * Rotate the cache_groups list so the previous head is now the
+ * tail.
+ */
+ rotor = __intel_cqm_pick_and_rotate();
+ rmid = intel_cqm_xchg_rmid(rotor, INVALID_RMID);
+
+ /*
+ * The group at the front of the list should always have a valid
+ * RMID. If it doesn't then no groups have RMIDs assigned.
+ */
+ if (!__rmid_valid(rmid))
+ goto stabilize;
+
+ /*
+ * If the rotation is going to succeed, reduce the threshold so
+ * that we don't needlessly reuse dirty RMIDs.
+ */
+ if (__rmid_valid(intel_cqm_rotation_rmid)) {
+ intel_cqm_xchg_rmid(start, intel_cqm_rotation_rmid);
+ intel_cqm_rotation_rmid = INVALID_RMID;
+
+ if (__intel_cqm_threshold)
+ __intel_cqm_threshold--;
+ }
+
+ __put_rmid(rmid);
+
+ rotated = true;
+
+stabilize:
+ /*
+ * We now need to stablize the RMID we freed above (if any) to
+ * ensure that the next time we rotate we have an RMID with zero
+ * occupancy value.
+ *
+ * Alternatively, if we didn't need to perform any rotation,
+ * we'll have a bunch of RMIDs in limbo that need stabilizing.
+ */
+ if (!intel_cqm_rmid_stabilize(&available)) {
+ unsigned int limit;
+
+ limit = __intel_cqm_max_threshold / cqm_l3_scale;
+ if (available && __intel_cqm_threshold < limit) {
+ __intel_cqm_threshold++;
+ goto again;
+ }
+ }
+
+out:
+ mutex_unlock(&cache_mutex);
+ return rotated;
+}
+
+static void intel_cqm_rmid_rotate(struct work_struct *work);
+
+static DECLARE_DELAYED_WORK(intel_cqm_rmid_work, intel_cqm_rmid_rotate);
+
+static void intel_cqm_rmid_rotate(struct work_struct *work)
+{
+ __intel_cqm_rmid_rotate();
+
+ schedule_delayed_work(&intel_cqm_rmid_work,
+ msecs_to_jiffies(__rotation_period));
+}
+
/*
* Find a group and setup RMID.
*
@@ -322,7 +735,6 @@ static int intel_cqm_setup_event(struct perf_event *event,
struct perf_event **group)
{
struct perf_event *iter;
- int rmid;
list_for_each_entry(iter, &cache_groups, hw.cqm_groups_entry) {
if (__match_event(iter, event)) {
@@ -336,17 +748,14 @@ static int intel_cqm_setup_event(struct perf_event *event,
return -EBUSY;
}
- rmid = __get_rmid();
- if (rmid < 0)
- return rmid;
-
- event->hw.cqm_rmid = rmid;
+ event->hw.cqm_rmid = __get_rmid();
return 0;
}
static void intel_cqm_event_read(struct perf_event *event)
{
- unsigned long rmid;
+ unsigned long flags;
+ unsigned int rmid;
u64 val;
/*
@@ -355,29 +764,50 @@ static void intel_cqm_event_read(struct perf_event *event)
if (event->cpu == -1)
return;
+ raw_spin_lock_irqsave(&cache_lock, flags);
rmid = event->hw.cqm_rmid;
+
+ if (!__rmid_valid(rmid))
+ goto out;
+
val = __rmid_read(rmid);
/*
* Ignore this reading on error states and do not update the value.
*/
if (val & (RMID_VAL_ERROR | RMID_VAL_UNAVAIL))
- return;
+ goto out;
local64_set(&event->count, val);
+out:
+ raw_spin_unlock_irqrestore(&cache_lock, flags);
}
static void __intel_cqm_event_count(void *info)
{
- struct perf_event *event = info;
+ struct intel_cqm_count_info *ci = info;
+ struct perf_event *event = ci->event;
+ unsigned long flags;
+ unsigned int rmid;
u64 val;
- val = __rmid_read(event->hw.cqm_rmid);
+ raw_spin_lock_irqsave(&cache_lock, flags);
+
+ rmid = event->hw.cqm_rmid;
+ if (!__rmid_valid(rmid)) {
+ ci->rmid_valid = false;
+ goto unlock;
+ }
+
+ val = __rmid_read(rmid);
if (val & (RMID_VAL_ERROR | RMID_VAL_UNAVAIL))
- return;
+ goto unlock;
local64_add(val, &event->count);
+
+unlock:
+ raw_spin_unlock_irqrestore(&cache_lock, flags);
}
static inline bool cqm_group_leader(struct perf_event *event)
@@ -387,6 +817,9 @@ static inline bool cqm_group_leader(struct perf_event *event)
static u64 intel_cqm_event_count(struct perf_event *event)
{
+ struct intel_cqm_count_info info;
+ u64 count;
+
/*
* We only need to worry about task events. System-wide events
* are handled like usual, i.e. entirely with
@@ -407,19 +840,26 @@ static u64 intel_cqm_event_count(struct perf_event *event)
if (!cqm_group_leader(event))
return 0;
+ count = local64_read(&event->count);
local64_set(&event->count, 0);
- preempt_disable()
- smp_call_function_many(&cqm_cpumask, __intel_cqm_event_count, event, 1);
+ info.rmid_valid = true;
+ info.event = event;
+
+ preempt_disable();
+ smp_call_function_many(&cqm_cpumask, __intel_cqm_event_count, &info, 1);
preempt_enable();
+ if (!info.rmid_valid)
+ local64_set(&event->count, count);
+
return __perf_event_count(event);
}
static void intel_cqm_event_start(struct perf_event *event, int mode)
{
struct intel_cqm_state *state = &__get_cpu_var(cqm_state);
- unsigned long rmid = event->hw.cqm_rmid;
+ unsigned int rmid = event->hw.cqm_rmid;
unsigned long flags;
if (!(event->hw.cqm_state & PERF_HES_STOPPED))
@@ -465,15 +905,19 @@ static void intel_cqm_event_stop(struct perf_event *event, int mode)
static int intel_cqm_event_add(struct perf_event *event, int mode)
{
- int rmid;
+ unsigned long flags;
+ unsigned int rmid;
+
+ raw_spin_lock_irqsave(&cache_lock, flags);
event->hw.cqm_state = PERF_HES_STOPPED;
rmid = event->hw.cqm_rmid;
- WARN_ON_ONCE(!rmid);
- if (mode & PERF_EF_START)
+ if (__rmid_valid(rmid) && (mode & PERF_EF_START))
intel_cqm_event_start(event, mode);
+ raw_spin_unlock_irqrestore(&cache_lock, flags);
+
return 0;
}
@@ -510,8 +954,10 @@ static void intel_cqm_event_destroy(struct perf_event *event)
list_replace(&event->hw.cqm_groups_entry,
&group_other->hw.cqm_groups_entry);
} else {
- int rmid = event->hw.cqm_rmid;
- __put_rmid(rmid);
+ unsigned int rmid = event->hw.cqm_rmid;
+
+ if (__rmid_valid(rmid))
+ __put_rmid(rmid);
list_del(&event->hw.cqm_groups_entry);
}
}
@@ -524,6 +970,7 @@ static struct pmu intel_cqm_pmu;
static int intel_cqm_event_init(struct perf_event *event)
{
struct perf_event *group = NULL;
+ bool rotate = false;
int err;
if (event->attr.type != intel_cqm_pmu.type)
@@ -560,10 +1007,24 @@ static int intel_cqm_event_init(struct perf_event *event)
} else {
list_add_tail(&event->hw.cqm_groups_entry,
&cache_groups);
+
+ /*
+ * All RMIDs are either in use or have recently been
+ * used. Kick the rotation worker to clean/free some.
+ *
+ * We only do this for the group leader, rather than for
+ * every event in a group to save on needless work.
+ */
+ if (!__rmid_valid(event->hw.cqm_rmid))
+ rotate = true;
}
out:
mutex_unlock(&cache_mutex);
+
+ if (rotate)
+ schedule_delayed_work(&intel_cqm_rmid_work, 0);
+
return err;
}
@@ -598,9 +1059,62 @@ static struct attribute_group intel_cqm_format_group = {
.attrs = intel_cqm_formats_attr,
};
+static ssize_t
+max_recycle_threshold_show(struct device *dev, struct device_attribute *attr,
+ char *page)
+{
+ ssize_t rv;
+
+ mutex_lock(&cache_mutex);
+ rv = snprintf(page, PAGE_SIZE-1, "%u\n", __intel_cqm_max_threshold);
+ mutex_unlock(&cache_mutex);
+
+ return rv;
+}
+
+static ssize_t
+max_recycle_threshold_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ unsigned int bytes, cachelines;
+ int ret;
+
+ ret = kstrtouint(buf, 0, &bytes);
+ if (ret)
+ return ret;
+
+ mutex_lock(&cache_mutex);
+
+ __intel_cqm_max_threshold = bytes;
+ cachelines = bytes / cqm_l3_scale;
+
+ /*
+ * The new maximum takes effect immediately.
+ */
+ if (__intel_cqm_threshold > cachelines)
+ __intel_cqm_threshold = cachelines;
+
+ mutex_unlock(&cache_mutex);
+
+ return count;
+}
+
+static DEVICE_ATTR_RW(max_recycle_threshold);
+
+static struct attribute *intel_cqm_attrs[] = {
+ &dev_attr_max_recycle_threshold.attr,
+ NULL,
+};
+
+static const struct attribute_group intel_cqm_group = {
+ .attrs = intel_cqm_attrs,
+};
+
static const struct attribute_group *intel_cqm_attr_groups[] = {
&intel_cqm_events_group,
&intel_cqm_format_group,
+ &intel_cqm_group,
NULL,
};
--
1.9.3
On Thu, Nov 06, 2014 at 12:23:20PM +0000, Matt Fleming wrote:
> +static void __intel_cqm_event_count(void *info)
> +{
> + struct perf_event *event = info;
> + u64 val;
> +
> + val = __rmid_read(event->hw.cqm_rmid);
> +
> + if (val & (RMID_VAL_ERROR | RMID_VAL_UNAVAIL))
> + return;
> +
> + local64_add(val, &event->count);
> +}
> +
> +static inline bool cqm_group_leader(struct perf_event *event)
> +{
> + return !list_empty(&event->hw.cqm_groups_entry);
> +}
> +
> +static u64 intel_cqm_event_count(struct perf_event *event)
> +{
> + /*
> + * We only need to worry about task events. System-wide events
> + * are handled like usual, i.e. entirely with
> + * intel_cqm_event_read().
> + */
> + if (event->cpu != -1)
> + return __perf_event_count(event);
> +
> + /*
> + * Only the group leader gets to report values. This stops us
> + * reporting duplicate values to userspace, and gives us a clear
> + * rule for which task gets to report the values.
> + *
> + * Note that it is impossible to attribute these values to
> + * specific packages - we forfeit that ability when we create
> + * task events.
> + */
> + if (!cqm_group_leader(event))
> + return 0;
> +
> + local64_set(&event->count, 0);
> +
> + preempt_disable()
> + smp_call_function_many(&cqm_cpumask, __intel_cqm_event_count, event, 1);
> + preempt_enable();
> +
> + return __perf_event_count(event);
> +}
How is that supposed to work? You call __intel_cqm_event_count() on the
one cpu per socket, but then you use a local_add, not an atomic_add,
even though these adds can happen concurrently as per IPI broadcast.
Also, I think smp_call_function_many() ignores the current cpu, if this
cpu happens to be the cpu for this socket, you're up some creek without
no paddle, right?
Thirdly, there is no serialization around calling perf_event_count() [or
your pmu::count method] so you cannot temporarily put it to 0.
On Fri, 07 Nov, at 10:08:04AM, Peter Zijlstra wrote:
>
> How is that supposed to work? You call __intel_cqm_event_count() on the
> one cpu per socket, but then you use a local_add, not an atomic_add,
> even though these adds can happen concurrently as per IPI broadcast.
Ouch, right. That's broken.
> Also, I think smp_call_function_many() ignores the current cpu, if this
> cpu happens to be the cpu for this socket, you're up some creek without
> no paddle, right?
OK, I didn't realise that. Yeah that sounds very problematic. I think my
eyes skipped over the word "other" in the smp_call_function_many() docs,
* smp_call_function_many(): Run a function on a set of other CPUs.
So, the correct way to do this is to iterate over cqm_cpumask and invoke
smp_call_function_single(), right?
> Thirdly, there is no serialization around calling perf_event_count() [or
> your pmu::count method] so you cannot temporarily put it to 0.
Urgh, thanks. Good spot. I'm gonna have to think of a suitable
serialisation mechanism because all the current ones are pretty
heavy-handed. And of course, there's the added fun that it needs to be
held across the IPIs.
Perhaps a per-cache-group mutex?
--
Matt Fleming, Intel Open Source Technology Center
On Fri, Nov 07, 2014 at 10:09:59AM +0000, Matt Fleming wrote:
> On Fri, 07 Nov, at 10:08:04AM, Peter Zijlstra wrote:
> >
> > How is that supposed to work? You call __intel_cqm_event_count() on the
> > one cpu per socket, but then you use a local_add, not an atomic_add,
> > even though these adds can happen concurrently as per IPI broadcast.
>
> Ouch, right. That's broken.
>
> > Also, I think smp_call_function_many() ignores the current cpu, if this
> > cpu happens to be the cpu for this socket, you're up some creek without
> > no paddle, right?
>
> OK, I didn't realise that. Yeah that sounds very problematic. I think my
> eyes skipped over the word "other" in the smp_call_function_many() docs,
>
> * smp_call_function_many(): Run a function on a set of other CPUs.
>
> So, the correct way to do this is to iterate over cqm_cpumask and invoke
> smp_call_function_single(), right?
>
> > Thirdly, there is no serialization around calling perf_event_count() [or
> > your pmu::count method] so you cannot temporarily put it to 0.
>
> Urgh, thanks. Good spot. I'm gonna have to think of a suitable
> serialisation mechanism because all the current ones are pretty
> heavy-handed. And of course, there's the added fun that it needs to be
> held across the IPIs.
>
> Perhaps a per-cache-group mutex?
struct rmid_read {
unsigned int rmid;
atomic64_t value;
}
static void __remote_rmid_read(void *arg)
{
struct rmid_read *rr = arg;
u64 val = __rmid_read(rr->rmid);
if (val & (RMID_VAL_ERROR | RMID_VAL_UNAVAIL))
return;
atomic64_add(val, &rr->value);
}
static void task_rmid_read(struct perf_event *event)
{
struct rmid_read rr = {
.rmid = ...,
.value = ATOMIC64_INIT(0),
};
int cpu;
...
cpu = get_cpu();
smp_call_function_many(&cqm_cpumask, __remote_rmid_read, &rr);
if (cpumask_test(cpu, &cqm_cpumask)) {
local_irq_disable();
__remote_rmid_read(&rr);
local_irq_enable();
}
put_cpu();
local64_set(&event->count, atomic64_read(&rr->value));
}
On Thu, Nov 06, 2014 at 12:23:21PM +0000, Matt Fleming wrote:
> +/*
> + * Exchange the RMID of a group of events.
> + */
> +static unsigned int
> +intel_cqm_xchg_rmid(struct perf_event *group, unsigned int rmid)
> +{
> + struct perf_event *event;
> + unsigned int old_rmid = group->hw.cqm_rmid;
> + struct list_head *head = &group->hw.cqm_group_entry;
> +
> + lockdep_assert_held(&cache_mutex);
> +
> + /*
> + * If our RMID is being deallocated, perform a read now.
> + */
> + if (__rmid_valid(old_rmid) && !__rmid_valid(rmid)) {
> + struct intel_cqm_count_info info;
> +
> + local64_set(&group->count, 0);
> + info.event = group;
> +
> + preempt_disable();
> + smp_call_function_many(&cqm_cpumask, __intel_cqm_event_count,
> + &info, 1);
> + preempt_enable();
> + }
This suffers the same issue as before, why not call that one function
and not reimplement it?
Also, I don't think we'd ever swap an rmid for another valid one, right?
So we could do this read/update unconditionally.
> +
> + raw_spin_lock_irq(&cache_lock);
> +
> + group->hw.cqm_rmid = rmid;
> + list_for_each_entry(event, head, hw.cqm_group_entry)
> + event->hw.cqm_rmid = rmid;
> +
> + raw_spin_unlock_irq(&cache_lock);
> +
> + return old_rmid;
> +}
On Thu, Nov 06, 2014 at 12:23:21PM +0000, Matt Fleming wrote:
> + /*
> + * Test whether an RMID is free for each package.
> + */
> + preempt_disable();
> + smp_call_function_many(&cqm_cpumask, intel_cqm_stable, NULL, true);
> + preempt_enable();
Same problem again, the current cpu is not included.
Ah, just found we have on_each_cpu_mask(), which is what you want.
On Thu, Nov 06, 2014 at 12:23:21PM +0000, Matt Fleming wrote:
> +/*
> + * If we fail to assign a new RMID for intel_cqm_rotation_rmid because
> + * cachelines are still tagged with RMIDs in limbo, we progressively
> + * increment the threshold until we find an RMID in limbo with <=
> + * __intel_cqm_threshold lines tagged. This is designed to mitigate the
> + * problem where cachelines tagged with an RMID are not steadily being
> + * evicted.
> + *
> + * On successful rotations we decrease the threshold back towards zero.
> + *
> + * __intel_cqm_max_threshold provides an upper bound on the threshold,
> + * and is measured in bytes because it's exposed to userland.
> + */
> +static unsigned int __intel_cqm_threshold;
> +static unsigned int __intel_cqm_max_threshold = -1;
Should we initialize that to a finite value? Surely results are absolute
crap if we do indeed reach that max?
On Thu, Nov 06, 2014 at 12:23:21PM +0000, Matt Fleming wrote:
> +/*
> + * Test whether an RMID has a zero occupancy value on this cpu.
> + */
> +static void intel_cqm_stable(void *arg)
> +{
> + unsigned int nr_bits;
> + int i = -1;
> +
> + nr_bits = cqm_max_rmid + 1;
> +
> + for (; i = find_next_bit(cqm_limbo_bitmap, nr_bits, i+1),
> + i < nr_bits;) {
> + if (__rmid_read(i) > __intel_cqm_threshold)
> + clear_bit(i, cqm_free_bitmap);
> + }
> +}
> +
> +static unsigned int __rotation_period = 250; /* ms */
> +
> +/*
> + * intel_cqm_rmid_stabilize - move RMIDs from limbo to free list
> + * @available: are there freeable RMIDs on the limbo list?
> + *
> + * Quiescent state; wait for all 'freed' RMIDs to become unused, i.e. no
> + * cachelines are tagged with those RMIDs. After this we can reuse them
> + * and know that the current set of active RMIDs is stable.
> + *
> + * Return %true or %false depending on whether we were able to stabilize
> + * an RMID for intel_cqm_rotation_rmid.
> + *
> + * If we return %false then @available is updated to indicate the reason
> + * we couldn't stabilize any RMIDs. @available is %false if no suitable
> + * RMIDs were found on the limbo list to recycle, i.e. no RMIDs had been
> + * on the list for the minimum queue time. If @available is %true then,
> + * we found suitable RMIDs to recycle but none had an associated
> + * occupancy value below __intel_cqm_threshold and the threshold should
> + * be increased and stabilization reattempted.
> + */
> +static bool intel_cqm_rmid_stabilize(bool *available)
> +{
> + struct cqm_rmid_entry *entry;
> + unsigned int nr_bits;
> + struct perf_event *event;
> +
> + lockdep_assert_held(&cache_mutex);
> +
> + nr_bits = cqm_max_rmid + 1;
> +
> + bitmap_zero(cqm_limbo_bitmap, nr_bits);
> + bitmap_zero(cqm_free_bitmap, nr_bits);
> +
> + list_for_each_entry(entry, &cqm_rmid_limbo_lru, list) {
> + unsigned long min_queue_time;
> + unsigned long now = jiffies;
> +
> + /*
> + * We hold RMIDs placed into limbo for a minimum queue
> + * time. Before the minimum queue time has elapsed we do
> + * not recycle RMIDs.
> + *
> + * The reasoning is that until a sufficient time has
> + * passed since we stopped using an RMID, any RMID
> + * placed onto the limbo list will likely still have
> + * data tagged in the cache, which means we'll probably
> + * fail to recycle it anyway.
> + *
> + * We can save ourselves an expensive IPI by skipping
> + * any RMIDs that have not been queued for the minimum
> + * time.
> + */
> + min_queue_time = entry->queue_time +
> + msecs_to_jiffies(__rotation_period);
> +
> + if (time_after(min_queue_time, now))
> + continue;
Why continue; this LRU is time ordered, later entries cannot be earlier,
right?
> + set_bit(entry->rmid, cqm_limbo_bitmap);
> + set_bit(entry->rmid, cqm_free_bitmap);
> + }
> +
> + /*
> + * Fast return if none of the RMIDs on the limbo list have been
> + * sitting on the queue for the minimum queue time.
> + */
> + *available = !bitmap_empty(cqm_limbo_bitmap, nr_bits);
> + if (!*available)
> + return false;
> +
> + /*
> + * Test whether an RMID is free for each package.
> + */
> + preempt_disable();
> + smp_call_function_many(&cqm_cpumask, intel_cqm_stable, NULL, true);
> + preempt_enable();
I don't get the whole list -> bitmap -> list juggle.
enum rmid_cycle_state {
RMID_AVAILABLE = 0,
RMID_LIMBO,
RMID_YOUNG,
};
struct cqm_rmid_entry {
...
enum rmid_cycle_state state;
};
static void __intel_sqm_stable(void *arg)
{
list_for_each_entry(entry, &cqm_rmid_limbo_lru, list) {
if (entry->state == RMID_YOUNG)
break;
if (__rmid_read(entry->rmid) > __threshold)
entry->state = RMID_LIMBO;
}
}
static bool intel_cqm_rmid_stabilize()
{
unsigned long queue_time = jiffies + msecs_to_jiffies(__rotation_period);
unsigned int nr_limbo = 0;
...
list_for_each_entry(entry, &cqm_rmid_limbo_lru, list) {
if (time_after(entry->queue_time, queue_time))
break;
entry->state = RMID_AVAILABLE;
nr_limbo++;
}
if (!nr_limbo)
return;
on_each_cpu_mask(&cqm_cpumask, __intel_cqm_stable, NULL, true);
list_for_each_entry_safe(entry, tmp, &cqm_rmid_limbo_lru, list) {
if (entry->state == RMID_YOUNG)
break;
if (entry->state == RMID_AVAILABLE)
list_move(&cqm_rmid_free_list, &entry->list);
}
}
Would not something like that work?
On Fri, Nov 07, 2014 at 01:34:31PM +0100, Peter Zijlstra wrote:
>
> enum rmid_cycle_state {
> RMID_AVAILABLE = 0,
> RMID_LIMBO,
> RMID_YOUNG,
> };
>
> struct cqm_rmid_entry {
> ...
> enum rmid_cycle_state state;
> };
>
> static void __intel_sqm_stable(void *arg)
> {
> list_for_each_entry(entry, &cqm_rmid_limbo_lru, list) {
> if (entry->state == RMID_YOUNG)
> break;
>
> if (__rmid_read(entry->rmid) > __threshold)
> entry->state = RMID_LIMBO;
> }
> }
>
> static bool intel_cqm_rmid_stabilize()
> {
> unsigned long queue_time = jiffies + msecs_to_jiffies(__rotation_period);
> unsigned int nr_limbo = 0;
> ...
>
> list_for_each_entry(entry, &cqm_rmid_limbo_lru, list) {
> if (time_after(entry->queue_time, queue_time))
> break;
>
> entry->state = RMID_AVAILABLE;
> nr_limbo++;
For optional goodness:
if (nr_limbo > max_scan_size)
break;
Which will limit the number of RMIDs you'll scan from the IPI, and
thereby limit the time taken there.
> }
>
> if (!nr_limbo)
> return;
>
> on_each_cpu_mask(&cqm_cpumask, __intel_cqm_stable, NULL, true);
>
> list_for_each_entry_safe(entry, tmp, &cqm_rmid_limbo_lru, list) {
> if (entry->state == RMID_YOUNG)
> break;
>
> if (entry->state == RMID_AVAILABLE)
> list_move(&cqm_rmid_free_list, &entry->list);
> }
> }
>
>
> Would not something like that work?
On Thu, Nov 06, 2014 at 12:23:21PM +0000, Matt Fleming wrote:
> +static unsigned int __rotation_period = 250; /* ms */
There's two things being conflated here I think, even though they're
related.
The one is how long we'll let RMIDs settle before trying to reuse them,
the second is how often we attempt the rotation. Clearly the rotation
time is limited by the settle time, but they need not be the same.
Also, we already have a per pmu rotation interval in
pmu::hrtimer_interval_ms, I suppose we should reuse that to be
consistent.
On Fri, 07 Nov, at 01:06:12PM, Peter Zijlstra wrote:
> On Thu, Nov 06, 2014 at 12:23:21PM +0000, Matt Fleming wrote:
> > +/*
> > + * Exchange the RMID of a group of events.
> > + */
> > +static unsigned int
> > +intel_cqm_xchg_rmid(struct perf_event *group, unsigned int rmid)
> > +{
> > + struct perf_event *event;
> > + unsigned int old_rmid = group->hw.cqm_rmid;
> > + struct list_head *head = &group->hw.cqm_group_entry;
> > +
> > + lockdep_assert_held(&cache_mutex);
> > +
> > + /*
> > + * If our RMID is being deallocated, perform a read now.
> > + */
> > + if (__rmid_valid(old_rmid) && !__rmid_valid(rmid)) {
> > + struct intel_cqm_count_info info;
> > +
> > + local64_set(&group->count, 0);
> > + info.event = group;
> > +
> > + preempt_disable();
> > + smp_call_function_many(&cqm_cpumask, __intel_cqm_event_count,
> > + &info, 1);
> > + preempt_enable();
> > + }
>
> This suffers the same issue as before, why not call that one function
> and not reimplement it?
>
> Also, I don't think we'd ever swap an rmid for another valid one, right?
> So we could do this read/update unconditionally.
No, we never swap a valid RMID for another valid one, but we do make a
invalid -> valid transition, so doing the read wouldn't make sense
in that situation.
--
Matt Fleming, Intel Open Source Technology Center
On Fri, 07 Nov, at 01:18:03PM, Peter Zijlstra wrote:
> On Thu, Nov 06, 2014 at 12:23:21PM +0000, Matt Fleming wrote:
> > + /*
> > + * Test whether an RMID is free for each package.
> > + */
> > + preempt_disable();
> > + smp_call_function_many(&cqm_cpumask, intel_cqm_stable, NULL, true);
> > + preempt_enable();
>
> Same problem again, the current cpu is not included.
>
> Ah, just found we have on_each_cpu_mask(), which is what you want.
Aha, yes, that looks useful. Thanks!
--
Matt Fleming, Intel Open Source Technology Center
On Fri, 07 Nov, at 01:20:52PM, Peter Zijlstra wrote:
> On Thu, Nov 06, 2014 at 12:23:21PM +0000, Matt Fleming wrote:
> > +/*
> > + * If we fail to assign a new RMID for intel_cqm_rotation_rmid because
> > + * cachelines are still tagged with RMIDs in limbo, we progressively
> > + * increment the threshold until we find an RMID in limbo with <=
> > + * __intel_cqm_threshold lines tagged. This is designed to mitigate the
> > + * problem where cachelines tagged with an RMID are not steadily being
> > + * evicted.
> > + *
> > + * On successful rotations we decrease the threshold back towards zero.
> > + *
> > + * __intel_cqm_max_threshold provides an upper bound on the threshold,
> > + * and is measured in bytes because it's exposed to userland.
> > + */
> > +static unsigned int __intel_cqm_threshold;
> > +static unsigned int __intel_cqm_max_threshold = -1;
>
> Should we initialize that to a finite value? Surely results are absolute
> crap if we do indeed reach that max?
I don't think we'll ever reach that max, it'll bottom out once it
reaches the size of the LLC, since the pathological case is that the
RMID you're currently trying to stabilize is used to tag every line in
the LLC.
Not sure what a reasonable finite value would be here though? 10% of the
LLC size?
--
Matt Fleming, Intel Open Source Technology Center
On Mon, Nov 10, 2014 at 08:43:53PM +0000, Matt Fleming wrote:
> On Fri, 07 Nov, at 01:06:12PM, Peter Zijlstra wrote:
> > On Thu, Nov 06, 2014 at 12:23:21PM +0000, Matt Fleming wrote:
> > > +/*
> > > + * Exchange the RMID of a group of events.
> > > + */
> > > +static unsigned int
> > > +intel_cqm_xchg_rmid(struct perf_event *group, unsigned int rmid)
> > > +{
> > > + struct perf_event *event;
> > > + unsigned int old_rmid = group->hw.cqm_rmid;
> > > + struct list_head *head = &group->hw.cqm_group_entry;
> > > +
> > > + lockdep_assert_held(&cache_mutex);
> > > +
> > > + /*
> > > + * If our RMID is being deallocated, perform a read now.
> > > + */
> > > + if (__rmid_valid(old_rmid) && !__rmid_valid(rmid)) {
> > > + struct intel_cqm_count_info info;
> > > +
> > > + local64_set(&group->count, 0);
> > > + info.event = group;
> > > +
> > > + preempt_disable();
> > > + smp_call_function_many(&cqm_cpumask, __intel_cqm_event_count,
> > > + &info, 1);
> > > + preempt_enable();
> > > + }
> >
> > This suffers the same issue as before, why not call that one function
> > and not reimplement it?
> >
> > Also, I don't think we'd ever swap an rmid for another valid one, right?
> > So we could do this read/update unconditionally.
>
> No, we never swap a valid RMID for another valid one, but we do make a
> invalid -> valid transition, so doing the read wouldn't make sense
> in that situation.
Ah indeed.
On Mon, Nov 10, 2014 at 08:56:53PM +0000, Matt Fleming wrote:
> > Should we initialize that to a finite value? Surely results are absolute
> > crap if we do indeed reach that max?
>
> I don't think we'll ever reach that max, it'll bottom out once it
> reaches the size of the LLC, since the pathological case is that the
> RMID you're currently trying to stabilize is used to tag every line in
> the LLC.
Sure, LLC size is the 'same'. Makes the entire ordeal rather pointless.
> Not sure what a reasonable finite value would be here though? 10% of the
> LLC size?
Can you ask the same Oracle that provided the magic 250 ms? Both are
magic/random numbers. 10% sounds rather large, but who knows.
On Fri, 07 Nov, at 01:34:31PM, Peter Zijlstra wrote:
> On Thu, Nov 06, 2014 at 12:23:21PM +0000, Matt Fleming wrote:
> > + min_queue_time = entry->queue_time +
> > + msecs_to_jiffies(__rotation_period);
> > +
> > + if (time_after(min_queue_time, now))
> > + continue;
>
> Why continue; this LRU is time ordered, later entries cannot be earlier,
> right?
Good point. We can just exit here.
> > + set_bit(entry->rmid, cqm_limbo_bitmap);
> > + set_bit(entry->rmid, cqm_free_bitmap);
> > + }
> > +
> > + /*
> > + * Fast return if none of the RMIDs on the limbo list have been
> > + * sitting on the queue for the minimum queue time.
> > + */
> > + *available = !bitmap_empty(cqm_limbo_bitmap, nr_bits);
> > + if (!*available)
> > + return false;
> > +
> > + /*
> > + * Test whether an RMID is free for each package.
> > + */
> > + preempt_disable();
> > + smp_call_function_many(&cqm_cpumask, intel_cqm_stable, NULL, true);
> > + preempt_enable();
>
> I don't get the whole list -> bitmap -> list juggle.
>
> enum rmid_cycle_state {
> RMID_AVAILABLE = 0,
> RMID_LIMBO,
> RMID_YOUNG,
> };
>
> struct cqm_rmid_entry {
> ...
> enum rmid_cycle_state state;
> };
>
> static void __intel_sqm_stable(void *arg)
> {
> list_for_each_entry(entry, &cqm_rmid_limbo_lru, list) {
> if (entry->state == RMID_YOUNG)
> break;
>
> if (__rmid_read(entry->rmid) > __threshold)
> entry->state = RMID_LIMBO;
> }
> }
>
> static bool intel_cqm_rmid_stabilize()
> {
> unsigned long queue_time = jiffies + msecs_to_jiffies(__rotation_period);
> unsigned int nr_limbo = 0;
> ...
>
> list_for_each_entry(entry, &cqm_rmid_limbo_lru, list) {
> if (time_after(entry->queue_time, queue_time))
> break;
>
> entry->state = RMID_AVAILABLE;
> nr_limbo++;
> }
>
> if (!nr_limbo)
> return;
>
> on_each_cpu_mask(&cqm_cpumask, __intel_cqm_stable, NULL, true);
>
> list_for_each_entry_safe(entry, tmp, &cqm_rmid_limbo_lru, list) {
> if (entry->state == RMID_YOUNG)
> break;
>
> if (entry->state == RMID_AVAILABLE)
> list_move(&cqm_rmid_free_list, &entry->list);
> }
> }
>
>
> Would not something like that work?
Actually, yeah, that does look like it'd work. Are you OK with me adding
an enum to the cqm_rmid_entry? You had concerns in the past about
growing the size of the struct.
--
Matt Fleming, Intel Open Source Technology Center
On Mon, Nov 10, 2014 at 09:31:40PM +0000, Matt Fleming wrote:
> Actually, yeah, that does look like it'd work. Are you OK with me adding
> an enum to the cqm_rmid_entry? You had concerns in the past about
> growing the size of the struct.
That was because I was thinking you did nr_rmid*sizeof(cqm_rmid_entry)
allocation, shortly thereafter I noticed you did a pointer alloc and
then allocated each individual entry.
Also, that enum can fit the hole you made there I think.
On Fri, 07 Nov, at 01:38:36PM, Peter Zijlstra wrote:
>
> For optional goodness:
>
> if (nr_limbo > max_scan_size)
> break;
>
> Which will limit the number of RMIDs you'll scan from the IPI, and
> thereby limit the time taken there.
To limit the amount of magic numbers we've got in this code, I'm going
to punt on this optional feature.
That is, unless you can provide a value for max_scan_size.
--
Matt Fleming, Intel Open Source Technology Center