The UV1 architecture is no longer being supported in future Linux kernels, so
remove UV1 specific code.
Signed-off-by: Mike Travis <[email protected]>
Reviewed-by: Dimitri Sivanich <[email protected]>
Tested-by: John Estabrook <[email protected]>
Tested-by: Gary Kroening <[email protected]>
---
arch/x86/include/asm/uv/uv_hub.h | 9 ------
arch/x86/kernel/apic/x2apic_uv_x.c | 53 ++-----------------------------------
arch/x86/platform/uv/tlb_uv.c | 2 -
arch/x86/platform/uv/uv_time.c | 3 --
4 files changed, 5 insertions(+), 62 deletions(-)
--- linux.orig/arch/x86/include/asm/uv/uv_hub.h
+++ linux/arch/x86/include/asm/uv/uv_hub.h
@@ -289,25 +289,21 @@ union uvh_apicid {
#define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024)
#define UV_LOCAL_MMR_BASE ( \
- is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \
is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \
is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \
/*is_uv4_hub*/ UV4_LOCAL_MMR_BASE)
#define UV_GLOBAL_MMR32_BASE ( \
- is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \
is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \
is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \
/*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE)
#define UV_LOCAL_MMR_SIZE ( \
- is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \
is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \
/*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE)
#define UV_GLOBAL_MMR32_SIZE ( \
- is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \
is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \
is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \
/*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE)
@@ -445,9 +441,6 @@ static inline int uv_apicid_to_pnode(int
*/
static inline int uv_apicid_to_socket(int apicid)
{
- if (is_uv1_hub())
- return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;
- else
return 0;
}
@@ -704,10 +697,8 @@ static inline void uv_set_cpu_scir_bits(
}
}
-extern unsigned int uv_apicid_hibits;
static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
{
- apicid |= uv_apicid_hibits;
return (1UL << UVH_IPI_INT_SEND_SHFT) |
((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
(mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
--- linux.orig/arch/x86/kernel/apic/x2apic_uv_x.c
+++ linux/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -39,8 +39,6 @@
#include <asm/x86_init.h>
#include <asm/nmi.h>
-DEFINE_PER_CPU(int, x2apic_extra_bits);
-
#define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
static enum uv_system_type uv_system_type;
@@ -50,8 +48,6 @@ static u64 gru_dist_lmask, gru_dist_umas
static union uvh_apicid uvh_apicid;
int uv_min_hub_revision_id;
EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
-unsigned int uv_apicid_hibits;
-EXPORT_SYMBOL_GPL(uv_apicid_hibits);
static struct apic apic_x2apic_uv_x;
@@ -140,23 +136,6 @@ static void __init early_get_apic_pnode_
uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
}
-/*
- * Add an extra bit as dictated by bios to the destination apicid of
- * interrupts potentially passing through the UV HUB. This prevents
- * a deadlock between interrupts and IO port operations.
- */
-static void __init uv_set_apicid_hibit(void)
-{
- union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
-
- if (is_uv1_hub()) {
- apicid_mask.v =
- uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
- uv_apicid_hibits =
- apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
- }
-}
-
static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
int pnodeid;
@@ -189,14 +168,6 @@ static int __init uv_acpi_madt_oem_check
if (!strcmp(oem_table_id, "UVX")) { /* most common */
uv_system_type = UV_X2APIC;
uv_apic = 0;
-
- } else if (!strcmp(oem_table_id, "UVH")) { /* only UV1 systems */
- uv_system_type = UV_NON_UNIQUE_APIC;
- __this_cpu_write(x2apic_extra_bits,
- pnodeid << uvh_apicid.s.pnode_shift);
- uv_set_apicid_hibit();
- uv_apic = 1;
-
} else if (!strcmp(oem_table_id, "UVL")) { /* only used for */
uv_system_type = UV_LEGACY_APIC; /* very small systems */
uv_apic = 0;
@@ -252,7 +223,6 @@ static int uv_wakeup_secondary(int phys_
int pnode;
pnode = uv_apicid_to_pnode(phys_apicid);
- phys_apicid |= uv_apicid_hibits;
val = (1UL << UVH_IPI_INT_SEND_SHFT) |
(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
@@ -344,7 +314,7 @@ uv_cpu_mask_to_apicid_and(const struct c
}
if (likely(cpu < nr_cpu_ids)) {
- *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
+ *apicid = per_cpu(x86_cpu_to_apicid, cpu);
return 0;
}
@@ -353,21 +323,12 @@ uv_cpu_mask_to_apicid_and(const struct c
static unsigned int x2apic_get_apic_id(unsigned long x)
{
- unsigned int id;
-
- WARN_ON(preemptible() && num_online_cpus() > 1);
- id = x | __this_cpu_read(x2apic_extra_bits);
-
- return id;
+ return x;
}
static unsigned long set_apic_id(unsigned int id)
{
- unsigned long x;
-
- /* maskout x2apic_extra_bits ? */
- x = id;
- return x;
+ return id;
}
static unsigned int uv_read_apic_id(void)
@@ -442,11 +403,6 @@ static struct apic __refdata apic_x2apic
.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
};
-static void set_x2apic_extra_bits(int pnode)
-{
- __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
-}
-
/*
* Called on boot cpu.
*/
@@ -878,9 +834,6 @@ void uv_cpu_init(void)
return;
uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
-
- if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
- set_x2apic_extra_bits(uv_hub_info->pnode);
}
struct mn {
--- linux.orig/arch/x86/platform/uv/tlb_uv.c
+++ linux/arch/x86/platform/uv/tlb_uv.c
@@ -1834,7 +1834,7 @@ static void __init init_uvhub(int uvhub,
* The below initialization can't be in firmware because the
* messaging IRQ will be determined by the OS.
*/
- apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
+ apicid = uvhub_to_first_apicid(uvhub);
write_mmr_data_config(pnode, ((apicid << 32) | vector));
}
--- linux.orig/arch/x86/platform/uv/uv_time.c
+++ linux/arch/x86/platform/uv/uv_time.c
@@ -87,7 +87,6 @@ static void uv_rtc_send_IPI(int cpu)
apicid = cpu_physical_id(cpu);
pnode = uv_apicid_to_pnode(apicid);
- apicid |= uv_apicid_hibits;
val = (1UL << UVH_IPI_INT_SEND_SHFT) |
(apicid << UVH_IPI_INT_APIC_ID_SHFT) |
(X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
@@ -111,7 +110,7 @@ static int uv_intr_pending(int pnode)
static int uv_setup_intr(int cpu, u64 expires)
{
u64 val;
- unsigned long apicid = cpu_physical_id(cpu) | uv_apicid_hibits;
+ unsigned long apicid = cpu_physical_id(cpu);
int pnode = uv_cpu_to_pnode(cpu);
uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
--
* Mike Travis <[email protected]> wrote:
> The UV1 architecture is no longer being supported in future Linux kernels, so
Is such hardware still out there? If yes then please don't break it.
You might not want to test it, and if no-one else does it will eventually and
inevitably bit rot, but please don't intentionally cripple it ..
Thanks,
Ingo
Hi Ingo,
I updated that patch to not remove any code, but instead there is now a
config option to enable or disable UV1 support, as well as an config help
message on why that might be done. I also addressed the other issues
you raised in the following 2 emails. And I found out that the newer
"checkpatches" script also had some new "concerns". I was able to fix
all that were possible (or practical).
The patches follow...
Thanks!
Mike
On 4/28/2016 1:48 AM, Ingo Molnar wrote:
>
> * Mike Travis <[email protected]> wrote:
>
>> The UV1 architecture is no longer being supported in future Linux kernels, so
>
> Is such hardware still out there? If yes then please don't break it.
>
> You might not want to test it, and if no-one else does it will eventually and
> inevitably bit rot, but please don't intentionally cripple it ..
>
> Thanks,
>
> Ingo
>