2017-12-06 12:13:59

by Srinivas Kandagatla

Subject: [PATCH 0/2] clk: qcom: gcc-msm8916: codec digital clk fixes

From: Srinivas Kandagatla <[email protected]>

Hi Stephen,

Found few issues while trying to set 12.288MHz on codec digital clk.
One is to do with missing mnd_width and other is missing clk entry.

thanks,
srini

Srinivas Kandagatla (2):
clk: qcom: msm8916: fix mnd_width for codec_digcodec
clk: qcom: msm8916: add 12.288 MHz support to codec dig clk

drivers/clk/qcom/gcc-msm8916.c | 2 ++
1 file changed, 2 insertions(+)

--
2.15.0

2017-12-06 12:14:01

by Srinivas Kandagatla

Subject: [PATCH 1/2] clk: qcom: msm8916: fix mnd_width for codec_digcodec

From: Srinivas Kandagatla <[email protected]>

This patch fixes missing mnd_width for codec_digital clk, this is now set to
8 inline with datasheet.

Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support")
Signed-off-by: Srinivas Kandagatla <[email protected]>
---
drivers/clk/qcom/gcc-msm8916.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 506e0736bf92..d973aeaab943 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -1443,6 +1443,7 @@ static const struct freq_tbl ftbl_codec_clk[] = {

static struct clk_rcg2 codec_digcodec_clk_src = {
.cmd_rcgr = 0x1c09c,
+ .mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll1_emclk_sleep_map,
.freq_tbl = ftbl_codec_clk,
--
2.15.0

2017-12-06 12:14:29

by Srinivas Kandagatla

Subject: [PATCH 2/2] clk: qcom: msm8916: add 12.288 MHz support to codec dig clk

From: Srinivas Kandagatla <[email protected]>

This patch adds 12.288 MHz suport to codec digital clk, this clock.
Some external PA requires a 12.288 MHz to work.

Signed-off-by: Srinivas Kandagatla <[email protected]>
---
drivers/clk/qcom/gcc-msm8916.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index d973aeaab943..d6c7f50ba86a 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -1436,6 +1436,7 @@ static struct clk_branch gcc_ultaudio_stc_xo_clk = {

static const struct freq_tbl ftbl_codec_clk[] = {
F(9600000, P_XO, 2, 0, 0),
+ F(12288000, P_XO, 1, 16, 25),
F(19200000, P_XO, 1, 0, 0),
F(11289600, P_EXT_MCLK, 1, 0, 0),
{ }
--
2.15.0

2017-12-07 06:34:45

by Stephen Boyd

Subject: Re: [PATCH 1/2] clk: qcom: msm8916: fix mnd_width for codec_digcodec

On 12/06, [email protected] wrote:
> From: Srinivas Kandagatla <[email protected]>
>
> This patch fixes missing mnd_width for codec_digital clk, this is now set to
> 8 inline with datasheet.
>
> Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support")
> Signed-off-by: Srinivas Kandagatla <[email protected]>
> ---

Applied to clk-next

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

2017-12-07 06:34:32

by Stephen Boyd

Subject: Re: [PATCH 2/2] clk: qcom: msm8916: add 12.288 MHz support to codec dig clk

On 12/06, [email protected] wrote:
> From: Srinivas Kandagatla <[email protected]>
>
> This patch adds 12.288 MHz suport to codec digital clk, this clock.
> Some external PA requires a 12.288 MHz to work.
>
> Signed-off-by: Srinivas Kandagatla <[email protected]>
> ---

Applied to clk-next

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project