2018-04-13 02:33:10

by Sinan Kaya

[permalink] [raw]
Subject: [PATCH v4 1/2] MIPS: io: prevent compiler reordering on the default writeX() implementation

writeX() has a strong ordering semantics with respect to memory updates.
In the abscence of a write barrier or a compiler barrier, commpiler can
reorder register and memory update instructions. This breaks the writeX()
API.

Signed-off-by: Sinan Kaya <[email protected]>
---
arch/mips/include/asm/io.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 0cbf3af..fd00ddaf 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -307,7 +307,7 @@ static inline void iounmap(const volatile void __iomem *addr)
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
#define war_io_reorder_wmb() wmb()
#else
-#define war_io_reorder_wmb() do { } while (0)
+#define war_io_reorder_wmb() barrier()
#endif

#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
--
2.7.4



2018-04-13 03:02:46

by Sinan Kaya

[permalink] [raw]
Subject: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

While a barrier is present in writeX() function before the register write,
a similar barrier is missing in the readX() function after the register
read. This could allow memory accesses following readX() to observe
stale data.

Signed-off-by: Sinan Kaya <[email protected]>
Reported-by: Arnd Bergmann <[email protected]>
---
arch/mips/include/asm/io.h | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index fd00ddaf..d96af41 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
BUG(); \
} \
\
+ /* prevent prefetching of coherent DMA dma prematurely */ \
+ rmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}

--
2.7.4


2018-04-13 03:35:45

by Sinan Kaya

[permalink] [raw]
Subject: Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> + /* prevent prefetching of coherent DMA dma prematurely */ \

I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
posting another version until I hear back from you for wmb().

--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.

2018-04-13 23:54:00

by James Hogan

[permalink] [raw]
Subject: Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

On Thu, Apr 12, 2018 at 10:33:42PM -0400, Sinan Kaya wrote:
> On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> > + /* prevent prefetching of coherent DMA dma prematurely */ \
>
> I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
> posting another version until I hear back from you for wmb().

No problem, I've applied both for 4.17 and tweaked the comment.

Thanks
James


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