This allows panels or bridges that need to send DSI commands during
pre_enable() to successfully send them. We delay DISP0 (aka the
actual display) enabling until after pre_enable so that pixels aren't
streaming before then.
v2: Just clear out the encoder->bridge value to disable the midlayer
calls (idea by Andrzej Hajda).
Signed-off-by: Eric Anholt <[email protected]>
Cc: Andrzej Hajda <[email protected]>
---
drivers/gpu/drm/vc4/vc4_dsi.c | 42 ++++++++++++++++++++++-------------
1 file changed, 27 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
index 8aa897835118..9c8e89372d1c 100644
--- a/drivers/gpu/drm/vc4/vc4_dsi.c
+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
@@ -814,7 +814,9 @@ static void vc4_dsi_encoder_disable(struct drm_encoder *encoder)
struct vc4_dsi *dsi = vc4_encoder->dsi;
struct device *dev = &dsi->pdev->dev;
+ drm_bridge_disable(dsi->bridge);
vc4_dsi_ulps(dsi, true);
+ drm_bridge_post_disable(dsi->bridge);
clk_disable_unprepare(dsi->pll_phy_clock);
clk_disable_unprepare(dsi->escape_clock);
@@ -1089,21 +1091,6 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
/* Display reset sequence timeout */
DSI_PORT_WRITE(PR_TO_CNT, 100000);
- if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
- DSI_PORT_WRITE(DISP0_CTRL,
- VC4_SET_FIELD(dsi->divider,
- DSI_DISP0_PIX_CLK_DIV) |
- VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
- VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
- DSI_DISP0_LP_STOP_CTRL) |
- DSI_DISP0_ST_END |
- DSI_DISP0_ENABLE);
- } else {
- DSI_PORT_WRITE(DISP0_CTRL,
- DSI_DISP0_COMMAND_MODE |
- DSI_DISP0_ENABLE);
- }
-
/* Set up DISP1 for transferring long command payloads through
* the pixfifo.
*/
@@ -1128,6 +1115,25 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
vc4_dsi_ulps(dsi, false);
+ drm_bridge_pre_enable(dsi->bridge);
+
+ if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
+ DSI_PORT_WRITE(DISP0_CTRL,
+ VC4_SET_FIELD(dsi->divider,
+ DSI_DISP0_PIX_CLK_DIV) |
+ VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
+ VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
+ DSI_DISP0_LP_STOP_CTRL) |
+ DSI_DISP0_ST_END |
+ DSI_DISP0_ENABLE);
+ } else {
+ DSI_PORT_WRITE(DISP0_CTRL,
+ DSI_DISP0_COMMAND_MODE |
+ DSI_DISP0_ENABLE);
+ }
+
+ drm_bridge_enable(dsi->bridge);
+
if (debug_dump_regs) {
DRM_INFO("DSI regs after:\n");
vc4_dsi_dump_regs(dsi);
@@ -1639,6 +1645,12 @@ static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
dev_err(dev, "bridge attach failed: %d\n", ret);
return ret;
}
+ /* Disable the atomic helper calls into the bridge. We
+ * manually call the bridge pre_enable / enable / etc. calls
+ * from our driver, since we need to sequence them within the
+ * encoder's enable/disable paths.
+ */
+ dsi->encoder->bridge = NULL;
pm_runtime_enable(dev);
--
2.18.0.rc2
On 22.06.2018 01:17, Eric Anholt wrote:
> This allows panels or bridges that need to send DSI commands during
> pre_enable() to successfully send them. We delay DISP0 (aka the
> actual display) enabling until after pre_enable so that pixels aren't
> streaming before then.
>
> v2: Just clear out the encoder->bridge value to disable the midlayer
> calls (idea by Andrzej Hajda).
>
> Signed-off-by: Eric Anholt <[email protected]>
> Cc: Andrzej Hajda <[email protected]>
Reviewed-by: Andrzej Hajda <[email protected]>
--
Regards
Andrzej
> ---
> drivers/gpu/drm/vc4/vc4_dsi.c | 42 ++++++++++++++++++++++-------------
> 1 file changed, 27 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
> index 8aa897835118..9c8e89372d1c 100644
> --- a/drivers/gpu/drm/vc4/vc4_dsi.c
> +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
> @@ -814,7 +814,9 @@ static void vc4_dsi_encoder_disable(struct drm_encoder *encoder)
> struct vc4_dsi *dsi = vc4_encoder->dsi;
> struct device *dev = &dsi->pdev->dev;
>
> + drm_bridge_disable(dsi->bridge);
> vc4_dsi_ulps(dsi, true);
> + drm_bridge_post_disable(dsi->bridge);
>
> clk_disable_unprepare(dsi->pll_phy_clock);
> clk_disable_unprepare(dsi->escape_clock);
> @@ -1089,21 +1091,6 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
> /* Display reset sequence timeout */
> DSI_PORT_WRITE(PR_TO_CNT, 100000);
>
> - if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
> - DSI_PORT_WRITE(DISP0_CTRL,
> - VC4_SET_FIELD(dsi->divider,
> - DSI_DISP0_PIX_CLK_DIV) |
> - VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
> - VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
> - DSI_DISP0_LP_STOP_CTRL) |
> - DSI_DISP0_ST_END |
> - DSI_DISP0_ENABLE);
> - } else {
> - DSI_PORT_WRITE(DISP0_CTRL,
> - DSI_DISP0_COMMAND_MODE |
> - DSI_DISP0_ENABLE);
> - }
> -
> /* Set up DISP1 for transferring long command payloads through
> * the pixfifo.
> */
> @@ -1128,6 +1115,25 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
>
> vc4_dsi_ulps(dsi, false);
>
> + drm_bridge_pre_enable(dsi->bridge);
> +
> + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
> + DSI_PORT_WRITE(DISP0_CTRL,
> + VC4_SET_FIELD(dsi->divider,
> + DSI_DISP0_PIX_CLK_DIV) |
> + VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
> + VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
> + DSI_DISP0_LP_STOP_CTRL) |
> + DSI_DISP0_ST_END |
> + DSI_DISP0_ENABLE);
> + } else {
> + DSI_PORT_WRITE(DISP0_CTRL,
> + DSI_DISP0_COMMAND_MODE |
> + DSI_DISP0_ENABLE);
> + }
> +
> + drm_bridge_enable(dsi->bridge);
> +
> if (debug_dump_regs) {
> DRM_INFO("DSI regs after:\n");
> vc4_dsi_dump_regs(dsi);
> @@ -1639,6 +1645,12 @@ static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
> dev_err(dev, "bridge attach failed: %d\n", ret);
> return ret;
> }
> + /* Disable the atomic helper calls into the bridge. We
> + * manually call the bridge pre_enable / enable / etc. calls
> + * from our driver, since we need to sequence them within the
> + * encoder's enable/disable paths.
> + */
> + dsi->encoder->bridge = NULL;
>
> pm_runtime_enable(dev);
>