LinuxLists.cc - [PATCH 0/2] Add clock driver for Actions S700 SoC

2018-06-27 00:43:43

Subject: [PATCH 0/2] Add clock driver for Actions S700 SoC

This patchset adds clock support for Actions Semi OWL series
S700 SoC with relevant clock bindings and device tree info.

Changed the UART clock using CMU instance and changes are
tested in cubieboard7

Thanks and regards,
Saravanan,
Parthiban

Saravanan Sekar (2):
arm64: dts: actions: Enable clock controller for S700
clk: actions: Add S700 SoC clock support

.../boot/dts/actions/s700-cubieboard7.dts | 7 -
arch/arm64/boot/dts/actions/s700.dtsi | 8 +
drivers/clk/actions/Kconfig | 7 +
drivers/clk/actions/Makefile | 1 +
drivers/clk/actions/owl-s700.c | 614 ++++++++++++++++++
include/dt-bindings/clock/actions,s700-cmu.h | 128 ++++
6 files changed, 758 insertions(+), 7 deletions(-)
create mode 100644 drivers/clk/actions/owl-s700.c
create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h

--
2.18.0

2018-06-26 19:32:55

by saravanan sekar

[permalink] [raw]

Subject: [PATCH 1/2] arm64: dts: actions: Enable clock controller for S700

Added clock management controller for S700

Signed-off-by: Parthiban Nallathambi <[email protected]>
Signed-off-by: Saravanan Sekar <[email protected]>
---
.../boot/dts/actions/s700-cubieboard7.dts | 7 -
arch/arm64/boot/dts/actions/s700.dtsi | 8 ++
include/dt-bindings/clock/actions,s700-cmu.h | 128 ++++++++++++++++++
3 files changed, 136 insertions(+), 7 deletions(-)
create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h

diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
index ef79d7905f44..28f3f4a0f7f0 100644
--- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
+++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
@@ -28,12 +28,6 @@
device_type = "memory";
reg = <0x1 0xe0000000 0x0 0x0>;
};
-
- uart3_clk: uart3-clk {
- compatible = "fixed-clock";
- clock-frequency = <921600>;
- #clock-cells = <0>;
- };
};

&timer {
@@ -42,5 +36,4 @@

&uart3 {
status = "okay";
- clocks = <&uart3_clk>;
};
diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
index 66dd5309f0a2..3530b705df90 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -4,6 +4,7 @@
*/

#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/actions,s700-cmu.h>

/ {
compatible = "actions,s700";
@@ -44,6 +45,12 @@
};
};

+ clock: clock-controller@e0168000 {
+ compatible = "actions,s700-cmu";
+ reg = <0 0xe0168000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -129,6 +136,7 @@
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0126000 0x0 0x2000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_UART3>;
status = "disabled";
};

diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
new file mode 100644
index 000000000000..e5b4ea130953
--- /dev/null
+++ b/include/dt-bindings/clock/actions,s700-cmu.h
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions S700 clock driver
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <[email protected]>
+ *
+ * Author: Pathiban Nallathambi <[email protected]>
+ * Author: Saravanan Sekar <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S700_H
+#define __DT_BINDINGS_CLOCK_S700_H
+
+#define CLK_NONE 0
+
+/* fixed rate clocks */
+#define CLK_LOSC 1
+#define CLK_HOSC 2
+
+/* pll clocks */
+#define CLK_CORE_PLL 3
+#define CLK_DEV_PLL 4
+#define CLK_DDR_PLL 5
+#define CLK_NAND_PLL 6
+#define CLK_DISPLAY_PLL 7
+#define CLK_TVOUT_PLL 8
+#define CLK_CVBS_PLL 9
+#define CLK_AUDIO_PLL 10
+#define CLK_ETHERNET_PLL 11
+
+
+/* system clock */
+#define CLK_SYS_BASE 12
+#define CLK_CPU CLK_SYS_BASE
+#define CLK_DEV (CLK_SYS_BASE+1)
+#define CLK_AHB (CLK_SYS_BASE+2)
+#define CLK_APB (CLK_SYS_BASE+3)
+#define CLK_DMAC (CLK_SYS_BASE+4)
+#define CLK_NOC0_CLK_MUX (CLK_SYS_BASE+5)
+#define CLK_NOC1_CLK_MUX (CLK_SYS_BASE+6)
+#define CLK_HP_CLK_MUX (CLK_SYS_BASE+7)
+#define CLK_HP_CLK_DIV (CLK_SYS_BASE+8)
+#define CLK_NOC1_CLK_DIV (CLK_SYS_BASE+9)
+#define CLK_NOC0 (CLK_SYS_BASE+10)
+#define CLK_NOC1 (CLK_SYS_BASE+11)
+#define CLK_SENOR_SRC (CLK_SYS_BASE+12)
+
+/* peripheral device clock */
+#define CLK_PERIP_BASE 25
+#define CLK_GPIO (CLK_PERIP_BASE)
+#define CLK_TIMER (CLK_PERIP_BASE+1)
+#define CLK_DSI (CLK_PERIP_BASE+2)
+#define CLK_CSI (CLK_PERIP_BASE+3)
+#define CLK_SI (CLK_PERIP_BASE+4)
+#define CLK_DE (CLK_PERIP_BASE+5)
+#define CLK_HDE (CLK_PERIP_BASE+6)
+#define CLK_VDE (CLK_PERIP_BASE+7)
+#define CLK_VCE (CLK_PERIP_BASE+8)
+#define CLK_NAND (CLK_PERIP_BASE+9)
+#define CLK_SD0 (CLK_PERIP_BASE+10)
+#define CLK_SD1 (CLK_PERIP_BASE+11)
+#define CLK_SD2 (CLK_PERIP_BASE+12)
+
+#define CLK_UART0 (CLK_PERIP_BASE+13)
+#define CLK_UART1 (CLK_PERIP_BASE+14)
+#define CLK_UART2 (CLK_PERIP_BASE+15)
+#define CLK_UART3 (CLK_PERIP_BASE+16)
+#define CLK_UART4 (CLK_PERIP_BASE+17)
+#define CLK_UART5 (CLK_PERIP_BASE+18)
+#define CLK_UART6 (CLK_PERIP_BASE+19)
+
+#define CLK_PWM0 (CLK_PERIP_BASE+20)
+#define CLK_PWM1 (CLK_PERIP_BASE+21)
+#define CLK_PWM2 (CLK_PERIP_BASE+22)
+#define CLK_PWM3 (CLK_PERIP_BASE+23)
+#define CLK_PWM4 (CLK_PERIP_BASE+24)
+#define CLK_PWM5 (CLK_PERIP_BASE+25)
+#define CLK_GPU3D (CLK_PERIP_BASE+26)
+
+#define CLK_I2C0 (CLK_PERIP_BASE+27)
+#define CLK_I2C1 (CLK_PERIP_BASE+28)
+#define CLK_I2C2 (CLK_PERIP_BASE+29)
+#define CLK_I2C3 (CLK_PERIP_BASE+30)
+
+
+#define CLK_SPI0 (CLK_PERIP_BASE+31)
+#define CLK_SPI1 (CLK_PERIP_BASE+32)
+#define CLK_SPI2 (CLK_PERIP_BASE+33)
+#define CLK_SPI3 (CLK_PERIP_BASE+34)
+
+#define CLK_USB3_480MPLL0 (CLK_PERIP_BASE+35)
+#define CLK_USB3_480MPHY0 (CLK_PERIP_BASE+36)
+#define CLK_USB3_5GPHY (CLK_PERIP_BASE+37)
+#define CLK_USB3_CCE (CLK_PERIP_BASE+48)
+#define CLK_USB3_MAC (CLK_PERIP_BASE+49)
+
+
+#define CLK_LCD (CLK_PERIP_BASE+50)
+#define CLK_HDMI_AUDIO (CLK_PERIP_BASE+51)
+#define CLK_I2SRX (CLK_PERIP_BASE+52)
+#define CLK_I2STX (CLK_PERIP_BASE+53)
+
+#define CLK_SENSOR0 (CLK_PERIP_BASE+54)
+#define CLK_SENSOR1 (CLK_PERIP_BASE+55)
+
+#define CLK_HDMI_DEV (CLK_PERIP_BASE+56)
+
+#define CLK_ETHERNET (CLK_PERIP_BASE+59)
+#define CLK_RMII_REF (CLK_PERIP_BASE+60)
+
+#define CLK_USB2H0_PLLEN (CLK_PERIP_BASE+61)
+#define CLK_USB2H0_PHY (CLK_PERIP_BASE+62)
+#define CLK_USB2H0_CCE (CLK_PERIP_BASE+63)
+#define CLK_USB2H1_PLLEN (CLK_PERIP_BASE+64)
+#define CLK_USB2H1_PHY (CLK_PERIP_BASE+65)
+#define CLK_USB2H1_CCE (CLK_PERIP_BASE+66)
+
+
+#define CLK_TVOUT (CLK_PERIP_BASE+67)
+
+#define CLK_THERMAL_SENSOR (CLK_PERIP_BASE+68)
+
+#define CLK_IRC_SWITCH (CLK_PERIP_BASE+69)
+#define CLK_PCM1 (CLK_PERIP_BASE+70)
+#define CLK_NR_CLKS (CLK_PCM1) /* update on adding new clk */
+
+#endif /* __DT_BINDINGS_CLOCK_S700_H */
--
2.18.0

2018-06-26 23:55:57

by saravanan sekar

[permalink] [raw]

Subject: [PATCH 2/2] clk: actions: Add S700 SoC clock support

Add Actions Semi S700 SoC clock support

Signed-off-by: Parthiban Nallathambi <[email protected]>
Signed-off-by: Saravanan Sekar <[email protected]>
---
drivers/clk/actions/Kconfig | 7 +
drivers/clk/actions/Makefile | 1 +
drivers/clk/actions/owl-s700.c | 614 +++++++++++++++++++++++++++++++++
3 files changed, 622 insertions(+)
create mode 100644 drivers/clk/actions/owl-s700.c

diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig
index 8854adb37847..d883b48e4607 100644
--- a/drivers/clk/actions/Kconfig
+++ b/drivers/clk/actions/Kconfig
@@ -1,6 +1,7 @@
config CLK_ACTIONS
bool "Clock driver for Actions Semi SoCs"
depends on ARCH_ACTIONS || COMPILE_TEST
+ select REGMAP_MMIO
default ARCH_ACTIONS

if CLK_ACTIONS
@@ -11,4 +12,10 @@ config CLK_OWL_S900
bool "Support for the Actions Semi OWL S900 clocks"
depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
default ARM64 && ARCH_ACTIONS
+
+config CLK_OWL_S700
+ bool "Support for the Actions Semi OWL S700 clocks"
+ depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
+ default ARM64 && ARCH_ACTIONS
+
endif
diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
index 76e431434d10..a860973d940d 100644
--- a/drivers/clk/actions/Makefile
+++ b/drivers/clk/actions/Makefile
@@ -9,4 +9,5 @@ clk-owl-y += owl-composite.o
clk-owl-y += owl-pll.o

# SoC support
+obj-$(CONFIG_CLK_OWL_S900) += owl-s700.o
obj-$(CONFIG_CLK_OWL_S900) += owl-s900.o
diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c
new file mode 100644
index 000000000000..36aee2477251
--- /dev/null
+++ b/drivers/clk/actions/owl-s700.c
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions S700 clock driver
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <[email protected]>
+ *
+ * Author: Pathiban Nallathambi <[email protected]>
+ * Author: Saravanan Sekar <[email protected]>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "owl-common.h"
+#include "owl-composite.h"
+#include "owl-divider.h"
+#include "owl-factor.h"
+#include "owl-fixed-factor.h"
+#include "owl-gate.h"
+#include "owl-mux.h"
+#include "owl-pll.h"
+
+#include <dt-bindings/clock/actions,s700-cmu.h>
+
+#define CMU_COREPLL (0x0000)
+#define CMU_DEVPLL (0x0004)
+#define CMU_DDRPLL (0x0008)
+#define CMU_NANDPLL (0x000C)
+#define CMU_DISPLAYPLL (0x0010)
+#define CMU_AUDIOPLL (0x0014)
+#define CMU_TVOUTPLL (0x0018)
+#define CMU_BUSCLK (0x001C)
+#define CMU_SENSORCLK (0x0020)
+#define CMU_LCDCLK (0x0024)
+#define CMU_DSIPLLCLK (0x0028)
+#define CMU_CSICLK (0x002C)
+#define CMU_DECLK (0x0030)
+#define CMU_SICLK (0x0034)
+#define CMU_BUSCLK1 (0x0038)
+#define CMU_HDECLK (0x003C)
+#define CMU_VDECLK (0x0040)
+#define CMU_VCECLK (0x0044)
+#define CMU_NANDCCLK (0x004C)
+#define CMU_SD0CLK (0x0050)
+#define CMU_SD1CLK (0x0054)
+#define CMU_SD2CLK (0x0058)
+#define CMU_UART0CLK (0x005C)
+#define CMU_UART1CLK (0x0060)
+#define CMU_UART2CLK (0x0064)
+#define CMU_UART3CLK (0x0068)
+#define CMU_UART4CLK (0x006C)
+#define CMU_UART5CLK (0x0070)
+#define CMU_UART6CLK (0x0074)
+#define CMU_PWM0CLK (0x0078)
+#define CMU_PWM1CLK (0x007C)
+#define CMU_PWM2CLK (0x0080)
+#define CMU_PWM3CLK (0x0084)
+#define CMU_PWM4CLK (0x0088)
+#define CMU_PWM5CLK (0x008C)
+#define CMU_GPU3DCLK (0x0090)
+#define CMU_CORECTL (0x009C)
+#define CMU_DEVCLKEN0 (0x00A0)
+#define CMU_DEVCLKEN1 (0x00A4)
+#define CMU_DEVRST0 (0x00A8)
+#define CMU_DEVRST1 (0x00AC)
+#define CMU_USBPLL (0x00B0)
+#define CMU_ETHERNETPLL (0x00B4)
+#define CMU_CVBSPLL (0x00B8)
+#define CMU_SSTSCLK (0x00C0)
+
+static struct clk_pll_table clk_audio_pll_table[] = {
+ {0, 45158400}, {1, 49152000},
+ {0, 0},
+};
+
+static struct clk_pll_table clk_cvbs_pll_table[] = {
+ {27, 29*12000000}, {28, 30*12000000}, {29, 31*12000000},
+ {30, 32*12000000}, {31, 33*12000000}, {32, 34*12000000},
+ {33, 35*12000000}, {34, 36*12000000}, {35, 37*12000000},
+ {36, 38*12000000}, {37, 39*12000000}, {38, 40*12000000},
+ {39, 41*12000000}, {40, 42*12000000}, {41, 43*12000000},
+ {42, 44*12000000}, {43, 45*12000000}, {0, 0},
+};
+
+/* pll clocks */
+static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
+
+
+static const char *cpu_clk_mux_p[] __initconst = {"losc", "hosc", "core_pll", "noc1_clk_div"};
+static const char *dev_clk_p[] __initconst = { "hosc", "dev_pll"};
+static const char *noc_clk_mux_p[] __initconst = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"};
+
+static const char *csi_clk_mux_p[] __initconst = { "display_pll", "dev_clk"};
+static const char *de_clk_mux_p[] __initconst = { "display_pll", "dev_clk"};
+static const char *hde_clk_mux_p[] __initconst = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"};
+static const char *nand_clk_mux_p[] __initconst = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"};
+static const char *sd_clk_mux_p[] __initconst = { "dev_clk", "nand_pll", };
+static const char *uart_clk_mux_p[] __initconst = { "hosc", "dev_pll"};
+static const char *pwm_clk_mux_p[] __initconst = { "losc", "hosc"};
+static const char *gpu_clk_mux_p[] __initconst = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"};
+static const char *lcd_clk_mux_p[] __initconst = { "display_pll", "dev_clk" };
+static const char *i2s_clk_mux_p[] __initconst = { "audio_pll" };
+static const char *sensor_clk_mux_p[] __initconst = { "hosc", "si"};
+
+
+/* mux clocks */
+static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
+static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
+static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT);
+static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT);
+static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
+
+static struct clk_factor_table sd_factor_table[] = {
+ /* bit0 ~ 4 */
+ {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
+ {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
+ {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
+ {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16},
+ {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20},
+ {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24},
+ {24, 1, 25}, {25, 1, 26},
+
+ /* bit8: /128 */
+ {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128},
+ {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128},
+ {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128},
+ {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128},
+ {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128},
+ {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
+ {280, 1, 25 * 128}, {281, 1, 26 * 128},
+
+ {0, 0},
+};
+
+static struct clk_factor_table lcd_factor_table[] = {
+ /* bit0 ~ 3 */
+ {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
+ {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
+ {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
+
+ /* bit8: /7 */
+ {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
+ {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
+ {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
+ {0, 0},
+};
+
+
+static struct clk_div_table hdmia_div_table[] = {
+ {0, 1}, {1, 2}, {2, 3}, {3, 4},
+ {4, 6}, {5, 8}, {6, 12}, {7, 16},
+ {8, 24},
+ {0, 0},
+};
+
+static struct clk_div_table rmii_div_table[] = {
+ {0, 4}, {1, 10},
+};
+
+
+/* divider clocks */
+static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0);
+static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0);
+static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0);
+static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
+static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
+static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
+static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0);
+static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0);
+static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0);
+
+static struct clk_factor_table de_factor_table[] = {
+ {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
+ {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
+ {8, 1, 12}, {0, 0, 0},
+};
+
+static struct clk_factor_table hde_factor_table[] = {
+ {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
+ {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
+ {0, 0, 0},
+};
+
+/* gate clocks */
+static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0);
+static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0);
+static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
+static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0);
+static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0);
+static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0);
+static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0);
+static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0);
+static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0);
+static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
+static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0);
+static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0);
+static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0);
+static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0);
+static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0);
+
+/* composite clocks */
+
+static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p,
+ OWL_MUX_HW(CMU_CSICLK, 4, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
+ OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p,
+ OWL_MUX_HW(CMU_SICLK, 4, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
+ OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
+ 0);
+
+static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p,
+ OWL_MUX_HW(CMU_DECLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
+ OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p,
+ OWL_MUX_HW(CMU_HDECLK, 4, 2),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
+ OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p,
+ OWL_MUX_HW(CMU_VDECLK, 4, 2),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
+ OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p,
+ OWL_MUX_HW(CMU_VCECLK, 4, 2),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
+ OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
+ 0);
+
+static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p,
+ OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
+ OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
+ CLK_SET_RATE_PARENT);
+
+static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p,
+ OWL_MUX_HW(CMU_SD0CLK, 9, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
+ OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p,
+ OWL_MUX_HW(CMU_SD1CLK, 9, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
+ OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p,
+ OWL_MUX_HW(CMU_SD2CLK, 9, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0),
+ OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
+#ifdef CONFIG_MMC_OWL_CLK_NANDPLL
+ CLK_SET_RATE_PARENT);
+#else
+ 0);
+#endif
+
+static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART0CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
+ OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART1CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0),
+ OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART2CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0),
+ OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART3CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0),
+ OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART4CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0),
+ OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART5CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0),
+ OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART6CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
+ OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0),
+ OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
+ CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
+ OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
+ OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
+ OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
+ OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
+ OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
+ 0);
+
+static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p,
+ OWL_MUX_HW(CMU_GPU3DCLK, 4, 3),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
+ OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p,
+ OWL_MUX_HW(CMU_LCDCLK, 12, 2),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0),
+ OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table),
+ 0);
+
+static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p,
+ OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),/*CMU_AUDIOPLL 24,1 unused*/
+ OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0),
+ OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
+ 0);
+
+static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p,
+ OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0),
+ OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
+ 0);
+
+static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p,
+ OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
+ OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
+ 0);
+
+/* for bluetooth pcm communication */
+static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll",
+ OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
+ 1, 2, 0);
+
+static OWL_COMP_DIV(clk_senor_src, "sensor_src", sensor_clk_mux_p,
+ OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
+ {0},
+ OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
+ 0);
+
+static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll",
+ OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
+ 1, 20, 0);
+
+static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc",
+ OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0),
+ OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),
+ 0);
+
+static struct owl_clk_common *s700_clks[] = {
+ &clk_core_pll.common,
+ &clk_dev_pll.common,
+ &clk_ddr_pll.common,
+ &clk_nand_pll.common,
+ &clk_display_pll.common,
+ &clk_cvbs_pll .common,
+ &clk_audio_pll.common,
+ &clk_ethernet_pll.common,
+ &clk_cpu.common,
+ &clk_dev.common,
+ &clk_ahb.common,
+ &clk_apb.common,
+ &clk_dmac.common,
+ &clk_noc0_clk_mux.common,
+ &clk_noc1_clk_mux.common,
+ &clk_hp_clk_mux.common,
+ &clk_hp_clk_div.common,
+ &clk_noc1_clk_div.common,
+ &clk_noc0.common,
+ &clk_noc1.common,
+ &clk_senor_src.common,
+ &clk_gpio.common,
+ &clk_timer.common,
+ &clk_dsi.common,
+ &clk_csi.common,
+ &clk_si.common,
+ &clk_de.common,
+ &clk_hde.common,
+ &clk_vde.common,
+ &clk_vce.common,
+ &clk_nand.common,
+ &clk_sd0.common,
+ &clk_sd1.common,
+ &clk_sd2.common,
+ &clk_uart0.common,
+ &clk_uart1.common,
+ &clk_uart2.common,
+ &clk_uart3.common,
+ &clk_uart4.common,
+ &clk_uart5.common,
+ &clk_uart6.common,
+ &clk_pwm0.common,
+ &clk_pwm1.common,
+ &clk_pwm2.common,
+ &clk_pwm3.common,
+ &clk_pwm4.common,
+ &clk_pwm5.common,
+ &clk_gpu3d.common,
+ &clk_i2c0.common,
+ &clk_i2c1.common,
+ &clk_i2c2.common,
+ &clk_i2c3.common,
+ &clk_spi0.common,
+ &clk_spi1.common,
+ &clk_spi2.common,
+ &clk_spi3.common,
+ &clk_usb3_480mpll0.common,
+ &clk_usb3_480mphy0.common,
+ &clk_usb3_5gphy.common,
+ &clk_usb3_cce.common,
+ &clk_lcd.common,
+ &clk_hdmi_audio.common,
+ &clk_i2srx.common,
+ &clk_i2stx.common,
+ &clk_sensor0.common,
+ &clk_sensor1.common,
+ &clk_hdmi_dev.common,
+ &clk_ethernet.common,
+ &clk_rmii_ref.common,
+ &clk_usb2h0_pllen.common,
+ &clk_usb2h0_phy.common,
+ &clk_usb2h0_cce.common,
+ &clk_usb2h1_pllen.common,
+ &clk_usb2h1_phy.common,
+ &clk_usb2h1_cce.common,
+ &clk_tvout.common,
+ &clk_thermal_sensor.common,
+ &clk_irc_switch.common,
+ &clk_pcm1.common,
+};
+
+static struct clk_hw_onecell_data s700_hw_clks = {
+ .hws = {
+ [CLK_CORE_PLL] = &clk_core_pll.common.hw,
+ [CLK_DEV_PLL] = &clk_dev_pll.common.hw,
+ [CLK_DDR_PLL] = &clk_ddr_pll.common.hw,
+ [CLK_NAND_PLL] = &clk_nand_pll.common.hw,
+ [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw,
+ [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw,
+ [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw,
+ [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw,
+ [CLK_CPU] = &clk_cpu.common.hw,
+ [CLK_DEV] = &clk_dev.common.hw,
+ [CLK_AHB] = &clk_ahb.common.hw,
+ [CLK_APB] = &clk_apb.common.hw,
+ [CLK_DMAC] = &clk_dmac.common.hw,
+ [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw,
+ [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw,
+ [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw,
+ [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw,
+ [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw,
+ [CLK_NOC0] = &clk_noc0.common.hw,
+ [CLK_NOC1] = &clk_noc1.common.hw,
+ [CLK_SENOR_SRC] = &clk_senor_src.common.hw,
+ [CLK_GPIO] = &clk_gpio.common.hw,
+ [CLK_TIMER] = &clk_timer.common.hw,
+ [CLK_DSI] = &clk_dsi.common.hw,
+ [CLK_CSI] = &clk_csi.common.hw,
+ [CLK_SI] = &clk_si.common.hw,
+ [CLK_DE] = &clk_de.common.hw,
+ [CLK_HDE] = &clk_hde.common.hw,
+ [CLK_VDE] = &clk_vde.common.hw,
+ [CLK_VCE] = &clk_vce.common.hw,
+ [CLK_NAND] = &clk_nand.common.hw,
+ [CLK_SD0] = &clk_sd0.common.hw,
+ [CLK_SD1] = &clk_sd1.common.hw,
+ [CLK_SD2] = &clk_sd2.common.hw,
+ [CLK_UART0] = &clk_uart0.common.hw,
+ [CLK_UART1] = &clk_uart1.common.hw,
+ [CLK_UART2] = &clk_uart2.common.hw,
+ [CLK_UART3] = &clk_uart3.common.hw,
+ [CLK_UART4] = &clk_uart4.common.hw,
+ [CLK_UART5] = &clk_uart5.common.hw,
+ [CLK_UART6] = &clk_uart6.common.hw,
+ [CLK_PWM0] = &clk_pwm0.common.hw,
+ [CLK_PWM1] = &clk_pwm1.common.hw,
+ [CLK_PWM2] = &clk_pwm2.common.hw,
+ [CLK_PWM3] = &clk_pwm3.common.hw,
+ [CLK_PWM4] = &clk_pwm4.common.hw,
+ [CLK_PWM5] = &clk_pwm5.common.hw,
+ [CLK_GPU3D] = &clk_gpu3d.common.hw,
+ [CLK_I2C0] = &clk_i2c0.common.hw,
+ [CLK_I2C1] = &clk_i2c1.common.hw,
+ [CLK_I2C2] = &clk_i2c2.common.hw,
+ [CLK_I2C3] = &clk_i2c3.common.hw,
+ [CLK_SPI0] = &clk_spi0.common.hw,
+ [CLK_SPI1] = &clk_spi1.common.hw,
+ [CLK_SPI2] = &clk_spi2.common.hw,
+ [CLK_SPI3] = &clk_spi3.common.hw,
+ [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw,
+ [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw,
+ [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw,
+ [CLK_USB3_CCE] = &clk_usb3_cce.common.hw,
+ [CLK_LCD] = &clk_lcd.common.hw,
+ [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw,
+ [CLK_I2SRX] = &clk_i2srx.common.hw,
+ [CLK_I2STX] = &clk_i2stx.common.hw,
+ [CLK_SENSOR0] = &clk_sensor0.common.hw,
+ [CLK_SENSOR1] = &clk_sensor1.common.hw,
+ [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw,
+ [CLK_ETHERNET] = &clk_ethernet.common.hw,
+ [CLK_RMII_REF] = &clk_rmii_ref.common.hw,
+ [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw,
+ [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw,
+ [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw,
+ [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw,
+ [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw,
+ [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw,
+ [CLK_TVOUT] = &clk_tvout.common.hw,
+ [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw,
+ [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw,
+ [CLK_PCM1] = &clk_pcm1.common.hw,
+ },
+ .num = CLK_NR_CLKS,
+};
+
+static const struct owl_clk_desc s700_clk_desc = {
+ .clks = s700_clks,
+ .num_clks = ARRAY_SIZE(s700_clks),
+
+ .hw_clks = &s700_hw_clks,
+};
+
+static int s700_clk_probe(struct platform_device *pdev)
+{
+ const struct owl_clk_desc *desc;
+
+ desc = &s700_clk_desc;
+ owl_clk_regmap_init(pdev, desc);
+
+ return owl_clk_probe(&pdev->dev, desc->hw_clks);
+}
+
+static const struct of_device_id s700_clk_of_match[] = {
+ { .compatible = "actions,s700-cmu", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver s700_clk_driver = {
+ .probe = s700_clk_probe,
+ .driver = {
+ .name = "s700-cmu",
+ .of_match_table = s700_clk_of_match
+ },
+};
+
+static int __init s700_clk_init(void)
+{
+ return platform_driver_register(&s700_clk_driver);
+}
+core_initcall(s700_clk_init);
--
2.18.0

2018-06-27 06:08:43

by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH 2/2] clk: actions: Add S700 SoC clock support

Hi Saravanan,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on v4.18-rc2 next-20180626]
[cannot apply to robh/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url: https://github.com/0day-ci/linux/commits/Saravanan-Sekar/Add-clock-driver-for-Actions-S700-SoC/20180627-033122
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64

All warnings (new ones prefixed by >>):

>> WARNING: vmlinux.o(.data+0x185d9b0): Section mismatch in reference from the variable __compound_literal.97 to the variable .init.rodata:sensor_clk_mux_p
The variable __compound_literal.97 references
the variable __initconst sensor_clk_mux_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

--
>> WARNING: vmlinux.o(.data+0x185dbb0): Section mismatch in reference from the variable __compound_literal.94 to the variable .init.rodata:i2s_clk_mux_p
The variable __compound_literal.94 references
the variable __initconst i2s_clk_mux_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

--
>> WARNING: vmlinux.o(.data+0x185e390): Section mismatch in reference from the variable __compound_literal.85 to the variable .init.rodata:pwm_clk_mux_p
The variable __compound_literal.85 references
the variable __initconst pwm_clk_mux_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

--
>> WARNING: vmlinux.o(.data+0x185e550): Section mismatch in reference from the variable __compound_literal.83 to the variable .init.rodata:uart_clk_mux_p
The variable __compound_literal.83 references
the variable __initconst uart_clk_mux_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

--
>> WARNING: vmlinux.o(.data+0x185eb70): Section mismatch in reference from the variable __compound_literal.76 to the variable .init.rodata:sd_clk_mux_p
The variable __compound_literal.76 references
the variable __initconst sd_clk_mux_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

--
>> WARNING: vmlinux.o(.data+0x185ee10): Section mismatch in reference from the variable __compound_literal.73 to the variable .init.rodata:nand_clk_mux_p
The variable __compound_literal.73 references
the variable __initconst nand_clk_mux_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

--
>> WARNING: vmlinux.o(.data+0x185eef0): Section mismatch in reference from the variable __compound_literal.72 to the variable .init.rodata:hde_clk_mux_p
The variable __compound_literal.72 references
the variable __initconst hde_clk_mux_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

--
>> WARNING: vmlinux.o(.data+0x185f190): Section mismatch in reference from the variable __compound_literal.69 to the variable .init.rodata:de_clk_mux_p
The variable __compound_literal.69 references
the variable __initconst de_clk_mux_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

--
>> WARNING: vmlinux.o(.data+0x185f270): Section mismatch in reference from the variable __compound_literal.68 to the variable .init.rodata:csi_clk_mux_p
The variable __compound_literal.68 references
the variable __initconst csi_clk_mux_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

--
>> WARNING: vmlinux.o(.data+0x1861890): Section mismatch in reference from the variable __compound_literal.12 to the variable .init.rodata:noc_clk_mux_p
The variable __compound_literal.12 references
the variable __initconst noc_clk_mux_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

--
>> WARNING: vmlinux.o(.data+0x1861ad0): Section mismatch in reference from the variable __compound_literal.9 to the variable .init.rodata:dev_clk_p
The variable __compound_literal.9 references
the variable __initconst dev_clk_p
If the reference is valid then annotate the
variable with or __refdata (see linux/init.h) or name the variable:

..

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation

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2018-06-27 06:08:43

by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH 2/2] clk: actions: Add S700 SoC clock support

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2018-06-29 04:26:03

by saravanan sekar

[permalink] [raw]

Subject: [PATCH v2 0/3] Add clock driver for Actions S700 SoC

Changelog v2:
Fixed 0 day compilation warning
Modified existing dts Actions S900 clock bindings common to Actions
Soc family

This patchset adds clock support for Actions Semi OWL series S700 SoC
with relevant clock bindings and device tree info.

Changed the UART clock using CMU instance and changes are tested in
cubieboard7

Thanks and regards,
Saravanan,
Parthiban

Saravanan Sekar (3):
arm64: dts: actions: Enable clock controller for S700
clk: actions: Add S700 SoC clock support
dt-bindings: clock: Modify Actions Soc clock bindings

...ions,s900-cmu.txt => actions,sx00-cmu.txt} | 18 +-
.../boot/dts/actions/s700-cubieboard7.dts | 7 -
arch/arm64/boot/dts/actions/s700.dtsi | 8 +
drivers/clk/actions/Kconfig | 7 +
drivers/clk/actions/Makefile | 1 +
drivers/clk/actions/owl-s700.c | 614 ++++++++++++++++++
include/dt-bindings/clock/actions,s700-cmu.h | 128 ++++
7 files changed, 768 insertions(+), 15 deletions(-)
rename Documentation/devicetree/bindings/clock/{actions,s900-cmu.txt => actions,sx00-cmu.txt} (71%)
create mode 100644 drivers/clk/actions/owl-s700.c
create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h

--
2.18.0

2018-06-29 04:26:11

by saravanan sekar

[permalink] [raw]

Subject: [PATCH v2 1/3] arm64: dts: actions: Enable clock controller for S700

2018-06-29 04:26:53

by saravanan sekar

[permalink] [raw]

Subject: [PATCH v2 3/3] dt-bindings: clock: Modify Actions Soc clock bindings

Modify clock bindings common Actions Semi Soc family S700/S900.

Signed-off-by: Parthiban Nallathambi <[email protected]>
Signed-off-by: Saravanan Sekar <[email protected]>
---
...tions,s900-cmu.txt => actions,sx00-cmu.txt} | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
rename Documentation/devicetree/bindings/clock/{actions,s900-cmu.txt => actions,sx00-cmu.txt} (71%)

diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
similarity index 71%
rename from Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
rename to Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
index 93e4fb827cd6..8dc7edb4d198 100644
--- a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
+++ b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
@@ -1,12 +1,14 @@
-* Actions S900 Clock Management Unit (CMU)
+* Actions S900/S700 Clock Management Unit (CMU)

-The Actions S900 clock management unit generates and supplies clock to various
-controllers within the SoC. The clock binding described here is applicable to
-S900 SoC.
+The Actions S900/S700 clock management unit generates and supplies clock to
+various controllers within the SoC. The clock binding described here is
+applicable to S900/S700 SoC.

Required Properties:

-- compatible: should be "actions,s900-cmu"
+- compatible: should be one of this
+ "actions,s900-cmu"
+ "actions,s700-cmu"
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: Reference to the parent clocks ("hosc", "losc")
@@ -15,9 +17,9 @@ Required Properties:
Each clock is assigned an identifier, and client nodes can use this identifier
to specify the clock which they consume.

-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/actions,s900-cmu.h header and can be used in device
-tree sources.
+All available clocks are defined as preprocessor macros in corresponding
+dt-bindings/clock/actions,s900-cmu.h or s700-cmu.h header and can be used in
+device tree sources.

External clocks:

--
2.18.0

2018-06-29 04:27:22

by saravanan sekar

[permalink] [raw]

Subject: [PATCH v2 2/3] clk: actions: Add S700 SoC clock support

Add Actions Semi S700 SoC clock support

Signed-off-by: Parthiban Nallathambi <[email protected]>
Signed-off-by: Saravanan Sekar <[email protected]>
---
drivers/clk/actions/Kconfig | 7 +
drivers/clk/actions/Makefile | 1 +
drivers/clk/actions/owl-s700.c | 614 +++++++++++++++++++++++++++++++++
3 files changed, 622 insertions(+)
create mode 100644 drivers/clk/actions/owl-s700.c

diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig
index 8854adb37847..d883b48e4607 100644
--- a/drivers/clk/actions/Kconfig
+++ b/drivers/clk/actions/Kconfig
@@ -1,6 +1,7 @@
config CLK_ACTIONS
bool "Clock driver for Actions Semi SoCs"
depends on ARCH_ACTIONS || COMPILE_TEST
+ select REGMAP_MMIO
default ARCH_ACTIONS

if CLK_ACTIONS
@@ -11,4 +12,10 @@ config CLK_OWL_S900
bool "Support for the Actions Semi OWL S900 clocks"
depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
default ARM64 && ARCH_ACTIONS
+
+config CLK_OWL_S700
+ bool "Support for the Actions Semi OWL S700 clocks"
+ depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
+ default ARM64 && ARCH_ACTIONS
+
endif
diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
index 76e431434d10..a860973d940d 100644
--- a/drivers/clk/actions/Makefile
+++ b/drivers/clk/actions/Makefile
@@ -9,4 +9,5 @@ clk-owl-y += owl-composite.o
clk-owl-y += owl-pll.o

# SoC support
+obj-$(CONFIG_CLK_OWL_S900) += owl-s700.o
obj-$(CONFIG_CLK_OWL_S900) += owl-s900.o
diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c
new file mode 100644
index 000000000000..cc8d1f947171
--- /dev/null
+++ b/drivers/clk/actions/owl-s700.c
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions S700 clock driver
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <[email protected]>
+ *
+ * Author: Pathiban Nallathambi <[email protected]>
+ * Author: Saravanan Sekar <[email protected]>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "owl-common.h"
+#include "owl-composite.h"
+#include "owl-divider.h"
+#include "owl-factor.h"
+#include "owl-fixed-factor.h"
+#include "owl-gate.h"
+#include "owl-mux.h"
+#include "owl-pll.h"
+
+#include <dt-bindings/clock/actions,s700-cmu.h>
+
+#define CMU_COREPLL (0x0000)
+#define CMU_DEVPLL (0x0004)
+#define CMU_DDRPLL (0x0008)
+#define CMU_NANDPLL (0x000C)
+#define CMU_DISPLAYPLL (0x0010)
+#define CMU_AUDIOPLL (0x0014)
+#define CMU_TVOUTPLL (0x0018)
+#define CMU_BUSCLK (0x001C)
+#define CMU_SENSORCLK (0x0020)
+#define CMU_LCDCLK (0x0024)
+#define CMU_DSIPLLCLK (0x0028)
+#define CMU_CSICLK (0x002C)
+#define CMU_DECLK (0x0030)
+#define CMU_SICLK (0x0034)
+#define CMU_BUSCLK1 (0x0038)
+#define CMU_HDECLK (0x003C)
+#define CMU_VDECLK (0x0040)
+#define CMU_VCECLK (0x0044)
+#define CMU_NANDCCLK (0x004C)
+#define CMU_SD0CLK (0x0050)
+#define CMU_SD1CLK (0x0054)
+#define CMU_SD2CLK (0x0058)
+#define CMU_UART0CLK (0x005C)
+#define CMU_UART1CLK (0x0060)
+#define CMU_UART2CLK (0x0064)
+#define CMU_UART3CLK (0x0068)
+#define CMU_UART4CLK (0x006C)
+#define CMU_UART5CLK (0x0070)
+#define CMU_UART6CLK (0x0074)
+#define CMU_PWM0CLK (0x0078)
+#define CMU_PWM1CLK (0x007C)
+#define CMU_PWM2CLK (0x0080)
+#define CMU_PWM3CLK (0x0084)
+#define CMU_PWM4CLK (0x0088)
+#define CMU_PWM5CLK (0x008C)
+#define CMU_GPU3DCLK (0x0090)
+#define CMU_CORECTL (0x009C)
+#define CMU_DEVCLKEN0 (0x00A0)
+#define CMU_DEVCLKEN1 (0x00A4)
+#define CMU_DEVRST0 (0x00A8)
+#define CMU_DEVRST1 (0x00AC)
+#define CMU_USBPLL (0x00B0)
+#define CMU_ETHERNETPLL (0x00B4)
+#define CMU_CVBSPLL (0x00B8)
+#define CMU_SSTSCLK (0x00C0)
+
+static struct clk_pll_table clk_audio_pll_table[] = {
+ {0, 45158400}, {1, 49152000},
+ {0, 0},
+};
+
+static struct clk_pll_table clk_cvbs_pll_table[] = {
+ {27, 29*12000000}, {28, 30*12000000}, {29, 31*12000000},
+ {30, 32*12000000}, {31, 33*12000000}, {32, 34*12000000},
+ {33, 35*12000000}, {34, 36*12000000}, {35, 37*12000000},
+ {36, 38*12000000}, {37, 39*12000000}, {38, 40*12000000},
+ {39, 41*12000000}, {40, 42*12000000}, {41, 43*12000000},
+ {42, 44*12000000}, {43, 45*12000000}, {0, 0},
+};
+
+/* pll clocks */
+static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
+
+
+static const char *cpu_clk_mux_p[] = {"losc", "hosc", "core_pll", "noc1_clk_div"};
+static const char *dev_clk_p[] = { "hosc", "dev_pll"};
+static const char *noc_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"};
+
+static const char *csi_clk_mux_p[] = { "display_pll", "dev_clk"};
+static const char *de_clk_mux_p[] = { "display_pll", "dev_clk"};
+static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"};
+static const char *nand_clk_mux_p[] = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"};
+static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll", };
+static const char *uart_clk_mux_p[] = { "hosc", "dev_pll"};
+static const char *pwm_clk_mux_p[] = { "losc", "hosc"};
+static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"};
+static const char *lcd_clk_mux_p[] = { "display_pll", "dev_clk" };
+static const char *i2s_clk_mux_p[] = { "audio_pll" };
+static const char *sensor_clk_mux_p[] = { "hosc", "si"};
+
+
+/* mux clocks */
+static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
+static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
+static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT);
+static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT);
+static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
+
+static struct clk_factor_table sd_factor_table[] = {
+ /* bit0 ~ 4 */
+ {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
+ {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
+ {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
+ {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16},
+ {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20},
+ {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24},
+ {24, 1, 25}, {25, 1, 26},
+
+ /* bit8: /128 */
+ {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128},
+ {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128},
+ {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128},
+ {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128},
+ {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128},
+ {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
+ {280, 1, 25 * 128}, {281, 1, 26 * 128},
+
+ {0, 0},
+};
+
+static struct clk_factor_table lcd_factor_table[] = {
+ /* bit0 ~ 3 */
+ {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
+ {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
+ {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
+
+ /* bit8: /7 */
+ {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
+ {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
+ {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
+ {0, 0},
+};
+
+
+static struct clk_div_table hdmia_div_table[] = {
+ {0, 1}, {1, 2}, {2, 3}, {3, 4},
+ {4, 6}, {5, 8}, {6, 12}, {7, 16},
+ {8, 24},
+ {0, 0},
+};
+
+static struct clk_div_table rmii_div_table[] = {
+ {0, 4}, {1, 10},
+};
+
+
+/* divider clocks */
+static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0);
+static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0);
+static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0);
+static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
+static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
+static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
+static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0);
+static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0);
+static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0);
+
+static struct clk_factor_table de_factor_table[] = {
+ {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
+ {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
+ {8, 1, 12}, {0, 0, 0},
+};
+
+static struct clk_factor_table hde_factor_table[] = {
+ {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
+ {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
+ {0, 0, 0},
+};
+
+/* gate clocks */
+static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0);
+static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0);
+static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
+static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0);
+static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0);
+static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0);
+static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0);
+static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0);
+static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0);
+static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
+static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0);
+static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0);
+static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0);
+static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0);
+static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0);
+static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0);
+
+/* composite clocks */
+
+static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p,
+ OWL_MUX_HW(CMU_CSICLK, 4, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
+ OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p,
+ OWL_MUX_HW(CMU_SICLK, 4, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
+ OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
+ 0);
+
+static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p,
+ OWL_MUX_HW(CMU_DECLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
+ OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p,
+ OWL_MUX_HW(CMU_HDECLK, 4, 2),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
+ OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p,
+ OWL_MUX_HW(CMU_VDECLK, 4, 2),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
+ OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p,
+ OWL_MUX_HW(CMU_VCECLK, 4, 2),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
+ OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
+ 0);
+
+static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p,
+ OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
+ OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
+ CLK_SET_RATE_PARENT);
+
+static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p,
+ OWL_MUX_HW(CMU_SD0CLK, 9, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
+ OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p,
+ OWL_MUX_HW(CMU_SD1CLK, 9, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
+ OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p,
+ OWL_MUX_HW(CMU_SD2CLK, 9, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0),
+ OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
+#ifdef CONFIG_MMC_OWL_CLK_NANDPLL
+ CLK_SET_RATE_PARENT);
+#else
+ 0);
+#endif
+
+static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART0CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
+ OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART1CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0),
+ OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART2CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0),
+ OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART3CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0),
+ OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART4CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0),
+ OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART5CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0),
+ OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p,
+ OWL_MUX_HW(CMU_UART6CLK, 16, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
+ OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0),
+ OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
+ CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
+ OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
+ OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
+ OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
+ OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p,
+ OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
+ OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
+ 0);
+
+static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p,
+ OWL_MUX_HW(CMU_GPU3DCLK, 4, 3),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
+ OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table),
+ 0);
+
+static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p,
+ OWL_MUX_HW(CMU_LCDCLK, 12, 2),
+ OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0),
+ OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table),
+ 0);
+
+static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p,
+ OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),/*CMU_AUDIOPLL 24,1 unused*/
+ OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0),
+ OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
+ 0);
+
+static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p,
+ OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0),
+ OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
+ 0);
+
+static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p,
+ OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
+ OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
+ OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
+ 0);
+
+/* for bluetooth pcm communication */
+static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll",
+ OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
+ 1, 2, 0);
+
+static OWL_COMP_DIV(clk_senor_src, "sensor_src", sensor_clk_mux_p,
+ OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
+ {0},
+ OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
+ 0);
+
+static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll",
+ OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
+ 1, 20, 0);
+
+static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc",
+ OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0),
+ OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),
+ 0);
+
+static struct owl_clk_common *s700_clks[] = {
+ &clk_core_pll.common,
+ &clk_dev_pll.common,
+ &clk_ddr_pll.common,
+ &clk_nand_pll.common,
+ &clk_display_pll.common,
+ &clk_cvbs_pll .common,
+ &clk_audio_pll.common,
+ &clk_ethernet_pll.common,
+ &clk_cpu.common,
+ &clk_dev.common,
+ &clk_ahb.common,
+ &clk_apb.common,
+ &clk_dmac.common,
+ &clk_noc0_clk_mux.common,
+ &clk_noc1_clk_mux.common,
+ &clk_hp_clk_mux.common,
+ &clk_hp_clk_div.common,
+ &clk_noc1_clk_div.common,
+ &clk_noc0.common,
+ &clk_noc1.common,
+ &clk_senor_src.common,
+ &clk_gpio.common,
+ &clk_timer.common,
+ &clk_dsi.common,
+ &clk_csi.common,
+ &clk_si.common,
+ &clk_de.common,
+ &clk_hde.common,
+ &clk_vde.common,
+ &clk_vce.common,
+ &clk_nand.common,
+ &clk_sd0.common,
+ &clk_sd1.common,
+ &clk_sd2.common,
+ &clk_uart0.common,
+ &clk_uart1.common,
+ &clk_uart2.common,
+ &clk_uart3.common,
+ &clk_uart4.common,
+ &clk_uart5.common,
+ &clk_uart6.common,
+ &clk_pwm0.common,
+ &clk_pwm1.common,
+ &clk_pwm2.common,
+ &clk_pwm3.common,
+ &clk_pwm4.common,
+ &clk_pwm5.common,
+ &clk_gpu3d.common,
+ &clk_i2c0.common,
+ &clk_i2c1.common,
+ &clk_i2c2.common,
+ &clk_i2c3.common,
+ &clk_spi0.common,
+ &clk_spi1.common,
+ &clk_spi2.common,
+ &clk_spi3.common,
+ &clk_usb3_480mpll0.common,
+ &clk_usb3_480mphy0.common,
+ &clk_usb3_5gphy.common,
+ &clk_usb3_cce.common,
+ &clk_lcd.common,
+ &clk_hdmi_audio.common,
+ &clk_i2srx.common,
+ &clk_i2stx.common,
+ &clk_sensor0.common,
+ &clk_sensor1.common,
+ &clk_hdmi_dev.common,
+ &clk_ethernet.common,
+ &clk_rmii_ref.common,
+ &clk_usb2h0_pllen.common,
+ &clk_usb2h0_phy.common,
+ &clk_usb2h0_cce.common,
+ &clk_usb2h1_pllen.common,
+ &clk_usb2h1_phy.common,
+ &clk_usb2h1_cce.common,
+ &clk_tvout.common,
+ &clk_thermal_sensor.common,
+ &clk_irc_switch.common,
+ &clk_pcm1.common,
+};
+
+static struct clk_hw_onecell_data s700_hw_clks = {
+ .hws = {
+ [CLK_CORE_PLL] = &clk_core_pll.common.hw,
+ [CLK_DEV_PLL] = &clk_dev_pll.common.hw,
+ [CLK_DDR_PLL] = &clk_ddr_pll.common.hw,
+ [CLK_NAND_PLL] = &clk_nand_pll.common.hw,
+ [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw,
+ [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw,
+ [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw,
+ [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw,
+ [CLK_CPU] = &clk_cpu.common.hw,
+ [CLK_DEV] = &clk_dev.common.hw,
+ [CLK_AHB] = &clk_ahb.common.hw,
+ [CLK_APB] = &clk_apb.common.hw,
+ [CLK_DMAC] = &clk_dmac.common.hw,
+ [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw,
+ [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw,
+ [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw,
+ [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw,
+ [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw,
+ [CLK_NOC0] = &clk_noc0.common.hw,
+ [CLK_NOC1] = &clk_noc1.common.hw,
+ [CLK_SENOR_SRC] = &clk_senor_src.common.hw,
+ [CLK_GPIO] = &clk_gpio.common.hw,
+ [CLK_TIMER] = &clk_timer.common.hw,
+ [CLK_DSI] = &clk_dsi.common.hw,
+ [CLK_CSI] = &clk_csi.common.hw,
+ [CLK_SI] = &clk_si.common.hw,
+ [CLK_DE] = &clk_de.common.hw,
+ [CLK_HDE] = &clk_hde.common.hw,
+ [CLK_VDE] = &clk_vde.common.hw,
+ [CLK_VCE] = &clk_vce.common.hw,
+ [CLK_NAND] = &clk_nand.common.hw,
+ [CLK_SD0] = &clk_sd0.common.hw,
+ [CLK_SD1] = &clk_sd1.common.hw,
+ [CLK_SD2] = &clk_sd2.common.hw,
+ [CLK_UART0] = &clk_uart0.common.hw,
+ [CLK_UART1] = &clk_uart1.common.hw,
+ [CLK_UART2] = &clk_uart2.common.hw,
+ [CLK_UART3] = &clk_uart3.common.hw,
+ [CLK_UART4] = &clk_uart4.common.hw,
+ [CLK_UART5] = &clk_uart5.common.hw,
+ [CLK_UART6] = &clk_uart6.common.hw,
+ [CLK_PWM0] = &clk_pwm0.common.hw,
+ [CLK_PWM1] = &clk_pwm1.common.hw,
+ [CLK_PWM2] = &clk_pwm2.common.hw,
+ [CLK_PWM3] = &clk_pwm3.common.hw,
+ [CLK_PWM4] = &clk_pwm4.common.hw,
+ [CLK_PWM5] = &clk_pwm5.common.hw,
+ [CLK_GPU3D] = &clk_gpu3d.common.hw,
+ [CLK_I2C0] = &clk_i2c0.common.hw,
+ [CLK_I2C1] = &clk_i2c1.common.hw,
+ [CLK_I2C2] = &clk_i2c2.common.hw,
+ [CLK_I2C3] = &clk_i2c3.common.hw,
+ [CLK_SPI0] = &clk_spi0.common.hw,
+ [CLK_SPI1] = &clk_spi1.common.hw,
+ [CLK_SPI2] = &clk_spi2.common.hw,
+ [CLK_SPI3] = &clk_spi3.common.hw,
+ [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw,
+ [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw,
+ [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw,
+ [CLK_USB3_CCE] = &clk_usb3_cce.common.hw,
+ [CLK_LCD] = &clk_lcd.common.hw,
+ [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw,
+ [CLK_I2SRX] = &clk_i2srx.common.hw,
+ [CLK_I2STX] = &clk_i2stx.common.hw,
+ [CLK_SENSOR0] = &clk_sensor0.common.hw,
+ [CLK_SENSOR1] = &clk_sensor1.common.hw,
+ [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw,
+ [CLK_ETHERNET] = &clk_ethernet.common.hw,
+ [CLK_RMII_REF] = &clk_rmii_ref.common.hw,
+ [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw,
+ [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw,
+ [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw,
+ [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw,
+ [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw,
+ [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw,
+ [CLK_TVOUT] = &clk_tvout.common.hw,
+ [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw,
+ [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw,
+ [CLK_PCM1] = &clk_pcm1.common.hw,
+ },
+ .num = CLK_NR_CLKS,
+};
+
+static const struct owl_clk_desc s700_clk_desc = {
+ .clks = s700_clks,
+ .num_clks = ARRAY_SIZE(s700_clks),
+
+ .hw_clks = &s700_hw_clks,
+};
+
+static int s700_clk_probe(struct platform_device *pdev)
+{
+ const struct owl_clk_desc *desc;
+
+ desc = &s700_clk_desc;
+ owl_clk_regmap_init(pdev, desc);
+
+ return owl_clk_probe(&pdev->dev, desc->hw_clks);
+}
+
+static const struct of_device_id s700_clk_of_match[] = {
+ { .compatible = "actions,s700-cmu", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver s700_clk_driver = {
+ .probe = s700_clk_probe,
+ .driver = {
+ .name = "s700-cmu",
+ .of_match_table = s700_clk_of_match
+ },
+};
+
+static int __init s700_clk_init(void)
+{
+ return platform_driver_register(&s700_clk_driver);
+}
+core_initcall(s700_clk_init);
--
2.18.0

2018-06-29 17:43:46

by Andreas Färber

[permalink] [raw]

Subject: Re: [PATCH v2 1/3] arm64: dts: actions: Enable clock controller for S700

Am 29.06.2018 um 19:36 schrieb Stephen Boyd:
> Quoting Saravanan Sekar (2018-06-28 12:18:03)
>> diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
>> index ef79d7905f44..28f3f4a0f7f0 100644
>> --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
>> +++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
>> diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
>> index 66dd5309f0a2..3530b705df90 100644
>> --- a/arch/arm64/boot/dts/actions/s700.dtsi
>> +++ b/arch/arm64/boot/dts/actions/s700.dtsi
>
> Can the above part be split from the below part? I don't want to merge
> dts bits into clk tree, when those should normally go through arm-soc.
>
>> diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
>> new file mode 100644

This part needs to go into the bindings patch, which should be 1/3, not
3/3 please.

Thanks,
Andreas

--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

2018-06-29 17:44:39

by Stephen Boyd

[permalink] [raw]

Subject: Re: [PATCH v2 0/3] Add clock driver for Actions S700 SoC

Quoting Saravanan Sekar (2018-06-28 12:18:02)
> Changelog v2:
> Fixed 0 day compilation warning
> Modified existing dts Actions S900 clock bindings common to Actions
> Soc family
>
> This patchset adds clock support for Actions Semi OWL series S700 SoC
> with relevant clock bindings and device tree info.
>
> Changed the UART clock using CMU instance and changes are tested in
> cubieboard7
>
> Thanks and regards,
> Saravanan,
> Parthiban
>
> Saravanan Sekar (3):
> arm64: dts: actions: Enable clock controller for S700
> clk: actions: Add S700 SoC clock support
> dt-bindings: clock: Modify Actions Soc clock bindings

Normally this patch comes first, and then clk driver, and then dts bits.
Also, the header file for the #define constants would be part of the
bindings patch.

2018-06-29 20:02:15

by Stephen Boyd

[permalink] [raw]

Subject: Re: [PATCH v2 1/3] arm64: dts: actions: Enable clock controller for S700

Quoting Saravanan Sekar (2018-06-28 12:18:03)
> diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
> index ef79d7905f44..28f3f4a0f7f0 100644
> --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
> +++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
> diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
> index 66dd5309f0a2..3530b705df90 100644
> --- a/arch/arm64/boot/dts/actions/s700.dtsi
> +++ b/arch/arm64/boot/dts/actions/s700.dtsi

Can the above part be split from the below part? I don't want to merge
dts bits into clk tree, when those should normally go through arm-soc.

> diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
> new file mode 100644

2018-06-30 09:24:54

by Manivannan Sadhasivam

[permalink] [raw]

Subject: Re: [PATCH v2 2/3] clk: actions: Add S700 SoC clock support

Hi Saravanan,

On Thu, Jun 28, 2018 at 09:18:04PM +0200, Saravanan Sekar wrote:
> Add Actions Semi S700 SoC clock support
>
> Signed-off-by: Parthiban Nallathambi <[email protected]>
> Signed-off-by: Saravanan Sekar <[email protected]>
> ---
> drivers/clk/actions/Kconfig | 7 +
> drivers/clk/actions/Makefile | 1 +
> drivers/clk/actions/owl-s700.c | 614 +++++++++++++++++++++++++++++++++
> 3 files changed, 622 insertions(+)
> create mode 100644 drivers/clk/actions/owl-s700.c
>
> diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig
> index 8854adb37847..d883b48e4607 100644
> --- a/drivers/clk/actions/Kconfig
> +++ b/drivers/clk/actions/Kconfig
> @@ -1,6 +1,7 @@
> config CLK_ACTIONS
> bool "Clock driver for Actions Semi SoCs"
> depends on ARCH_ACTIONS || COMPILE_TEST
> + select REGMAP_MMIO

This change should be in a separate patch.

> default ARCH_ACTIONS
>
> if CLK_ACTIONS
> @@ -11,4 +12,10 @@ config CLK_OWL_S900
> bool "Support for the Actions Semi OWL S900 clocks"
> depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
> default ARM64 && ARCH_ACTIONS
> +
> +config CLK_OWL_S700
> + bool "Support for the Actions Semi OWL S700 clocks"
> + depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
> + default ARM64 && ARCH_ACTIONS
> +

It's good to keep the symbols alphabetically sorted (ascending order)

> endif
> diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
> index 76e431434d10..a860973d940d 100644
> --- a/drivers/clk/actions/Makefile
> +++ b/drivers/clk/actions/Makefile
> @@ -9,4 +9,5 @@ clk-owl-y += owl-composite.o
> clk-owl-y += owl-pll.o
>
> # SoC support
> +obj-$(CONFIG_CLK_OWL_S900) += owl-s700.o

Should be CONFIG_CLK_OWL_S700

> obj-$(CONFIG_CLK_OWL_S900) += owl-s900.o
> diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c
> new file mode 100644
> index 000000000000..cc8d1f947171
> --- /dev/null
> +++ b/drivers/clk/actions/owl-s700.c
> @@ -0,0 +1,614 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Actions S700 clock driver
> + *
> + * Copyright (c) 2014 Actions Semi Inc.
> + * Author: David Liu <[email protected]>
> + *
> + * Author: Pathiban Nallathambi <[email protected]>
> + * Author: Saravanan Sekar <[email protected]>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "owl-common.h"
> +#include "owl-composite.h"
> +#include "owl-divider.h"
> +#include "owl-factor.h"
> +#include "owl-fixed-factor.h"
> +#include "owl-gate.h"
> +#include "owl-mux.h"
> +#include "owl-pll.h"
> +
> +#include <dt-bindings/clock/actions,s700-cmu.h>
> +
> +#define CMU_COREPLL (0x0000)
> +#define CMU_DEVPLL (0x0004)
> +#define CMU_DDRPLL (0x0008)
> +#define CMU_NANDPLL (0x000C)
> +#define CMU_DISPLAYPLL (0x0010)
> +#define CMU_AUDIOPLL (0x0014)
> +#define CMU_TVOUTPLL (0x0018)
> +#define CMU_BUSCLK (0x001C)
> +#define CMU_SENSORCLK (0x0020)
> +#define CMU_LCDCLK (0x0024)
> +#define CMU_DSIPLLCLK (0x0028)
> +#define CMU_CSICLK (0x002C)
> +#define CMU_DECLK (0x0030)
> +#define CMU_SICLK (0x0034)
> +#define CMU_BUSCLK1 (0x0038)
> +#define CMU_HDECLK (0x003C)
> +#define CMU_VDECLK (0x0040)
> +#define CMU_VCECLK (0x0044)
> +#define CMU_NANDCCLK (0x004C)
> +#define CMU_SD0CLK (0x0050)
> +#define CMU_SD1CLK (0x0054)
> +#define CMU_SD2CLK (0x0058)
> +#define CMU_UART0CLK (0x005C)
> +#define CMU_UART1CLK (0x0060)
> +#define CMU_UART2CLK (0x0064)
> +#define CMU_UART3CLK (0x0068)
> +#define CMU_UART4CLK (0x006C)
> +#define CMU_UART5CLK (0x0070)
> +#define CMU_UART6CLK (0x0074)
> +#define CMU_PWM0CLK (0x0078)
> +#define CMU_PWM1CLK (0x007C)
> +#define CMU_PWM2CLK (0x0080)
> +#define CMU_PWM3CLK (0x0084)
> +#define CMU_PWM4CLK (0x0088)
> +#define CMU_PWM5CLK (0x008C)
> +#define CMU_GPU3DCLK (0x0090)
> +#define CMU_CORECTL (0x009C)
> +#define CMU_DEVCLKEN0 (0x00A0)
> +#define CMU_DEVCLKEN1 (0x00A4)
> +#define CMU_DEVRST0 (0x00A8)
> +#define CMU_DEVRST1 (0x00AC)
> +#define CMU_USBPLL (0x00B0)
> +#define CMU_ETHERNETPLL (0x00B4)
> +#define CMU_CVBSPLL (0x00B8)
> +#define CMU_SSTSCLK (0x00C0)
> +
> +static struct clk_pll_table clk_audio_pll_table[] = {
> + {0, 45158400}, {1, 49152000},
> + {0, 0},
> +};
> +
> +static struct clk_pll_table clk_cvbs_pll_table[] = {
> + {27, 29*12000000}, {28, 30*12000000}, {29, 31*12000000},

Please leave a space around *

> + {30, 32*12000000}, {31, 33*12000000}, {32, 34*12000000},
> + {33, 35*12000000}, {34, 36*12000000}, {35, 37*12000000},
> + {36, 38*12000000}, {37, 39*12000000}, {38, 40*12000000},
> + {39, 41*12000000}, {40, 42*12000000}, {41, 43*12000000},
> + {42, 44*12000000}, {43, 45*12000000}, {0, 0},
> +};
> +
> +/* pll clocks */
> +static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED);
> +static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED);
> +static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED);
> +static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED);
> +static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED);
> +static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED);
> +static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
> +static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
> +
> +

Remove extra new line

> +static const char *cpu_clk_mux_p[] = {"losc", "hosc", "core_pll", "noc1_clk_div"};
> +static const char *dev_clk_p[] = { "hosc", "dev_pll"};
> +static const char *noc_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"};
> +
> +static const char *csi_clk_mux_p[] = { "display_pll", "dev_clk"};
> +static const char *de_clk_mux_p[] = { "display_pll", "dev_clk"};
> +static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"};
> +static const char *nand_clk_mux_p[] = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"};
> +static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll", };
> +static const char *uart_clk_mux_p[] = { "hosc", "dev_pll"};
> +static const char *pwm_clk_mux_p[] = { "losc", "hosc"};
> +static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"};
> +static const char *lcd_clk_mux_p[] = { "display_pll", "dev_clk" };
> +static const char *i2s_clk_mux_p[] = { "audio_pll" };
> +static const char *sensor_clk_mux_p[] = { "hosc", "si"};
> +
> +

Remove extra new line

> +/* mux clocks */
> +static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
> +static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
> +static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT);

Keep the spacing consistent.

> +static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT);

ditto

> +static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
> +
> +static struct clk_factor_table sd_factor_table[] = {
> + /* bit0 ~ 4 */
> + {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
> + {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
> + {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
> + {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16},
> + {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20},
> + {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24},
> + {24, 1, 25}, {25, 1, 26},
> +
> + /* bit8: /128 */
> + {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128},
> + {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128},
> + {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128},
> + {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128},
> + {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128},
> + {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
> + {280, 1, 25 * 128}, {281, 1, 26 * 128},
> +
> + {0, 0},
> +};
> +
> +static struct clk_factor_table lcd_factor_table[] = {
> + /* bit0 ~ 3 */
> + {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
> + {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
> + {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
> +
> + /* bit8: /7 */
> + {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
> + {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
> + {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
> + {0, 0},
> +};
> +
> +

Remove extra new line

> +static struct clk_div_table hdmia_div_table[] = {
> + {0, 1}, {1, 2}, {2, 3}, {3, 4},
> + {4, 6}, {5, 8}, {6, 12}, {7, 16},
> + {8, 24},
> + {0, 0},
> +};
> +
> +static struct clk_div_table rmii_div_table[] = {
> + {0, 4}, {1, 10},
> +};
> +
> +

Remove extra new line

> +/* divider clocks */
> +static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0);
> +static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0);
> +static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0);
> +static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> +static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
> +static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
> +static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0);
> +static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0);
> +static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0);
> +
> +static struct clk_factor_table de_factor_table[] = {
> + {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
> + {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
> + {8, 1, 12}, {0, 0, 0},
> +};
> +
> +static struct clk_factor_table hde_factor_table[] = {
> + {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
> + {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
> + {0, 0, 0},
> +};
> +
> +/* gate clocks */
> +static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0);
> +static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0);
> +static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 27, 0, 0);

Timer clk enable bit should be 22 according to the datasheet I have.

> +static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0);
> +static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0);
> +static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0);
> +static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0);
> +static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
> +static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0);
> +static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0);
> +static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0);
> +static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0);
> +static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0);
> +
> +/* composite clocks */
> +
> +static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p,
> + OWL_MUX_HW(CMU_CSICLK, 4, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
> + OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p,
> + OWL_MUX_HW(CMU_SICLK, 4, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
> + OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
> + 0);
> +
> +static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p,
> + OWL_MUX_HW(CMU_DECLK, 12, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
> + OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table),
> + 0);
> +
> +static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p,
> + OWL_MUX_HW(CMU_HDECLK, 4, 2),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
> + OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table),
> + 0);
> +
> +static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p,
> + OWL_MUX_HW(CMU_VDECLK, 4, 2),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
> + OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
> + 0);
> +
> +static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p,
> + OWL_MUX_HW(CMU_VCECLK, 4, 2),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
> + OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
> + 0);
> +
> +static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p,
> + OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
> + OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
> + CLK_SET_RATE_PARENT);
> +
> +static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p,
> + OWL_MUX_HW(CMU_SD0CLK, 9, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
> + OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
> + 0);
> +
> +static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p,
> + OWL_MUX_HW(CMU_SD1CLK, 9, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
> + OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
> + 0);
> +
> +static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p,
> + OWL_MUX_HW(CMU_SD2CLK, 9, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0),
> + OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
> +#ifdef CONFIG_MMC_OWL_CLK_NANDPLL

From where this define comes from?

> + CLK_SET_RATE_PARENT);
> +#else
> + 0);
> +#endif
> +
> +static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
> + OWL_MUX_HW(CMU_UART0CLK, 16, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
> + OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p,
> + OWL_MUX_HW(CMU_UART1CLK, 16, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0),
> + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p,
> + OWL_MUX_HW(CMU_UART2CLK, 16, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0),
> + OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p,
> + OWL_MUX_HW(CMU_UART3CLK, 16, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0),
> + OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p,
> + OWL_MUX_HW(CMU_UART4CLK, 16, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0),
> + OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p,
> + OWL_MUX_HW(CMU_UART5CLK, 16, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0),
> + OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p,
> + OWL_MUX_HW(CMU_UART6CLK, 16, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
> + OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p,
> + OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0),
> + OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
> + CLK_IGNORE_UNUSED);
> +
> +static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p,
> + OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
> + OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p,
> + OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
> + OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p,
> + OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
> + OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p,
> + OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
> + OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
> + 0);
> +
> +static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p,
> + OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
> + OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
> + 0);
> +
> +static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p,

Please keep spacing consistent

> + OWL_MUX_HW(CMU_GPU3DCLK, 4, 3),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
> + OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table),
> + 0);
> +
> +static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p,

ditto

> + OWL_MUX_HW(CMU_LCDCLK, 12, 2),
> + OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0),
> + OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table),
> + 0);
> +
> +static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p,
> + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),/*CMU_AUDIOPLL 24,1 unused*/
> + OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0),
> + OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
> + 0);
> +
> +static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p,
> + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0),
> + OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
> + 0);
> +
> +static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p,
> + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
> + OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
> + OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
> + 0);
> +
> +/* for bluetooth pcm communication */
> +static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll",
> + OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
> + 1, 2, 0);
> +
> +static OWL_COMP_DIV(clk_senor_src, "sensor_src", sensor_clk_mux_p,

Should be clk_sensor_src.

Thanks,
Mani

> + OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
> + {0},
> + OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
> + 0);
> +
> +static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll",
> + OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
> + 1, 20, 0);
> +
> +static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc",
> + OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0),
> + OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),
> + 0);
> +
> +static struct owl_clk_common *s700_clks[] = {
> + &clk_core_pll.common,
> + &clk_dev_pll.common,
> + &clk_ddr_pll.common,
> + &clk_nand_pll.common,
> + &clk_display_pll.common,
> + &clk_cvbs_pll .common,
> + &clk_audio_pll.common,
> + &clk_ethernet_pll.common,
> + &clk_cpu.common,
> + &clk_dev.common,
> + &clk_ahb.common,
> + &clk_apb.common,
> + &clk_dmac.common,
> + &clk_noc0_clk_mux.common,
> + &clk_noc1_clk_mux.common,
> + &clk_hp_clk_mux.common,
> + &clk_hp_clk_div.common,
> + &clk_noc1_clk_div.common,
> + &clk_noc0.common,
> + &clk_noc1.common,
> + &clk_senor_src.common,
> + &clk_gpio.common,
> + &clk_timer.common,
> + &clk_dsi.common,
> + &clk_csi.common,
> + &clk_si.common,
> + &clk_de.common,
> + &clk_hde.common,
> + &clk_vde.common,
> + &clk_vce.common,
> + &clk_nand.common,
> + &clk_sd0.common,
> + &clk_sd1.common,
> + &clk_sd2.common,
> + &clk_uart0.common,
> + &clk_uart1.common,
> + &clk_uart2.common,
> + &clk_uart3.common,
> + &clk_uart4.common,
> + &clk_uart5.common,
> + &clk_uart6.common,
> + &clk_pwm0.common,
> + &clk_pwm1.common,
> + &clk_pwm2.common,
> + &clk_pwm3.common,
> + &clk_pwm4.common,
> + &clk_pwm5.common,
> + &clk_gpu3d.common,
> + &clk_i2c0.common,
> + &clk_i2c1.common,
> + &clk_i2c2.common,
> + &clk_i2c3.common,
> + &clk_spi0.common,
> + &clk_spi1.common,
> + &clk_spi2.common,
> + &clk_spi3.common,
> + &clk_usb3_480mpll0.common,
> + &clk_usb3_480mphy0.common,
> + &clk_usb3_5gphy.common,
> + &clk_usb3_cce.common,
> + &clk_lcd.common,
> + &clk_hdmi_audio.common,
> + &clk_i2srx.common,
> + &clk_i2stx.common,
> + &clk_sensor0.common,
> + &clk_sensor1.common,
> + &clk_hdmi_dev.common,
> + &clk_ethernet.common,
> + &clk_rmii_ref.common,
> + &clk_usb2h0_pllen.common,
> + &clk_usb2h0_phy.common,
> + &clk_usb2h0_cce.common,
> + &clk_usb2h1_pllen.common,
> + &clk_usb2h1_phy.common,
> + &clk_usb2h1_cce.common,
> + &clk_tvout.common,
> + &clk_thermal_sensor.common,
> + &clk_irc_switch.common,
> + &clk_pcm1.common,
> +};
> +
> +static struct clk_hw_onecell_data s700_hw_clks = {
> + .hws = {
> + [CLK_CORE_PLL] = &clk_core_pll.common.hw,
> + [CLK_DEV_PLL] = &clk_dev_pll.common.hw,
> + [CLK_DDR_PLL] = &clk_ddr_pll.common.hw,
> + [CLK_NAND_PLL] = &clk_nand_pll.common.hw,
> + [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw,
> + [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw,
> + [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw,
> + [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw,
> + [CLK_CPU] = &clk_cpu.common.hw,
> + [CLK_DEV] = &clk_dev.common.hw,
> + [CLK_AHB] = &clk_ahb.common.hw,
> + [CLK_APB] = &clk_apb.common.hw,
> + [CLK_DMAC] = &clk_dmac.common.hw,
> + [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw,
> + [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw,
> + [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw,
> + [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw,
> + [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw,
> + [CLK_NOC0] = &clk_noc0.common.hw,
> + [CLK_NOC1] = &clk_noc1.common.hw,
> + [CLK_SENOR_SRC] = &clk_senor_src.common.hw,
> + [CLK_GPIO] = &clk_gpio.common.hw,
> + [CLK_TIMER] = &clk_timer.common.hw,
> + [CLK_DSI] = &clk_dsi.common.hw,
> + [CLK_CSI] = &clk_csi.common.hw,
> + [CLK_SI] = &clk_si.common.hw,
> + [CLK_DE] = &clk_de.common.hw,
> + [CLK_HDE] = &clk_hde.common.hw,
> + [CLK_VDE] = &clk_vde.common.hw,
> + [CLK_VCE] = &clk_vce.common.hw,
> + [CLK_NAND] = &clk_nand.common.hw,
> + [CLK_SD0] = &clk_sd0.common.hw,
> + [CLK_SD1] = &clk_sd1.common.hw,
> + [CLK_SD2] = &clk_sd2.common.hw,
> + [CLK_UART0] = &clk_uart0.common.hw,
> + [CLK_UART1] = &clk_uart1.common.hw,
> + [CLK_UART2] = &clk_uart2.common.hw,
> + [CLK_UART3] = &clk_uart3.common.hw,
> + [CLK_UART4] = &clk_uart4.common.hw,
> + [CLK_UART5] = &clk_uart5.common.hw,
> + [CLK_UART6] = &clk_uart6.common.hw,
> + [CLK_PWM0] = &clk_pwm0.common.hw,
> + [CLK_PWM1] = &clk_pwm1.common.hw,
> + [CLK_PWM2] = &clk_pwm2.common.hw,
> + [CLK_PWM3] = &clk_pwm3.common.hw,
> + [CLK_PWM4] = &clk_pwm4.common.hw,
> + [CLK_PWM5] = &clk_pwm5.common.hw,
> + [CLK_GPU3D] = &clk_gpu3d.common.hw,
> + [CLK_I2C0] = &clk_i2c0.common.hw,
> + [CLK_I2C1] = &clk_i2c1.common.hw,
> + [CLK_I2C2] = &clk_i2c2.common.hw,
> + [CLK_I2C3] = &clk_i2c3.common.hw,
> + [CLK_SPI0] = &clk_spi0.common.hw,
> + [CLK_SPI1] = &clk_spi1.common.hw,
> + [CLK_SPI2] = &clk_spi2.common.hw,
> + [CLK_SPI3] = &clk_spi3.common.hw,
> + [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw,
> + [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw,
> + [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw,
> + [CLK_USB3_CCE] = &clk_usb3_cce.common.hw,
> + [CLK_LCD] = &clk_lcd.common.hw,
> + [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw,
> + [CLK_I2SRX] = &clk_i2srx.common.hw,
> + [CLK_I2STX] = &clk_i2stx.common.hw,
> + [CLK_SENSOR0] = &clk_sensor0.common.hw,
> + [CLK_SENSOR1] = &clk_sensor1.common.hw,
> + [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw,
> + [CLK_ETHERNET] = &clk_ethernet.common.hw,
> + [CLK_RMII_REF] = &clk_rmii_ref.common.hw,
> + [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw,
> + [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw,
> + [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw,
> + [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw,
> + [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw,
> + [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw,
> + [CLK_TVOUT] = &clk_tvout.common.hw,
> + [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw,
> + [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw,
> + [CLK_PCM1] = &clk_pcm1.common.hw,
> + },
> + .num = CLK_NR_CLKS,
> +};
> +
> +static const struct owl_clk_desc s700_clk_desc = {
> + .clks = s700_clks,
> + .num_clks = ARRAY_SIZE(s700_clks),
> +
> + .hw_clks = &s700_hw_clks,
> +};
> +
> +static int s700_clk_probe(struct platform_device *pdev)
> +{
> + const struct owl_clk_desc *desc;
> +
> + desc = &s700_clk_desc;
> + owl_clk_regmap_init(pdev, desc);
> +
> + return owl_clk_probe(&pdev->dev, desc->hw_clks);
> +}
> +
> +static const struct of_device_id s700_clk_of_match[] = {
> + { .compatible = "actions,s700-cmu", },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver s700_clk_driver = {
> + .probe = s700_clk_probe,
> + .driver = {
> + .name = "s700-cmu",
> + .of_match_table = s700_clk_of_match
> + },
> +};
> +
> +static int __init s700_clk_init(void)
> +{
> + return platform_driver_register(&s700_clk_driver);
> +}
> +core_initcall(s700_clk_init);
> --
> 2.18.0
>

2018-06-30 09:33:28

by Manivannan Sadhasivam

[permalink] [raw]

Subject: Re: [PATCH v2 3/3] dt-bindings: clock: Modify Actions Soc clock bindings

Hi Saravanan,

I agree with modifying the existing binding to accomodate other
SoC's of the same family. But the binding should be
"actions,owl-cmu.txt" since it reflects the family name.

Andreas, what do you think?

On Thu, Jun 28, 2018 at 09:18:05PM +0200, Saravanan Sekar wrote:
> Modify clock bindings common Actions Semi Soc family S700/S900.
>
> Signed-off-by: Parthiban Nallathambi <[email protected]>
> Signed-off-by: Saravanan Sekar <[email protected]>
> ---
> ...tions,s900-cmu.txt => actions,sx00-cmu.txt} | 18 ++++++++++--------
> 1 file changed, 10 insertions(+), 8 deletions(-)
> rename Documentation/devicetree/bindings/clock/{actions,s900-cmu.txt => actions,sx00-cmu.txt} (71%)
>
> diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
> similarity index 71%
> rename from Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
> rename to Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
> index 93e4fb827cd6..8dc7edb4d198 100644
> --- a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
> +++ b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
> @@ -1,12 +1,14 @@
> -* Actions S900 Clock Management Unit (CMU)
> +* Actions S900/S700 Clock Management Unit (CMU)
>

Same as above. Should be Actions OWL SoC's Clock Management Unit (CMU).

> -The Actions S900 clock management unit generates and supplies clock to various
> -controllers within the SoC. The clock binding described here is applicable to
> -S900 SoC.
> +The Actions S900/S700 clock management unit generates and supplies clock to
> +various controllers within the SoC. The clock binding described here is
> +applicable to S900/S700 SoC.
>
> Required Properties:
>
> -- compatible: should be "actions,s900-cmu"
> +- compatible: should be one of this

Change to: compatible: should be one of the following:

Thanks,
Mani

> + "actions,s900-cmu"
> + "actions,s700-cmu"
> - reg: physical base address of the controller and length of memory mapped
> region.
> - clocks: Reference to the parent clocks ("hosc", "losc")
> @@ -15,9 +17,9 @@ Required Properties:
> Each clock is assigned an identifier, and client nodes can use this identifier
> to specify the clock which they consume.
>
> -All available clocks are defined as preprocessor macros in
> -dt-bindings/clock/actions,s900-cmu.h header and can be used in device
> -tree sources.
> +All available clocks are defined as preprocessor macros in corresponding
> +dt-bindings/clock/actions,s900-cmu.h or s700-cmu.h header and can be used in
> +device tree sources.
>
> External clocks:
>
> --
> 2.18.0
>

2018-06-30 09:52:37

by Manivannan Sadhasivam

[permalink] [raw]

Subject: Re: [PATCH v2 1/3] arm64: dts: actions: Enable clock controller for S700

On Thu, Jun 28, 2018 at 09:18:03PM +0200, Saravanan Sekar wrote:
> Added clock management controller for S700
>
> Signed-off-by: Parthiban Nallathambi <[email protected]>
> Signed-off-by: Saravanan Sekar <[email protected]>
> ---
> .../boot/dts/actions/s700-cubieboard7.dts | 7 -
> arch/arm64/boot/dts/actions/s700.dtsi | 8 ++
> include/dt-bindings/clock/actions,s700-cmu.h | 128 ++++++++++++++++++
> 3 files changed, 136 insertions(+), 7 deletions(-)
> create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h
>
> diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
> index ef79d7905f44..28f3f4a0f7f0 100644
> --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
> +++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
> @@ -28,12 +28,6 @@
> device_type = "memory";
> reg = <0x1 0xe0000000 0x0 0x0>;
> };
> -
> - uart3_clk: uart3-clk {
> - compatible = "fixed-clock";
> - clock-frequency = <921600>;
> - #clock-cells = <0>;
> - };

Sourcing CMU clock for UART should be in a separate patch.

> };
>
> &timer {
> @@ -42,5 +36,4 @@
>
> &uart3 {
> status = "okay";
> - clocks = <&uart3_clk>;
> };
> diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
> index 66dd5309f0a2..3530b705df90 100644
> --- a/arch/arm64/boot/dts/actions/s700.dtsi
> +++ b/arch/arm64/boot/dts/actions/s700.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/actions,s700-cmu.h>
>
> / {
> compatible = "actions,s700";
> @@ -44,6 +45,12 @@
> };
> };
>
> + clock: clock-controller@e0168000 {
> + compatible = "actions,s700-cmu";
> + reg = <0 0xe0168000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +

There is no fixed rate clock like losc?

> reserved-memory {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -129,6 +136,7 @@
> compatible = "actions,s900-uart", "actions,owl-uart";
> reg = <0x0 0xe0126000 0x0 0x2000>;
> interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clock CLK_UART3>;
> status = "disabled";
> };
>
> diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
> new file mode 100644
> index 000000000000..e5b4ea130953
> --- /dev/null
> +++ b/include/dt-bindings/clock/actions,s700-cmu.h
> @@ -0,0 +1,128 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Actions S700 clock driver
> + *
> + * Copyright (c) 2014 Actions Semi Inc.
> + * Author: David Liu <[email protected]>
> + *
> + * Author: Pathiban Nallathambi <[email protected]>
> + * Author: Saravanan Sekar <[email protected]>
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_S700_H
> +#define __DT_BINDINGS_CLOCK_S700_H
> +
> +#define CLK_NONE 0
> +
> +/* fixed rate clocks */
> +#define CLK_LOSC 1
> +#define CLK_HOSC 2
> +
> +/* pll clocks */
> +#define CLK_CORE_PLL 3
> +#define CLK_DEV_PLL 4
> +#define CLK_DDR_PLL 5
> +#define CLK_NAND_PLL 6
> +#define CLK_DISPLAY_PLL 7
> +#define CLK_TVOUT_PLL 8
> +#define CLK_CVBS_PLL 9
> +#define CLK_AUDIO_PLL 10
> +#define CLK_ETHERNET_PLL 11
> +

Remove extra new line please.

> +
> +/* system clock */
> +#define CLK_SYS_BASE 12
> +#define CLK_CPU CLK_SYS_BASE
> +#define CLK_DEV (CLK_SYS_BASE+1)
> +#define CLK_AHB (CLK_SYS_BASE+2)
> +#define CLK_APB (CLK_SYS_BASE+3)
> +#define CLK_DMAC (CLK_SYS_BASE+4)
> +#define CLK_NOC0_CLK_MUX (CLK_SYS_BASE+5)
> +#define CLK_NOC1_CLK_MUX (CLK_SYS_BASE+6)
> +#define CLK_HP_CLK_MUX (CLK_SYS_BASE+7)
> +#define CLK_HP_CLK_DIV (CLK_SYS_BASE+8)
> +#define CLK_NOC1_CLK_DIV (CLK_SYS_BASE+9)
> +#define CLK_NOC0 (CLK_SYS_BASE+10)
> +#define CLK_NOC1 (CLK_SYS_BASE+11)
> +#define CLK_SENOR_SRC (CLK_SYS_BASE+12)
> +
> +/* peripheral device clock */
> +#define CLK_PERIP_BASE 25
> +#define CLK_GPIO (CLK_PERIP_BASE)
> +#define CLK_TIMER (CLK_PERIP_BASE+1)
> +#define CLK_DSI (CLK_PERIP_BASE+2)
> +#define CLK_CSI (CLK_PERIP_BASE+3)
> +#define CLK_SI (CLK_PERIP_BASE+4)
> +#define CLK_DE (CLK_PERIP_BASE+5)
> +#define CLK_HDE (CLK_PERIP_BASE+6)
> +#define CLK_VDE (CLK_PERIP_BASE+7)
> +#define CLK_VCE (CLK_PERIP_BASE+8)
> +#define CLK_NAND (CLK_PERIP_BASE+9)
> +#define CLK_SD0 (CLK_PERIP_BASE+10)
> +#define CLK_SD1 (CLK_PERIP_BASE+11)
> +#define CLK_SD2 (CLK_PERIP_BASE+12)
> +
> +#define CLK_UART0 (CLK_PERIP_BASE+13)
> +#define CLK_UART1 (CLK_PERIP_BASE+14)
> +#define CLK_UART2 (CLK_PERIP_BASE+15)
> +#define CLK_UART3 (CLK_PERIP_BASE+16)
> +#define CLK_UART4 (CLK_PERIP_BASE+17)
> +#define CLK_UART5 (CLK_PERIP_BASE+18)
> +#define CLK_UART6 (CLK_PERIP_BASE+19)
> +
> +#define CLK_PWM0 (CLK_PERIP_BASE+20)
> +#define CLK_PWM1 (CLK_PERIP_BASE+21)
> +#define CLK_PWM2 (CLK_PERIP_BASE+22)
> +#define CLK_PWM3 (CLK_PERIP_BASE+23)
> +#define CLK_PWM4 (CLK_PERIP_BASE+24)
> +#define CLK_PWM5 (CLK_PERIP_BASE+25)
> +#define CLK_GPU3D (CLK_PERIP_BASE+26)
> +
> +#define CLK_I2C0 (CLK_PERIP_BASE+27)
> +#define CLK_I2C1 (CLK_PERIP_BASE+28)
> +#define CLK_I2C2 (CLK_PERIP_BASE+29)
> +#define CLK_I2C3 (CLK_PERIP_BASE+30)
> +
> +
> +#define CLK_SPI0 (CLK_PERIP_BASE+31)
> +#define CLK_SPI1 (CLK_PERIP_BASE+32)
> +#define CLK_SPI2 (CLK_PERIP_BASE+33)
> +#define CLK_SPI3 (CLK_PERIP_BASE+34)
> +
> +#define CLK_USB3_480MPLL0 (CLK_PERIP_BASE+35)
> +#define CLK_USB3_480MPHY0 (CLK_PERIP_BASE+36)
> +#define CLK_USB3_5GPHY (CLK_PERIP_BASE+37)
> +#define CLK_USB3_CCE (CLK_PERIP_BASE+48)
> +#define CLK_USB3_MAC (CLK_PERIP_BASE+49)
> +
> +
> +#define CLK_LCD (CLK_PERIP_BASE+50)
> +#define CLK_HDMI_AUDIO (CLK_PERIP_BASE+51)
> +#define CLK_I2SRX (CLK_PERIP_BASE+52)
> +#define CLK_I2STX (CLK_PERIP_BASE+53)
> +
> +#define CLK_SENSOR0 (CLK_PERIP_BASE+54)
> +#define CLK_SENSOR1 (CLK_PERIP_BASE+55)
> +
> +#define CLK_HDMI_DEV (CLK_PERIP_BASE+56)
> +
> +#define CLK_ETHERNET (CLK_PERIP_BASE+59)
> +#define CLK_RMII_REF (CLK_PERIP_BASE+60)
> +
> +#define CLK_USB2H0_PLLEN (CLK_PERIP_BASE+61)
> +#define CLK_USB2H0_PHY (CLK_PERIP_BASE+62)
> +#define CLK_USB2H0_CCE (CLK_PERIP_BASE+63)
> +#define CLK_USB2H1_PLLEN (CLK_PERIP_BASE+64)
> +#define CLK_USB2H1_PHY (CLK_PERIP_BASE+65)
> +#define CLK_USB2H1_CCE (CLK_PERIP_BASE+66)
> +
> +
> +#define CLK_TVOUT (CLK_PERIP_BASE+67)
> +
> +#define CLK_THERMAL_SENSOR (CLK_PERIP_BASE+68)
> +
> +#define CLK_IRC_SWITCH (CLK_PERIP_BASE+69)
> +#define CLK_PCM1 (CLK_PERIP_BASE+70)
> +#define CLK_NR_CLKS (CLK_PCM1) /* update on adding new clk */
> +

Since the index starts from 0, CLK_NR_CLKS should be CLK_PCM1 + 1

Thanks,
Mani

> +#endif /* __DT_BINDINGS_CLOCK_S700_H */
> --
> 2.18.0
>

2018-07-01 16:52:22

by saravanan sekar

[permalink] [raw]

Subject: Re: [PATCH v2 1/3] arm64: dts: actions: Enable clock controller for S700

Hi Stephen,

On 06/29/18 19:36, Stephen Boyd wrote:
> Quoting Saravanan Sekar (2018-06-28 12:18:03)
>> diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
>> index ef79d7905f44..28f3f4a0f7f0 100644
>> --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
>> +++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
>> diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
>> index 66dd5309f0a2..3530b705df90 100644
>> --- a/arch/arm64/boot/dts/actions/s700.dtsi
>> +++ b/arch/arm64/boot/dts/actions/s700.dtsi
> Can the above part be split from the below part? I don't want to merge
> dts bits into clk tree, when those should normally go through arm-soc.
Sure I will spilt into bindings commit
>> diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
>> new file mode 100644

2018-07-01 16:55:21

by saravanan sekar

[permalink] [raw]

Subject: Re: [PATCH v2 0/3] Add clock driver for Actions S700 SoC

Hi Stephen

On 06/29/18 19:38, Stephen Boyd wrote:
> Quoting Saravanan Sekar (2018-06-28 12:18:02)
>> Changelog v2:
>> Fixed 0 day compilation warning
>> Modified existing dts Actions S900 clock bindings common to Actions
>> Soc family
>>
>> This patchset adds clock support for Actions Semi OWL series S700 SoC
>> with relevant clock bindings and device tree info.
>>
>> Changed the UART clock using CMU instance and changes are tested in
>> cubieboard7
>>
>> Thanks and regards,
>> Saravanan,
>> Parthiban
>>
>> Saravanan Sekar (3):
>> arm64: dts: actions: Enable clock controller for S700
>> clk: actions: Add S700 SoC clock support
>> dt-bindings: clock: Modify Actions Soc clock bindings
> Normally this patch comes first, and then clk driver, and then dts bits.
> Also, the header file for the #define constants would be part of the
> bindings patch.

I will reorder the commit and split the patch

2018-07-01 17:25:39

by saravanan sekar

[permalink] [raw]

Subject: Re: [PATCH v2 2/3] clk: actions: Add S700 SoC clock support

On 06/30/18 11:22, Manivannan Sadhasivam wrote:
> Hi Saravanan,
>
> On Thu, Jun 28, 2018 at 09:18:04PM +0200, Saravanan Sekar wrote:
>> Add Actions Semi S700 SoC clock support
>>
>> Signed-off-by: Parthiban Nallathambi <[email protected]>
>> Signed-off-by: Saravanan Sekar <[email protected]>
>> ---
>> drivers/clk/actions/Kconfig | 7 +
>> drivers/clk/actions/Makefile | 1 +
>> drivers/clk/actions/owl-s700.c | 614 +++++++++++++++++++++++++++++++++
>> 3 files changed, 622 insertions(+)
>> create mode 100644 drivers/clk/actions/owl-s700.c
>>
>> diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig
>> index 8854adb37847..d883b48e4607 100644
>> --- a/drivers/clk/actions/Kconfig
>> +++ b/drivers/clk/actions/Kconfig
>> @@ -1,6 +1,7 @@
>> config CLK_ACTIONS
>> bool "Clock driver for Actions Semi SoCs"
>> depends on ARCH_ACTIONS || COMPILE_TEST
>> + select REGMAP_MMIO
> This change should be in a separate patch.

I don't see any specifc reason to split this as seperate patch, since
driver is bound to regmap

>> default ARCH_ACTIONS
>>
>> if CLK_ACTIONS
>> @@ -11,4 +12,10 @@ config CLK_OWL_S900
>> bool "Support for the Actions Semi OWL S900 clocks"
>> depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
>> default ARM64 && ARCH_ACTIONS
>> +
>> +config CLK_OWL_S700
>> + bool "Support for the Actions Semi OWL S700 clocks"
>> + depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
>> + default ARM64 && ARCH_ACTIONS
>> +
> It's good to keep the symbols alphabetically sorted (ascending order)

Will change the order

>> endif
>> diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
>> index 76e431434d10..a860973d940d 100644
>> --- a/drivers/clk/actions/Makefile
>> +++ b/drivers/clk/actions/Makefile
>> @@ -9,4 +9,5 @@ clk-owl-y += owl-composite.o
>> clk-owl-y += owl-pll.o
>>
>> # SoC support
>> +obj-$(CONFIG_CLK_OWL_S900) += owl-s700.o
> Should be CONFIG_CLK_OWL_S700

I will correct it

>> obj-$(CONFIG_CLK_OWL_S900) += owl-s900.o
>> diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c
>> new file mode 100644
>> index 000000000000..cc8d1f947171
>> --- /dev/null
>> +++ b/drivers/clk/actions/owl-s700.c
>> @@ -0,0 +1,614 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Actions S700 clock driver
>> + *
>> + * Copyright (c) 2014 Actions Semi Inc.
>> + * Author: David Liu <[email protected]>
>> + *
>> + * Author: Pathiban Nallathambi <[email protected]>
>> + * Author: Saravanan Sekar <[email protected]>
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "owl-common.h"
>> +#include "owl-composite.h"
>> +#include "owl-divider.h"
>> +#include "owl-factor.h"
>> +#include "owl-fixed-factor.h"
>> +#include "owl-gate.h"
>> +#include "owl-mux.h"
>> +#include "owl-pll.h"
>> +
>> +#include <dt-bindings/clock/actions,s700-cmu.h>
>> +
>> +#define CMU_COREPLL (0x0000)
>> +#define CMU_DEVPLL (0x0004)
>> +#define CMU_DDRPLL (0x0008)
>> +#define CMU_NANDPLL (0x000C)
>> +#define CMU_DISPLAYPLL (0x0010)
>> +#define CMU_AUDIOPLL (0x0014)
>> +#define CMU_TVOUTPLL (0x0018)
>> +#define CMU_BUSCLK (0x001C)
>> +#define CMU_SENSORCLK (0x0020)
>> +#define CMU_LCDCLK (0x0024)
>> +#define CMU_DSIPLLCLK (0x0028)
>> +#define CMU_CSICLK (0x002C)
>> +#define CMU_DECLK (0x0030)
>> +#define CMU_SICLK (0x0034)
>> +#define CMU_BUSCLK1 (0x0038)
>> +#define CMU_HDECLK (0x003C)
>> +#define CMU_VDECLK (0x0040)
>> +#define CMU_VCECLK (0x0044)
>> +#define CMU_NANDCCLK (0x004C)
>> +#define CMU_SD0CLK (0x0050)
>> +#define CMU_SD1CLK (0x0054)
>> +#define CMU_SD2CLK (0x0058)
>> +#define CMU_UART0CLK (0x005C)
>> +#define CMU_UART1CLK (0x0060)
>> +#define CMU_UART2CLK (0x0064)
>> +#define CMU_UART3CLK (0x0068)
>> +#define CMU_UART4CLK (0x006C)
>> +#define CMU_UART5CLK (0x0070)
>> +#define CMU_UART6CLK (0x0074)
>> +#define CMU_PWM0CLK (0x0078)
>> +#define CMU_PWM1CLK (0x007C)
>> +#define CMU_PWM2CLK (0x0080)
>> +#define CMU_PWM3CLK (0x0084)
>> +#define CMU_PWM4CLK (0x0088)
>> +#define CMU_PWM5CLK (0x008C)
>> +#define CMU_GPU3DCLK (0x0090)
>> +#define CMU_CORECTL (0x009C)
>> +#define CMU_DEVCLKEN0 (0x00A0)
>> +#define CMU_DEVCLKEN1 (0x00A4)
>> +#define CMU_DEVRST0 (0x00A8)
>> +#define CMU_DEVRST1 (0x00AC)
>> +#define CMU_USBPLL (0x00B0)
>> +#define CMU_ETHERNETPLL (0x00B4)
>> +#define CMU_CVBSPLL (0x00B8)
>> +#define CMU_SSTSCLK (0x00C0)
>> +
>> +static struct clk_pll_table clk_audio_pll_table[] = {
>> + {0, 45158400}, {1, 49152000},
>> + {0, 0},
>> +};
>> +
>> +static struct clk_pll_table clk_cvbs_pll_table[] = {
>> + {27, 29*12000000}, {28, 30*12000000}, {29, 31*12000000},
> Please leave a space around *

will change it

>> + {30, 32*12000000}, {31, 33*12000000}, {32, 34*12000000},
>> + {33, 35*12000000}, {34, 36*12000000}, {35, 37*12000000},
>> + {36, 38*12000000}, {37, 39*12000000}, {38, 40*12000000},
>> + {39, 41*12000000}, {40, 42*12000000}, {41, 43*12000000},
>> + {42, 44*12000000}, {43, 45*12000000}, {0, 0},
>> +};
>> +
>> +/* pll clocks */
>> +static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED);
>> +static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED);
>> +static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED);
>> +static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED);
>> +static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED);
>> +static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED);
>> +static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
>> +static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
>> +
>> +
> Remove extra new line

will remove

>> +static const char *cpu_clk_mux_p[] = {"losc", "hosc", "core_pll", "noc1_clk_div"};
>> +static const char *dev_clk_p[] = { "hosc", "dev_pll"};
>> +static const char *noc_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"};
>> +
>> +static const char *csi_clk_mux_p[] = { "display_pll", "dev_clk"};
>> +static const char *de_clk_mux_p[] = { "display_pll", "dev_clk"};
>> +static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"};
>> +static const char *nand_clk_mux_p[] = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"};
>> +static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll", };
>> +static const char *uart_clk_mux_p[] = { "hosc", "dev_pll"};
>> +static const char *pwm_clk_mux_p[] = { "losc", "hosc"};
>> +static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"};
>> +static const char *lcd_clk_mux_p[] = { "display_pll", "dev_clk" };
>> +static const char *i2s_clk_mux_p[] = { "audio_pll" };
>> +static const char *sensor_clk_mux_p[] = { "hosc", "si"};
>> +
>> +
> Remove extra new line

will remove

>> +/* mux clocks */
>> +static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
>> +static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
>> +static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT);
> Keep the spacing consistent.

will remove extra space

>> +static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT);
> ditto
>
>> +static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
>> +
>> +static struct clk_factor_table sd_factor_table[] = {
>> + /* bit0 ~ 4 */
>> + {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
>> + {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
>> + {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
>> + {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16},
>> + {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20},
>> + {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24},
>> + {24, 1, 25}, {25, 1, 26},
>> +
>> + /* bit8: /128 */
>> + {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128},
>> + {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128},
>> + {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128},
>> + {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128},
>> + {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128},
>> + {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
>> + {280, 1, 25 * 128}, {281, 1, 26 * 128},
>> +
>> + {0, 0},
>> +};
>> +
>> +static struct clk_factor_table lcd_factor_table[] = {
>> + /* bit0 ~ 3 */
>> + {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
>> + {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
>> + {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
>> +
>> + /* bit8: /7 */
>> + {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
>> + {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
>> + {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
>> + {0, 0},
>> +};
>> +
>> +
> Remove extra new line

sure

>> +static struct clk_div_table hdmia_div_table[] = {
>> + {0, 1}, {1, 2}, {2, 3}, {3, 4},
>> + {4, 6}, {5, 8}, {6, 12}, {7, 16},
>> + {8, 24},
>> + {0, 0},
>> +};
>> +
>> +static struct clk_div_table rmii_div_table[] = {
>> + {0, 4}, {1, 10},
>> +};
>> +
>> +
> Remove extra new line

sure

>> +/* divider clocks */
>> +static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0);
>> +static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0);
>> +static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0);
>> +static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
>> +static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
>> +static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
>> +static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0);
>> +static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0);
>> +static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0);
>> +
>> +static struct clk_factor_table de_factor_table[] = {
>> + {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
>> + {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
>> + {8, 1, 12}, {0, 0, 0},
>> +};
>> +
>> +static struct clk_factor_table hde_factor_table[] = {
>> + {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
>> + {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
>> + {0, 0, 0},
>> +};
>> +
>> +/* gate clocks */
>> +static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0);
>> +static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0);
>> +static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
> Timer clk enable bit should be 22 according to the datasheet I have.

Thanks for pointing out, I have refered datasheet and will correct it

>> +static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0);
>> +static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0);
>> +static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0);
>> +static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0);
>> +static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
>> +static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0);
>> +static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0);
>> +static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0);
>> +static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0);
>> +static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0);
>> +
>> +/* composite clocks */
>> +
>> +static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p,
>> + OWL_MUX_HW(CMU_CSICLK, 4, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
>> + OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p,
>> + OWL_MUX_HW(CMU_SICLK, 4, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
>> + OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
>> + 0);
>> +
>> +static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p,
>> + OWL_MUX_HW(CMU_DECLK, 12, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
>> + OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table),
>> + 0);
>> +
>> +static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p,
>> + OWL_MUX_HW(CMU_HDECLK, 4, 2),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
>> + OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table),
>> + 0);
>> +
>> +static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p,
>> + OWL_MUX_HW(CMU_VDECLK, 4, 2),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
>> + OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
>> + 0);
>> +
>> +static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p,
>> + OWL_MUX_HW(CMU_VCECLK, 4, 2),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
>> + OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p,
>> + OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
>> + OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
>> + CLK_SET_RATE_PARENT);
>> +
>> +static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p,
>> + OWL_MUX_HW(CMU_SD0CLK, 9, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
>> + OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
>> + 0);
>> +
>> +static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p,
>> + OWL_MUX_HW(CMU_SD1CLK, 9, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
>> + OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
>> + 0);
>> +
>> +static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p,
>> + OWL_MUX_HW(CMU_SD2CLK, 9, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0),
>> + OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
>> +#ifdef CONFIG_MMC_OWL_CLK_NANDPLL
> From where this define comes from?

Will add this options in the kconfig

>> + CLK_SET_RATE_PARENT);
>> +#else
>> + 0);
>> +#endif
>> +
>> +static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
>> + OWL_MUX_HW(CMU_UART0CLK, 16, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
>> + OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p,
>> + OWL_MUX_HW(CMU_UART1CLK, 16, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0),
>> + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p,
>> + OWL_MUX_HW(CMU_UART2CLK, 16, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0),
>> + OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p,
>> + OWL_MUX_HW(CMU_UART3CLK, 16, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0),
>> + OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p,
>> + OWL_MUX_HW(CMU_UART4CLK, 16, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0),
>> + OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p,
>> + OWL_MUX_HW(CMU_UART5CLK, 16, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0),
>> + OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p,
>> + OWL_MUX_HW(CMU_UART6CLK, 16, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
>> + OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p,
>> + OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0),
>> + OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
>> + CLK_IGNORE_UNUSED);
>> +
>> +static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p,
>> + OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
>> + OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p,
>> + OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
>> + OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p,
>> + OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
>> + OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p,
>> + OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
>> + OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p,
>> + OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
>> + OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
>> + 0);
>> +
>> +static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p,
> Please keep spacing consistent
>
>> + OWL_MUX_HW(CMU_GPU3DCLK, 4, 3),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
>> + OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table),
>> + 0);
>> +
>> +static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p,
> ditto
>
>> + OWL_MUX_HW(CMU_LCDCLK, 12, 2),
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0),
>> + OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p,
>> + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),/*CMU_AUDIOPLL 24,1 unused*/
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0),
>> + OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p,
>> + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0),
>> + OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
>> + 0);
>> +
>> +static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p,
>> + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
>> + OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
>> + 0);
>> +
>> +/* for bluetooth pcm communication */
>> +static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll",
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
>> + 1, 2, 0);
>> +
>> +static OWL_COMP_DIV(clk_senor_src, "sensor_src", sensor_clk_mux_p,
> Should be clk_sensor_src.

Will correct the typo

> Thanks,
> Mani
>
>> + OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
>> + {0},
>> + OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
>> + 0);
>> +
>> +static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll",
>> + OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
>> + 1, 20, 0);
>> +
>> +static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc",
>> + OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0),
>> + OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),
>> + 0);
>> +
>> +static struct owl_clk_common *s700_clks[] = {
>> + &clk_core_pll.common,
>> + &clk_dev_pll.common,
>> + &clk_ddr_pll.common,
>> + &clk_nand_pll.common,
>> + &clk_display_pll.common,
>> + &clk_cvbs_pll .common,
>> + &clk_audio_pll.common,
>> + &clk_ethernet_pll.common,
>> + &clk_cpu.common,
>> + &clk_dev.common,
>> + &clk_ahb.common,
>> + &clk_apb.common,
>> + &clk_dmac.common,
>> + &clk_noc0_clk_mux.common,
>> + &clk_noc1_clk_mux.common,
>> + &clk_hp_clk_mux.common,
>> + &clk_hp_clk_div.common,
>> + &clk_noc1_clk_div.common,
>> + &clk_noc0.common,
>> + &clk_noc1.common,
>> + &clk_senor_src.common,
>> + &clk_gpio.common,
>> + &clk_timer.common,
>> + &clk_dsi.common,
>> + &clk_csi.common,
>> + &clk_si.common,
>> + &clk_de.common,
>> + &clk_hde.common,
>> + &clk_vde.common,
>> + &clk_vce.common,
>> + &clk_nand.common,
>> + &clk_sd0.common,
>> + &clk_sd1.common,
>> + &clk_sd2.common,
>> + &clk_uart0.common,
>> + &clk_uart1.common,
>> + &clk_uart2.common,
>> + &clk_uart3.common,
>> + &clk_uart4.common,
>> + &clk_uart5.common,
>> + &clk_uart6.common,
>> + &clk_pwm0.common,
>> + &clk_pwm1.common,
>> + &clk_pwm2.common,
>> + &clk_pwm3.common,
>> + &clk_pwm4.common,
>> + &clk_pwm5.common,
>> + &clk_gpu3d.common,
>> + &clk_i2c0.common,
>> + &clk_i2c1.common,
>> + &clk_i2c2.common,
>> + &clk_i2c3.common,
>> + &clk_spi0.common,
>> + &clk_spi1.common,
>> + &clk_spi2.common,
>> + &clk_spi3.common,
>> + &clk_usb3_480mpll0.common,
>> + &clk_usb3_480mphy0.common,
>> + &clk_usb3_5gphy.common,
>> + &clk_usb3_cce.common,
>> + &clk_lcd.common,
>> + &clk_hdmi_audio.common,
>> + &clk_i2srx.common,
>> + &clk_i2stx.common,
>> + &clk_sensor0.common,
>> + &clk_sensor1.common,
>> + &clk_hdmi_dev.common,
>> + &clk_ethernet.common,
>> + &clk_rmii_ref.common,
>> + &clk_usb2h0_pllen.common,
>> + &clk_usb2h0_phy.common,
>> + &clk_usb2h0_cce.common,
>> + &clk_usb2h1_pllen.common,
>> + &clk_usb2h1_phy.common,
>> + &clk_usb2h1_cce.common,
>> + &clk_tvout.common,
>> + &clk_thermal_sensor.common,
>> + &clk_irc_switch.common,
>> + &clk_pcm1.common,
>> +};
>> +
>> +static struct clk_hw_onecell_data s700_hw_clks = {
>> + .hws = {
>> + [CLK_CORE_PLL] = &clk_core_pll.common.hw,
>> + [CLK_DEV_PLL] = &clk_dev_pll.common.hw,
>> + [CLK_DDR_PLL] = &clk_ddr_pll.common.hw,
>> + [CLK_NAND_PLL] = &clk_nand_pll.common.hw,
>> + [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw,
>> + [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw,
>> + [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw,
>> + [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw,
>> + [CLK_CPU] = &clk_cpu.common.hw,
>> + [CLK_DEV] = &clk_dev.common.hw,
>> + [CLK_AHB] = &clk_ahb.common.hw,
>> + [CLK_APB] = &clk_apb.common.hw,
>> + [CLK_DMAC] = &clk_dmac.common.hw,
>> + [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw,
>> + [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw,
>> + [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw,
>> + [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw,
>> + [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw,
>> + [CLK_NOC0] = &clk_noc0.common.hw,
>> + [CLK_NOC1] = &clk_noc1.common.hw,
>> + [CLK_SENOR_SRC] = &clk_senor_src.common.hw,
>> + [CLK_GPIO] = &clk_gpio.common.hw,
>> + [CLK_TIMER] = &clk_timer.common.hw,
>> + [CLK_DSI] = &clk_dsi.common.hw,
>> + [CLK_CSI] = &clk_csi.common.hw,
>> + [CLK_SI] = &clk_si.common.hw,
>> + [CLK_DE] = &clk_de.common.hw,
>> + [CLK_HDE] = &clk_hde.common.hw,
>> + [CLK_VDE] = &clk_vde.common.hw,
>> + [CLK_VCE] = &clk_vce.common.hw,
>> + [CLK_NAND] = &clk_nand.common.hw,
>> + [CLK_SD0] = &clk_sd0.common.hw,
>> + [CLK_SD1] = &clk_sd1.common.hw,
>> + [CLK_SD2] = &clk_sd2.common.hw,
>> + [CLK_UART0] = &clk_uart0.common.hw,
>> + [CLK_UART1] = &clk_uart1.common.hw,
>> + [CLK_UART2] = &clk_uart2.common.hw,
>> + [CLK_UART3] = &clk_uart3.common.hw,
>> + [CLK_UART4] = &clk_uart4.common.hw,
>> + [CLK_UART5] = &clk_uart5.common.hw,
>> + [CLK_UART6] = &clk_uart6.common.hw,
>> + [CLK_PWM0] = &clk_pwm0.common.hw,
>> + [CLK_PWM1] = &clk_pwm1.common.hw,
>> + [CLK_PWM2] = &clk_pwm2.common.hw,
>> + [CLK_PWM3] = &clk_pwm3.common.hw,
>> + [CLK_PWM4] = &clk_pwm4.common.hw,
>> + [CLK_PWM5] = &clk_pwm5.common.hw,
>> + [CLK_GPU3D] = &clk_gpu3d.common.hw,
>> + [CLK_I2C0] = &clk_i2c0.common.hw,
>> + [CLK_I2C1] = &clk_i2c1.common.hw,
>> + [CLK_I2C2] = &clk_i2c2.common.hw,
>> + [CLK_I2C3] = &clk_i2c3.common.hw,
>> + [CLK_SPI0] = &clk_spi0.common.hw,
>> + [CLK_SPI1] = &clk_spi1.common.hw,
>> + [CLK_SPI2] = &clk_spi2.common.hw,
>> + [CLK_SPI3] = &clk_spi3.common.hw,
>> + [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw,
>> + [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw,
>> + [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw,
>> + [CLK_USB3_CCE] = &clk_usb3_cce.common.hw,
>> + [CLK_LCD] = &clk_lcd.common.hw,
>> + [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw,
>> + [CLK_I2SRX] = &clk_i2srx.common.hw,
>> + [CLK_I2STX] = &clk_i2stx.common.hw,
>> + [CLK_SENSOR0] = &clk_sensor0.common.hw,
>> + [CLK_SENSOR1] = &clk_sensor1.common.hw,
>> + [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw,
>> + [CLK_ETHERNET] = &clk_ethernet.common.hw,
>> + [CLK_RMII_REF] = &clk_rmii_ref.common.hw,
>> + [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw,
>> + [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw,
>> + [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw,
>> + [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw,
>> + [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw,
>> + [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw,
>> + [CLK_TVOUT] = &clk_tvout.common.hw,
>> + [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw,
>> + [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw,
>> + [CLK_PCM1] = &clk_pcm1.common.hw,
>> + },
>> + .num = CLK_NR_CLKS,
>> +};
>> +
>> +static const struct owl_clk_desc s700_clk_desc = {
>> + .clks = s700_clks,
>> + .num_clks = ARRAY_SIZE(s700_clks),
>> +
>> + .hw_clks = &s700_hw_clks,
>> +};
>> +
>> +static int s700_clk_probe(struct platform_device *pdev)
>> +{
>> + const struct owl_clk_desc *desc;
>> +
>> + desc = &s700_clk_desc;
>> + owl_clk_regmap_init(pdev, desc);
>> +
>> + return owl_clk_probe(&pdev->dev, desc->hw_clks);
>> +}
>> +
>> +static const struct of_device_id s700_clk_of_match[] = {
>> + { .compatible = "actions,s700-cmu", },
>> + { /* sentinel */ }
>> +};
>> +
>> +static struct platform_driver s700_clk_driver = {
>> + .probe = s700_clk_probe,
>> + .driver = {
>> + .name = "s700-cmu",
>> + .of_match_table = s700_clk_of_match
>> + },
>> +};
>> +
>> +static int __init s700_clk_init(void)
>> +{
>> + return platform_driver_register(&s700_clk_driver);
>> +}
>> +core_initcall(s700_clk_init);
>> --
>> 2.18.0
>>

2018-07-01 17:28:51

by saravanan sekar

[permalink] [raw]

Subject: Re: [PATCH v2 3/3] dt-bindings: clock: Modify Actions Soc clock bindings

Hi Mani

On 06/30/18 11:32, Manivannan Sadhasivam wrote:
> Hi Saravanan,
>
> I agree with modifying the existing binding to accomodate other
> SoC's of the same family. But the binding should be
> "actions,owl-cmu.txt" since it reflects the family name.

Agree, will modify the name

> Andreas, what do you think?
>
> On Thu, Jun 28, 2018 at 09:18:05PM +0200, Saravanan Sekar wrote:
>> Modify clock bindings common Actions Semi Soc family S700/S900.
>>
>> Signed-off-by: Parthiban Nallathambi <[email protected]>
>> Signed-off-by: Saravanan Sekar <[email protected]>
>> ---
>> ...tions,s900-cmu.txt => actions,sx00-cmu.txt} | 18 ++++++++++--------
>> 1 file changed, 10 insertions(+), 8 deletions(-)
>> rename Documentation/devicetree/bindings/clock/{actions,s900-cmu.txt => actions,sx00-cmu.txt} (71%)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
>> similarity index 71%
>> rename from Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
>> rename to Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
>> index 93e4fb827cd6..8dc7edb4d198 100644
>> --- a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
>> +++ b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
>> @@ -1,12 +1,14 @@
>> -* Actions S900 Clock Management Unit (CMU)
>> +* Actions S900/S700 Clock Management Unit (CMU)
>>
> Same as above. Should be Actions OWL SoC's Clock Management Unit (CMU).

sure

>> -The Actions S900 clock management unit generates and supplies clock to various
>> -controllers within the SoC. The clock binding described here is applicable to
>> -S900 SoC.
>> +The Actions S900/S700 clock management unit generates and supplies clock to
>> +various controllers within the SoC. The clock binding described here is
>> +applicable to S900/S700 SoC.
>>
>> Required Properties:
>>
>> -- compatible: should be "actions,s900-cmu"
>> +- compatible: should be one of this
> Change to: compatible: should be one of the following:

sure

> Thanks,
> Mani
>
>> + "actions,s900-cmu"
>> + "actions,s700-cmu"
>> - reg: physical base address of the controller and length of memory mapped
>> region.
>> - clocks: Reference to the parent clocks ("hosc", "losc")
>> @@ -15,9 +17,9 @@ Required Properties:
>> Each clock is assigned an identifier, and client nodes can use this identifier
>> to specify the clock which they consume.
>>
>> -All available clocks are defined as preprocessor macros in
>> -dt-bindings/clock/actions,s900-cmu.h header and can be used in device
>> -tree sources.
>> +All available clocks are defined as preprocessor macros in corresponding
>> +dt-bindings/clock/actions,s900-cmu.h or s700-cmu.h header and can be used in
>> +device tree sources.
>>
>> External clocks:
>>
>> --
>> 2.18.0
>>

Thanks,
Saravanan

2018-07-01 17:32:04

by Manivannan Sadhasivam

[permalink] [raw]

Subject: Re: [PATCH v2 2/3] clk: actions: Add S700 SoC clock support

On Sun, Jul 01, 2018 at 07:23:58PM +0200, Saravanan Sekar wrote:
>
>
> On 06/30/18 11:22, Manivannan Sadhasivam wrote:
> > Hi Saravanan,
> >
> > On Thu, Jun 28, 2018 at 09:18:04PM +0200, Saravanan Sekar wrote:
> > > Add Actions Semi S700 SoC clock support
> > >
> > > Signed-off-by: Parthiban Nallathambi <[email protected]>
> > > Signed-off-by: Saravanan Sekar <[email protected]>
> > > ---
> > > drivers/clk/actions/Kconfig | 7 +
> > > drivers/clk/actions/Makefile | 1 +
> > > drivers/clk/actions/owl-s700.c | 614 +++++++++++++++++++++++++++++++++
> > > 3 files changed, 622 insertions(+)
> > > create mode 100644 drivers/clk/actions/owl-s700.c
> > >
> > > diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig
> > > index 8854adb37847..d883b48e4607 100644
> > > --- a/drivers/clk/actions/Kconfig
> > > +++ b/drivers/clk/actions/Kconfig
> > > @@ -1,6 +1,7 @@
> > > config CLK_ACTIONS
> > > bool "Clock driver for Actions Semi SoCs"
> > > depends on ARCH_ACTIONS || COMPILE_TEST
> > > + select REGMAP_MMIO
> > This change should be in a separate patch.
>
> I don't see any specifc reason to split this as seperate patch, since driver
> is bound to regmap
>

I'd say this is a fix to the Owl common clk code rather than an addition
for the S700 SoC. So this should be in a separate patch.

Thanks,
Mani

>
> > > default ARCH_ACTIONS
> > > if CLK_ACTIONS
> > > @@ -11,4 +12,10 @@ config CLK_OWL_S900
> > > bool "Support for the Actions Semi OWL S900 clocks"
> > > depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
> > > default ARM64 && ARCH_ACTIONS
> > > +
> > > +config CLK_OWL_S700
> > > + bool "Support for the Actions Semi OWL S700 clocks"
> > > + depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
> > > + default ARM64 && ARCH_ACTIONS
> > > +
> > It's good to keep the symbols alphabetically sorted (ascending order)
>
> Will change the order
>
> > > endif
> > > diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
> > > index 76e431434d10..a860973d940d 100644
> > > --- a/drivers/clk/actions/Makefile
> > > +++ b/drivers/clk/actions/Makefile
> > > @@ -9,4 +9,5 @@ clk-owl-y += owl-composite.o
> > > clk-owl-y += owl-pll.o
> > > # SoC support
> > > +obj-$(CONFIG_CLK_OWL_S900) += owl-s700.o
> > Should be CONFIG_CLK_OWL_S700
>
> I will correct it
>
> > > obj-$(CONFIG_CLK_OWL_S900) += owl-s900.o
> > > diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c
> > > new file mode 100644
> > > index 000000000000..cc8d1f947171
> > > --- /dev/null
> > > +++ b/drivers/clk/actions/owl-s700.c
> > > @@ -0,0 +1,614 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Actions S700 clock driver
> > > + *
> > > + * Copyright (c) 2014 Actions Semi Inc.
> > > + * Author: David Liu <[email protected]>
> > > + *
> > > + * Author: Pathiban Nallathambi <[email protected]>
> > > + * Author: Saravanan Sekar <[email protected]>
> > > + */
> > > +
> > > +#include <linux/clk-provider.h>
> > > +#include <linux/platform_device.h>
> > > +
> > > +#include "owl-common.h"
> > > +#include "owl-composite.h"
> > > +#include "owl-divider.h"
> > > +#include "owl-factor.h"
> > > +#include "owl-fixed-factor.h"
> > > +#include "owl-gate.h"
> > > +#include "owl-mux.h"
> > > +#include "owl-pll.h"
> > > +
> > > +#include <dt-bindings/clock/actions,s700-cmu.h>
> > > +
> > > +#define CMU_COREPLL (0x0000)
> > > +#define CMU_DEVPLL (0x0004)
> > > +#define CMU_DDRPLL (0x0008)
> > > +#define CMU_NANDPLL (0x000C)
> > > +#define CMU_DISPLAYPLL (0x0010)
> > > +#define CMU_AUDIOPLL (0x0014)
> > > +#define CMU_TVOUTPLL (0x0018)
> > > +#define CMU_BUSCLK (0x001C)
> > > +#define CMU_SENSORCLK (0x0020)
> > > +#define CMU_LCDCLK (0x0024)
> > > +#define CMU_DSIPLLCLK (0x0028)
> > > +#define CMU_CSICLK (0x002C)
> > > +#define CMU_DECLK (0x0030)
> > > +#define CMU_SICLK (0x0034)
> > > +#define CMU_BUSCLK1 (0x0038)
> > > +#define CMU_HDECLK (0x003C)
> > > +#define CMU_VDECLK (0x0040)
> > > +#define CMU_VCECLK (0x0044)
> > > +#define CMU_NANDCCLK (0x004C)
> > > +#define CMU_SD0CLK (0x0050)
> > > +#define CMU_SD1CLK (0x0054)
> > > +#define CMU_SD2CLK (0x0058)
> > > +#define CMU_UART0CLK (0x005C)
> > > +#define CMU_UART1CLK (0x0060)
> > > +#define CMU_UART2CLK (0x0064)
> > > +#define CMU_UART3CLK (0x0068)
> > > +#define CMU_UART4CLK (0x006C)
> > > +#define CMU_UART5CLK (0x0070)
> > > +#define CMU_UART6CLK (0x0074)
> > > +#define CMU_PWM0CLK (0x0078)
> > > +#define CMU_PWM1CLK (0x007C)
> > > +#define CMU_PWM2CLK (0x0080)
> > > +#define CMU_PWM3CLK (0x0084)
> > > +#define CMU_PWM4CLK (0x0088)
> > > +#define CMU_PWM5CLK (0x008C)
> > > +#define CMU_GPU3DCLK (0x0090)
> > > +#define CMU_CORECTL (0x009C)
> > > +#define CMU_DEVCLKEN0 (0x00A0)
> > > +#define CMU_DEVCLKEN1 (0x00A4)
> > > +#define CMU_DEVRST0 (0x00A8)
> > > +#define CMU_DEVRST1 (0x00AC)
> > > +#define CMU_USBPLL (0x00B0)
> > > +#define CMU_ETHERNETPLL (0x00B4)
> > > +#define CMU_CVBSPLL (0x00B8)
> > > +#define CMU_SSTSCLK (0x00C0)
> > > +
> > > +static struct clk_pll_table clk_audio_pll_table[] = {
> > > + {0, 45158400}, {1, 49152000},
> > > + {0, 0},
> > > +};
> > > +
> > > +static struct clk_pll_table clk_cvbs_pll_table[] = {
> > > + {27, 29*12000000}, {28, 30*12000000}, {29, 31*12000000},
> > Please leave a space around *
>
> will change it
>
> > > + {30, 32*12000000}, {31, 33*12000000}, {32, 34*12000000},
> > > + {33, 35*12000000}, {34, 36*12000000}, {35, 37*12000000},
> > > + {36, 38*12000000}, {37, 39*12000000}, {38, 40*12000000},
> > > + {39, 41*12000000}, {40, 42*12000000}, {41, 43*12000000},
> > > + {42, 44*12000000}, {43, 45*12000000}, {0, 0},
> > > +};
> > > +
> > > +/* pll clocks */
> > > +static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED);
> > > +static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED);
> > > +static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED);
> > > +static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED);
> > > +static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED);
> > > +static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED);
> > > +static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
> > > +static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
> > > +
> > > +
> > Remove extra new line
>
> will remove
>
> > > +static const char *cpu_clk_mux_p[] = {"losc", "hosc", "core_pll", "noc1_clk_div"};
> > > +static const char *dev_clk_p[] = { "hosc", "dev_pll"};
> > > +static const char *noc_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"};
> > > +
> > > +static const char *csi_clk_mux_p[] = { "display_pll", "dev_clk"};
> > > +static const char *de_clk_mux_p[] = { "display_pll", "dev_clk"};
> > > +static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"};
> > > +static const char *nand_clk_mux_p[] = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"};
> > > +static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll", };
> > > +static const char *uart_clk_mux_p[] = { "hosc", "dev_pll"};
> > > +static const char *pwm_clk_mux_p[] = { "losc", "hosc"};
> > > +static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"};
> > > +static const char *lcd_clk_mux_p[] = { "display_pll", "dev_clk" };
> > > +static const char *i2s_clk_mux_p[] = { "audio_pll" };
> > > +static const char *sensor_clk_mux_p[] = { "hosc", "si"};
> > > +
> > > +
> > Remove extra new line
>
> will remove
>
> > > +/* mux clocks */
> > > +static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
> > > +static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
> > > +static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT);
> > Keep the spacing consistent.
>
> will remove extra space
>
> > > +static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT);
> > ditto
> >
> > > +static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
> > > +
> > > +static struct clk_factor_table sd_factor_table[] = {
> > > + /* bit0 ~ 4 */
> > > + {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
> > > + {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
> > > + {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
> > > + {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16},
> > > + {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20},
> > > + {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24},
> > > + {24, 1, 25}, {25, 1, 26},
> > > +
> > > + /* bit8: /128 */
> > > + {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128},
> > > + {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128},
> > > + {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128},
> > > + {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128},
> > > + {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128},
> > > + {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
> > > + {280, 1, 25 * 128}, {281, 1, 26 * 128},
> > > +
> > > + {0, 0},
> > > +};
> > > +
> > > +static struct clk_factor_table lcd_factor_table[] = {
> > > + /* bit0 ~ 3 */
> > > + {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
> > > + {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
> > > + {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
> > > +
> > > + /* bit8: /7 */
> > > + {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
> > > + {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
> > > + {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
> > > + {0, 0},
> > > +};
> > > +
> > > +
> > Remove extra new line
>
> sure
>
> > > +static struct clk_div_table hdmia_div_table[] = {
> > > + {0, 1}, {1, 2}, {2, 3}, {3, 4},
> > > + {4, 6}, {5, 8}, {6, 12}, {7, 16},
> > > + {8, 24},
> > > + {0, 0},
> > > +};
> > > +
> > > +static struct clk_div_table rmii_div_table[] = {
> > > + {0, 4}, {1, 10},
> > > +};
> > > +
> > > +
> > Remove extra new line
>
> sure
>
>
> > > +/* divider clocks */
> > > +static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0);
> > > +static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0);
> > > +static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0);
> > > +static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> > > +static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
> > > +static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
> > > +static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0);
> > > +static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0);
> > > +static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0);
> > > +
> > > +static struct clk_factor_table de_factor_table[] = {
> > > + {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
> > > + {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
> > > + {8, 1, 12}, {0, 0, 0},
> > > +};
> > > +
> > > +static struct clk_factor_table hde_factor_table[] = {
> > > + {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
> > > + {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
> > > + {0, 0, 0},
> > > +};
> > > +
> > > +/* gate clocks */
> > > +static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0);
> > > +static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0);
> > > +static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
> > Timer clk enable bit should be 22 according to the datasheet I have.
>
> Thanks for pointing out, I have refered datasheet and will correct it
>
> > > +static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0);
> > > +static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0);
> > > +static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0);
> > > +static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0);
> > > +static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
> > > +static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0);
> > > +static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0);
> > > +static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0);
> > > +static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0);
> > > +static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0);
> > > +
> > > +/* composite clocks */
> > > +
> > > +static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p,
> > > + OWL_MUX_HW(CMU_CSICLK, 4, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
> > > + OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p,
> > > + OWL_MUX_HW(CMU_SICLK, 4, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
> > > + OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p,
> > > + OWL_MUX_HW(CMU_DECLK, 12, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
> > > + OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table),
> > > + 0);
> > > +
> > > +static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p,
> > > + OWL_MUX_HW(CMU_HDECLK, 4, 2),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
> > > + OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table),
> > > + 0);
> > > +
> > > +static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p,
> > > + OWL_MUX_HW(CMU_VDECLK, 4, 2),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
> > > + OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
> > > + 0);
> > > +
> > > +static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p,
> > > + OWL_MUX_HW(CMU_VCECLK, 4, 2),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
> > > + OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p,
> > > + OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
> > > + OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
> > > + CLK_SET_RATE_PARENT);
> > > +
> > > +static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p,
> > > + OWL_MUX_HW(CMU_SD0CLK, 9, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
> > > + OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
> > > + 0);
> > > +
> > > +static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p,
> > > + OWL_MUX_HW(CMU_SD1CLK, 9, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
> > > + OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
> > > + 0);
> > > +
> > > +static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p,
> > > + OWL_MUX_HW(CMU_SD2CLK, 9, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0),
> > > + OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
> > > +#ifdef CONFIG_MMC_OWL_CLK_NANDPLL
> > From where this define comes from?
>
> Will add this options in the kconfig
>
>
> > > + CLK_SET_RATE_PARENT);
> > > +#else
> > > + 0);
> > > +#endif
> > > +
> > > +static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
> > > + OWL_MUX_HW(CMU_UART0CLK, 16, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
> > > + OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p,
> > > + OWL_MUX_HW(CMU_UART1CLK, 16, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0),
> > > + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p,
> > > + OWL_MUX_HW(CMU_UART2CLK, 16, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0),
> > > + OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p,
> > > + OWL_MUX_HW(CMU_UART3CLK, 16, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0),
> > > + OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p,
> > > + OWL_MUX_HW(CMU_UART4CLK, 16, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0),
> > > + OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p,
> > > + OWL_MUX_HW(CMU_UART5CLK, 16, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0),
> > > + OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p,
> > > + OWL_MUX_HW(CMU_UART6CLK, 16, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
> > > + OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p,
> > > + OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0),
> > > + OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
> > > + CLK_IGNORE_UNUSED);
> > > +
> > > +static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p,
> > > + OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
> > > + OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p,
> > > + OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
> > > + OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p,
> > > + OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
> > > + OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p,
> > > + OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
> > > + OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p,
> > > + OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
> > > + OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p,
> > Please keep spacing consistent
> >
> > > + OWL_MUX_HW(CMU_GPU3DCLK, 4, 3),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
> > > + OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table),
> > > + 0);
> > > +
> > > +static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p,
> > ditto
> >
> > > + OWL_MUX_HW(CMU_LCDCLK, 12, 2),
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0),
> > > + OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p,
> > > + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),/*CMU_AUDIOPLL 24,1 unused*/
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0),
> > > + OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p,
> > > + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0),
> > > + OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
> > > + 0);
> > > +
> > > +static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p,
> > > + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
> > > + OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
> > > + 0);
> > > +
> > > +/* for bluetooth pcm communication */
> > > +static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll",
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
> > > + 1, 2, 0);
> > > +
> > > +static OWL_COMP_DIV(clk_senor_src, "sensor_src", sensor_clk_mux_p,
> > Should be clk_sensor_src.
>
> Will correct the typo
>
> > Thanks,
> > Mani
> >
> > > + OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
> > > + {0},
> > > + OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
> > > + 0);
> > > +
> > > +static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll",
> > > + OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
> > > + 1, 20, 0);
> > > +
> > > +static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc",
> > > + OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0),
> > > + OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),
> > > + 0);
> > > +
> > > +static struct owl_clk_common *s700_clks[] = {
> > > + &clk_core_pll.common,
> > > + &clk_dev_pll.common,
> > > + &clk_ddr_pll.common,
> > > + &clk_nand_pll.common,
> > > + &clk_display_pll.common,
> > > + &clk_cvbs_pll .common,
> > > + &clk_audio_pll.common,
> > > + &clk_ethernet_pll.common,
> > > + &clk_cpu.common,
> > > + &clk_dev.common,
> > > + &clk_ahb.common,
> > > + &clk_apb.common,
> > > + &clk_dmac.common,
> > > + &clk_noc0_clk_mux.common,
> > > + &clk_noc1_clk_mux.common,
> > > + &clk_hp_clk_mux.common,
> > > + &clk_hp_clk_div.common,
> > > + &clk_noc1_clk_div.common,
> > > + &clk_noc0.common,
> > > + &clk_noc1.common,
> > > + &clk_senor_src.common,
> > > + &clk_gpio.common,
> > > + &clk_timer.common,
> > > + &clk_dsi.common,
> > > + &clk_csi.common,
> > > + &clk_si.common,
> > > + &clk_de.common,
> > > + &clk_hde.common,
> > > + &clk_vde.common,
> > > + &clk_vce.common,
> > > + &clk_nand.common,
> > > + &clk_sd0.common,
> > > + &clk_sd1.common,
> > > + &clk_sd2.common,
> > > + &clk_uart0.common,
> > > + &clk_uart1.common,
> > > + &clk_uart2.common,
> > > + &clk_uart3.common,
> > > + &clk_uart4.common,
> > > + &clk_uart5.common,
> > > + &clk_uart6.common,
> > > + &clk_pwm0.common,
> > > + &clk_pwm1.common,
> > > + &clk_pwm2.common,
> > > + &clk_pwm3.common,
> > > + &clk_pwm4.common,
> > > + &clk_pwm5.common,
> > > + &clk_gpu3d.common,
> > > + &clk_i2c0.common,
> > > + &clk_i2c1.common,
> > > + &clk_i2c2.common,
> > > + &clk_i2c3.common,
> > > + &clk_spi0.common,
> > > + &clk_spi1.common,
> > > + &clk_spi2.common,
> > > + &clk_spi3.common,
> > > + &clk_usb3_480mpll0.common,
> > > + &clk_usb3_480mphy0.common,
> > > + &clk_usb3_5gphy.common,
> > > + &clk_usb3_cce.common,
> > > + &clk_lcd.common,
> > > + &clk_hdmi_audio.common,
> > > + &clk_i2srx.common,
> > > + &clk_i2stx.common,
> > > + &clk_sensor0.common,
> > > + &clk_sensor1.common,
> > > + &clk_hdmi_dev.common,
> > > + &clk_ethernet.common,
> > > + &clk_rmii_ref.common,
> > > + &clk_usb2h0_pllen.common,
> > > + &clk_usb2h0_phy.common,
> > > + &clk_usb2h0_cce.common,
> > > + &clk_usb2h1_pllen.common,
> > > + &clk_usb2h1_phy.common,
> > > + &clk_usb2h1_cce.common,
> > > + &clk_tvout.common,
> > > + &clk_thermal_sensor.common,
> > > + &clk_irc_switch.common,
> > > + &clk_pcm1.common,
> > > +};
> > > +
> > > +static struct clk_hw_onecell_data s700_hw_clks = {
> > > + .hws = {
> > > + [CLK_CORE_PLL] = &clk_core_pll.common.hw,
> > > + [CLK_DEV_PLL] = &clk_dev_pll.common.hw,
> > > + [CLK_DDR_PLL] = &clk_ddr_pll.common.hw,
> > > + [CLK_NAND_PLL] = &clk_nand_pll.common.hw,
> > > + [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw,
> > > + [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw,
> > > + [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw,
> > > + [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw,
> > > + [CLK_CPU] = &clk_cpu.common.hw,
> > > + [CLK_DEV] = &clk_dev.common.hw,
> > > + [CLK_AHB] = &clk_ahb.common.hw,
> > > + [CLK_APB] = &clk_apb.common.hw,
> > > + [CLK_DMAC] = &clk_dmac.common.hw,
> > > + [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw,
> > > + [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw,
> > > + [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw,
> > > + [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw,
> > > + [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw,
> > > + [CLK_NOC0] = &clk_noc0.common.hw,
> > > + [CLK_NOC1] = &clk_noc1.common.hw,
> > > + [CLK_SENOR_SRC] = &clk_senor_src.common.hw,
> > > + [CLK_GPIO] = &clk_gpio.common.hw,
> > > + [CLK_TIMER] = &clk_timer.common.hw,
> > > + [CLK_DSI] = &clk_dsi.common.hw,
> > > + [CLK_CSI] = &clk_csi.common.hw,
> > > + [CLK_SI] = &clk_si.common.hw,
> > > + [CLK_DE] = &clk_de.common.hw,
> > > + [CLK_HDE] = &clk_hde.common.hw,
> > > + [CLK_VDE] = &clk_vde.common.hw,
> > > + [CLK_VCE] = &clk_vce.common.hw,
> > > + [CLK_NAND] = &clk_nand.common.hw,
> > > + [CLK_SD0] = &clk_sd0.common.hw,
> > > + [CLK_SD1] = &clk_sd1.common.hw,
> > > + [CLK_SD2] = &clk_sd2.common.hw,
> > > + [CLK_UART0] = &clk_uart0.common.hw,
> > > + [CLK_UART1] = &clk_uart1.common.hw,
> > > + [CLK_UART2] = &clk_uart2.common.hw,
> > > + [CLK_UART3] = &clk_uart3.common.hw,
> > > + [CLK_UART4] = &clk_uart4.common.hw,
> > > + [CLK_UART5] = &clk_uart5.common.hw,
> > > + [CLK_UART6] = &clk_uart6.common.hw,
> > > + [CLK_PWM0] = &clk_pwm0.common.hw,
> > > + [CLK_PWM1] = &clk_pwm1.common.hw,
> > > + [CLK_PWM2] = &clk_pwm2.common.hw,
> > > + [CLK_PWM3] = &clk_pwm3.common.hw,
> > > + [CLK_PWM4] = &clk_pwm4.common.hw,
> > > + [CLK_PWM5] = &clk_pwm5.common.hw,
> > > + [CLK_GPU3D] = &clk_gpu3d.common.hw,
> > > + [CLK_I2C0] = &clk_i2c0.common.hw,
> > > + [CLK_I2C1] = &clk_i2c1.common.hw,
> > > + [CLK_I2C2] = &clk_i2c2.common.hw,
> > > + [CLK_I2C3] = &clk_i2c3.common.hw,
> > > + [CLK_SPI0] = &clk_spi0.common.hw,
> > > + [CLK_SPI1] = &clk_spi1.common.hw,
> > > + [CLK_SPI2] = &clk_spi2.common.hw,
> > > + [CLK_SPI3] = &clk_spi3.common.hw,
> > > + [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw,
> > > + [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw,
> > > + [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw,
> > > + [CLK_USB3_CCE] = &clk_usb3_cce.common.hw,
> > > + [CLK_LCD] = &clk_lcd.common.hw,
> > > + [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw,
> > > + [CLK_I2SRX] = &clk_i2srx.common.hw,
> > > + [CLK_I2STX] = &clk_i2stx.common.hw,
> > > + [CLK_SENSOR0] = &clk_sensor0.common.hw,
> > > + [CLK_SENSOR1] = &clk_sensor1.common.hw,
> > > + [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw,
> > > + [CLK_ETHERNET] = &clk_ethernet.common.hw,
> > > + [CLK_RMII_REF] = &clk_rmii_ref.common.hw,
> > > + [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw,
> > > + [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw,
> > > + [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw,
> > > + [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw,
> > > + [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw,
> > > + [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw,
> > > + [CLK_TVOUT] = &clk_tvout.common.hw,
> > > + [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw,
> > > + [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw,
> > > + [CLK_PCM1] = &clk_pcm1.common.hw,
> > > + },
> > > + .num = CLK_NR_CLKS,
> > > +};
> > > +
> > > +static const struct owl_clk_desc s700_clk_desc = {
> > > + .clks = s700_clks,
> > > + .num_clks = ARRAY_SIZE(s700_clks),
> > > +
> > > + .hw_clks = &s700_hw_clks,
> > > +};
> > > +
> > > +static int s700_clk_probe(struct platform_device *pdev)
> > > +{
> > > + const struct owl_clk_desc *desc;
> > > +
> > > + desc = &s700_clk_desc;
> > > + owl_clk_regmap_init(pdev, desc);
> > > +
> > > + return owl_clk_probe(&pdev->dev, desc->hw_clks);
> > > +}
> > > +
> > > +static const struct of_device_id s700_clk_of_match[] = {
> > > + { .compatible = "actions,s700-cmu", },
> > > + { /* sentinel */ }
> > > +};
> > > +
> > > +static struct platform_driver s700_clk_driver = {
> > > + .probe = s700_clk_probe,
> > > + .driver = {
> > > + .name = "s700-cmu",
> > > + .of_match_table = s700_clk_of_match
> > > + },
> > > +};
> > > +
> > > +static int __init s700_clk_init(void)
> > > +{
> > > + return platform_driver_register(&s700_clk_driver);
> > > +}
> > > +core_initcall(s700_clk_init);
> > > --
> > > 2.18.0
> > >
>

2018-07-01 17:39:16

by Manivannan Sadhasivam

[permalink] [raw]

Subject: Re: [PATCH v2 3/3] dt-bindings: clock: Modify Actions Soc clock bindings

On Sun, Jul 01, 2018 at 07:26:20PM +0200, Saravanan Sekar wrote:
> Hi Mani
>
>
> On 06/30/18 11:32, Manivannan Sadhasivam wrote:
> > Hi Saravanan,
> >
> > I agree with modifying the existing binding to accomodate other
> > SoC's of the same family. But the binding should be
> > "actions,owl-cmu.txt" since it reflects the family name.
>
> Agree, will modify the name
>
> > Andreas, what do you think?
> >
> > On Thu, Jun 28, 2018 at 09:18:05PM +0200, Saravanan Sekar wrote:
> > > Modify clock bindings common Actions Semi Soc family S700/S900.
> > >
> > > Signed-off-by: Parthiban Nallathambi <[email protected]>
> > > Signed-off-by: Saravanan Sekar <[email protected]>
> > > ---
> > > ...tions,s900-cmu.txt => actions,sx00-cmu.txt} | 18 ++++++++++--------
> > > 1 file changed, 10 insertions(+), 8 deletions(-)
> > > rename Documentation/devicetree/bindings/clock/{actions,s900-cmu.txt => actions,sx00-cmu.txt} (71%)
> > >
> > > diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
> > > similarity index 71%
> > > rename from Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
> > > rename to Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
> > > index 93e4fb827cd6..8dc7edb4d198 100644
> > > --- a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
> > > +++ b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
> > > @@ -1,12 +1,14 @@
> > > -* Actions S900 Clock Management Unit (CMU)
> > > +* Actions S900/S700 Clock Management Unit (CMU)
> > Same as above. Should be Actions OWL SoC's Clock Management Unit (CMU).
>
> sure
>

During the review of I2C controller driver, Andreas pointed out that
we should use Owl instead of OWL in all places and also Actions should
be replaced by Actions Semiconductor. So, please change it in relevant
places. For this binding, title should be:

Actions Semiconductor Owl SoC's Clock Management Unit (CMU).

Thanks,
Mani

> > > -The Actions S900 clock management unit generates and supplies clock to various
> > > -controllers within the SoC. The clock binding described here is applicable to
> > > -S900 SoC.
> > > +The Actions S900/S700 clock management unit generates and supplies clock to
> > > +various controllers within the SoC. The clock binding described here is
> > > +applicable to S900/S700 SoC.
> > > Required Properties:
> > > -- compatible: should be "actions,s900-cmu"
> > > +- compatible: should be one of this
> > Change to: compatible: should be one of the following:
>
> sure
>
> > Thanks,
> > Mani
> >
> > > + "actions,s900-cmu"
> > > + "actions,s700-cmu"
> > > - reg: physical base address of the controller and length of memory mapped
> > > region.
> > > - clocks: Reference to the parent clocks ("hosc", "losc")
> > > @@ -15,9 +17,9 @@ Required Properties:
> > > Each clock is assigned an identifier, and client nodes can use this identifier
> > > to specify the clock which they consume.
> > > -All available clocks are defined as preprocessor macros in
> > > -dt-bindings/clock/actions,s900-cmu.h header and can be used in device
> > > -tree sources.
> > > +All available clocks are defined as preprocessor macros in corresponding
> > > +dt-bindings/clock/actions,s900-cmu.h or s700-cmu.h header and can be used in
> > > +device tree sources.
> > > External clocks:
> > > --
> > > 2.18.0
> > >
>
> Thanks,
> Saravanan

2018-07-01 17:52:38

by saravanan sekar

[permalink] [raw]

Subject: Re: [PATCH v2 1/3] arm64: dts: actions: Enable clock controller for S700

Hi Mani,

On 06/30/18 11:42, Manivannan Sadhasivam wrote:
> On Thu, Jun 28, 2018 at 09:18:03PM +0200, Saravanan Sekar wrote:
>> Added clock management controller for S700
>>
>> Signed-off-by: Parthiban Nallathambi <[email protected]>
>> Signed-off-by: Saravanan Sekar <[email protected]>
>> ---
>> .../boot/dts/actions/s700-cubieboard7.dts | 7 -
>> arch/arm64/boot/dts/actions/s700.dtsi | 8 ++
>> include/dt-bindings/clock/actions,s700-cmu.h | 128 ++++++++++++++++++
>> 3 files changed, 136 insertions(+), 7 deletions(-)
>> create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h
>>
>> diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
>> index ef79d7905f44..28f3f4a0f7f0 100644
>> --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
>> +++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
>> @@ -28,12 +28,6 @@
>> device_type = "memory";
>> reg = <0x1 0xe0000000 0x0 0x0>;
>> };
>> -
>> - uart3_clk: uart3-clk {
>> - compatible = "fixed-clock";
>> - clock-frequency = <921600>;
>> - #clock-cells = <0>;
>> - };
> Sourcing CMU clock for UART should be in a separate patch.

sure

>> };
>>
>> &timer {
>> @@ -42,5 +36,4 @@
>>
>> &uart3 {
>> status = "okay";
>> - clocks = <&uart3_clk>;
>> };
>> diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
>> index 66dd5309f0a2..3530b705df90 100644
>> --- a/arch/arm64/boot/dts/actions/s700.dtsi
>> +++ b/arch/arm64/boot/dts/actions/s700.dtsi
>> @@ -4,6 +4,7 @@
>> */
>>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/actions,s700-cmu.h>
>>
>> / {
>> compatible = "actions,s700";
>> @@ -44,6 +45,12 @@
>> };
>> };
>>
>> + clock: clock-controller@e0168000 {
>> + compatible = "actions,s700-cmu";
>> + reg = <0 0xe0168000 0 0x1000>;
>> + #clock-cells = <1>;
>> + };
>> +
> There is no fixed rate clock like losc?

losc is 32k, I will add it

>> reserved-memory {
>> #address-cells = <2>;
>> #size-cells = <2>;
>> @@ -129,6 +136,7 @@
>> compatible = "actions,s900-uart", "actions,owl-uart";
>> reg = <0x0 0xe0126000 0x0 0x2000>;
>> interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clock CLK_UART3>;
>> status = "disabled";
>> };
>>
>> diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
>> new file mode 100644
>> index 000000000000..e5b4ea130953
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/actions,s700-cmu.h
>> @@ -0,0 +1,128 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Actions S700 clock driver
>> + *
>> + * Copyright (c) 2014 Actions Semi Inc.
>> + * Author: David Liu <[email protected]>
>> + *
>> + * Author: Pathiban Nallathambi <[email protected]>
>> + * Author: Saravanan Sekar <[email protected]>
>> + */
>> +
>> +#ifndef __DT_BINDINGS_CLOCK_S700_H
>> +#define __DT_BINDINGS_CLOCK_S700_H
>> +
>> +#define CLK_NONE 0
>> +
>> +/* fixed rate clocks */
>> +#define CLK_LOSC 1
>> +#define CLK_HOSC 2
>> +
>> +/* pll clocks */
>> +#define CLK_CORE_PLL 3
>> +#define CLK_DEV_PLL 4
>> +#define CLK_DDR_PLL 5
>> +#define CLK_NAND_PLL 6
>> +#define CLK_DISPLAY_PLL 7
>> +#define CLK_TVOUT_PLL 8
>> +#define CLK_CVBS_PLL 9
>> +#define CLK_AUDIO_PLL 10
>> +#define CLK_ETHERNET_PLL 11
>> +
> Remove extra new line please.
>
>> +
>> +/* system clock */
>> +#define CLK_SYS_BASE 12
>> +#define CLK_CPU CLK_SYS_BASE
>> +#define CLK_DEV (CLK_SYS_BASE+1)
>> +#define CLK_AHB (CLK_SYS_BASE+2)
>> +#define CLK_APB (CLK_SYS_BASE+3)
>> +#define CLK_DMAC (CLK_SYS_BASE+4)
>> +#define CLK_NOC0_CLK_MUX (CLK_SYS_BASE+5)
>> +#define CLK_NOC1_CLK_MUX (CLK_SYS_BASE+6)
>> +#define CLK_HP_CLK_MUX (CLK_SYS_BASE+7)
>> +#define CLK_HP_CLK_DIV (CLK_SYS_BASE+8)
>> +#define CLK_NOC1_CLK_DIV (CLK_SYS_BASE+9)
>> +#define CLK_NOC0 (CLK_SYS_BASE+10)
>> +#define CLK_NOC1 (CLK_SYS_BASE+11)
>> +#define CLK_SENOR_SRC (CLK_SYS_BASE+12)
>> +
>> +/* peripheral device clock */
>> +#define CLK_PERIP_BASE 25
>> +#define CLK_GPIO (CLK_PERIP_BASE)
>> +#define CLK_TIMER (CLK_PERIP_BASE+1)
>> +#define CLK_DSI (CLK_PERIP_BASE+2)
>> +#define CLK_CSI (CLK_PERIP_BASE+3)
>> +#define CLK_SI (CLK_PERIP_BASE+4)
>> +#define CLK_DE (CLK_PERIP_BASE+5)
>> +#define CLK_HDE (CLK_PERIP_BASE+6)
>> +#define CLK_VDE (CLK_PERIP_BASE+7)
>> +#define CLK_VCE (CLK_PERIP_BASE+8)
>> +#define CLK_NAND (CLK_PERIP_BASE+9)
>> +#define CLK_SD0 (CLK_PERIP_BASE+10)
>> +#define CLK_SD1 (CLK_PERIP_BASE+11)
>> +#define CLK_SD2 (CLK_PERIP_BASE+12)
>> +
>> +#define CLK_UART0 (CLK_PERIP_BASE+13)
>> +#define CLK_UART1 (CLK_PERIP_BASE+14)
>> +#define CLK_UART2 (CLK_PERIP_BASE+15)
>> +#define CLK_UART3 (CLK_PERIP_BASE+16)
>> +#define CLK_UART4 (CLK_PERIP_BASE+17)
>> +#define CLK_UART5 (CLK_PERIP_BASE+18)
>> +#define CLK_UART6 (CLK_PERIP_BASE+19)
>> +
>> +#define CLK_PWM0 (CLK_PERIP_BASE+20)
>> +#define CLK_PWM1 (CLK_PERIP_BASE+21)
>> +#define CLK_PWM2 (CLK_PERIP_BASE+22)
>> +#define CLK_PWM3 (CLK_PERIP_BASE+23)
>> +#define CLK_PWM4 (CLK_PERIP_BASE+24)
>> +#define CLK_PWM5 (CLK_PERIP_BASE+25)
>> +#define CLK_GPU3D (CLK_PERIP_BASE+26)
>> +
>> +#define CLK_I2C0 (CLK_PERIP_BASE+27)
>> +#define CLK_I2C1 (CLK_PERIP_BASE+28)
>> +#define CLK_I2C2 (CLK_PERIP_BASE+29)
>> +#define CLK_I2C3 (CLK_PERIP_BASE+30)
>> +
>> +
>> +#define CLK_SPI0 (CLK_PERIP_BASE+31)
>> +#define CLK_SPI1 (CLK_PERIP_BASE+32)
>> +#define CLK_SPI2 (CLK_PERIP_BASE+33)
>> +#define CLK_SPI3 (CLK_PERIP_BASE+34)
>> +
>> +#define CLK_USB3_480MPLL0 (CLK_PERIP_BASE+35)
>> +#define CLK_USB3_480MPHY0 (CLK_PERIP_BASE+36)
>> +#define CLK_USB3_5GPHY (CLK_PERIP_BASE+37)
>> +#define CLK_USB3_CCE (CLK_PERIP_BASE+48)
>> +#define CLK_USB3_MAC (CLK_PERIP_BASE+49)
>> +
>> +
>> +#define CLK_LCD (CLK_PERIP_BASE+50)
>> +#define CLK_HDMI_AUDIO (CLK_PERIP_BASE+51)
>> +#define CLK_I2SRX (CLK_PERIP_BASE+52)
>> +#define CLK_I2STX (CLK_PERIP_BASE+53)
>> +
>> +#define CLK_SENSOR0 (CLK_PERIP_BASE+54)
>> +#define CLK_SENSOR1 (CLK_PERIP_BASE+55)
>> +
>> +#define CLK_HDMI_DEV (CLK_PERIP_BASE+56)
>> +
>> +#define CLK_ETHERNET (CLK_PERIP_BASE+59)
>> +#define CLK_RMII_REF (CLK_PERIP_BASE+60)
>> +
>> +#define CLK_USB2H0_PLLEN (CLK_PERIP_BASE+61)
>> +#define CLK_USB2H0_PHY (CLK_PERIP_BASE+62)
>> +#define CLK_USB2H0_CCE (CLK_PERIP_BASE+63)
>> +#define CLK_USB2H1_PLLEN (CLK_PERIP_BASE+64)
>> +#define CLK_USB2H1_PHY (CLK_PERIP_BASE+65)
>> +#define CLK_USB2H1_CCE (CLK_PERIP_BASE+66)
>> +
>> +
>> +#define CLK_TVOUT (CLK_PERIP_BASE+67)
>> +
>> +#define CLK_THERMAL_SENSOR (CLK_PERIP_BASE+68)
>> +
>> +#define CLK_IRC_SWITCH (CLK_PERIP_BASE+69)
>> +#define CLK_PCM1 (CLK_PERIP_BASE+70)
>> +#define CLK_NR_CLKS (CLK_PCM1) /* update on adding new clk */
>> +
> Since the index starts from 0, CLK_NR_CLKS should be CLK_PCM1 + 1

0 is for CLK_NONE, so actual clock starts from 1

> Thanks,
> Mani
>
>> +#endif /* __DT_BINDINGS_CLOCK_S700_H */
>> --
>> 2.18.0
>>

2018-07-01 17:53:48

by saravanan sekar

[permalink] [raw]

Subject: Re: [PATCH v2 2/3] clk: actions: Add S700 SoC clock support

On 07/01/18 19:30, Manivannan Sadhasivam wrote:
> On Sun, Jul 01, 2018 at 07:23:58PM +0200, Saravanan Sekar wrote:
>>
>> On 06/30/18 11:22, Manivannan Sadhasivam wrote:
>>> Hi Saravanan,
>>>
>>> On Thu, Jun 28, 2018 at 09:18:04PM +0200, Saravanan Sekar wrote:
>>>> Add Actions Semi S700 SoC clock support
>>>>
>>>> Signed-off-by: Parthiban Nallathambi <[email protected]>
>>>> Signed-off-by: Saravanan Sekar <[email protected]>
>>>> ---
>>>> drivers/clk/actions/Kconfig | 7 +
>>>> drivers/clk/actions/Makefile | 1 +
>>>> drivers/clk/actions/owl-s700.c | 614 +++++++++++++++++++++++++++++++++
>>>> 3 files changed, 622 insertions(+)
>>>> create mode 100644 drivers/clk/actions/owl-s700.c
>>>>
>>>> diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig
>>>> index 8854adb37847..d883b48e4607 100644
>>>> --- a/drivers/clk/actions/Kconfig
>>>> +++ b/drivers/clk/actions/Kconfig
>>>> @@ -1,6 +1,7 @@
>>>> config CLK_ACTIONS
>>>> bool "Clock driver for Actions Semi SoCs"
>>>> depends on ARCH_ACTIONS || COMPILE_TEST
>>>> + select REGMAP_MMIO
>>> This change should be in a separate patch.
>> I don't see any specifc reason to split this as seperate patch, since driver
>> is bound to regmap
>>
> I'd say this is a fix to the Owl common clk code rather than an addition
> for the S700 SoC. So this should be in a separate patch.

Ok, will seperate it

Thanks, Saravanan

> Thanks,
> Mani
>
>>>> default ARCH_ACTIONS
>>>> if CLK_ACTIONS
>>>> @@ -11,4 +12,10 @@ config CLK_OWL_S900
>>>> bool "Support for the Actions Semi OWL S900 clocks"
>>>> depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
>>>> default ARM64 && ARCH_ACTIONS
>>>> +
>>>> +config CLK_OWL_S700
>>>> + bool "Support for the Actions Semi OWL S700 clocks"
>>>> + depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
>>>> + default ARM64 && ARCH_ACTIONS
>>>> +
>>> It's good to keep the symbols alphabetically sorted (ascending order)
>> Will change the order
>>
>>>> endif
>>>> diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
>>>> index 76e431434d10..a860973d940d 100644
>>>> --- a/drivers/clk/actions/Makefile
>>>> +++ b/drivers/clk/actions/Makefile
>>>> @@ -9,4 +9,5 @@ clk-owl-y += owl-composite.o
>>>> clk-owl-y += owl-pll.o
>>>> # SoC support
>>>> +obj-$(CONFIG_CLK_OWL_S900) += owl-s700.o
>>> Should be CONFIG_CLK_OWL_S700
>> I will correct it
>>
>>>> obj-$(CONFIG_CLK_OWL_S900) += owl-s900.o
>>>> diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c
>>>> new file mode 100644
>>>> index 000000000000..cc8d1f947171
>>>> --- /dev/null
>>>> +++ b/drivers/clk/actions/owl-s700.c
>>>> @@ -0,0 +1,614 @@
>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>> +/*
>>>> + * Actions S700 clock driver
>>>> + *
>>>> + * Copyright (c) 2014 Actions Semi Inc.
>>>> + * Author: David Liu <[email protected]>
>>>> + *
>>>> + * Author: Pathiban Nallathambi <[email protected]>
>>>> + * Author: Saravanan Sekar <[email protected]>
>>>> + */
>>>> +
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/platform_device.h>
>>>> +
>>>> +#include "owl-common.h"
>>>> +#include "owl-composite.h"
>>>> +#include "owl-divider.h"
>>>> +#include "owl-factor.h"
>>>> +#include "owl-fixed-factor.h"
>>>> +#include "owl-gate.h"
>>>> +#include "owl-mux.h"
>>>> +#include "owl-pll.h"
>>>> +
>>>> +#include <dt-bindings/clock/actions,s700-cmu.h>
>>>> +
>>>> +#define CMU_COREPLL (0x0000)
>>>> +#define CMU_DEVPLL (0x0004)
>>>> +#define CMU_DDRPLL (0x0008)
>>>> +#define CMU_NANDPLL (0x000C)
>>>> +#define CMU_DISPLAYPLL (0x0010)
>>>> +#define CMU_AUDIOPLL (0x0014)
>>>> +#define CMU_TVOUTPLL (0x0018)
>>>> +#define CMU_BUSCLK (0x001C)
>>>> +#define CMU_SENSORCLK (0x0020)
>>>> +#define CMU_LCDCLK (0x0024)
>>>> +#define CMU_DSIPLLCLK (0x0028)
>>>> +#define CMU_CSICLK (0x002C)
>>>> +#define CMU_DECLK (0x0030)
>>>> +#define CMU_SICLK (0x0034)
>>>> +#define CMU_BUSCLK1 (0x0038)
>>>> +#define CMU_HDECLK (0x003C)
>>>> +#define CMU_VDECLK (0x0040)
>>>> +#define CMU_VCECLK (0x0044)
>>>> +#define CMU_NANDCCLK (0x004C)
>>>> +#define CMU_SD0CLK (0x0050)
>>>> +#define CMU_SD1CLK (0x0054)
>>>> +#define CMU_SD2CLK (0x0058)
>>>> +#define CMU_UART0CLK (0x005C)
>>>> +#define CMU_UART1CLK (0x0060)
>>>> +#define CMU_UART2CLK (0x0064)
>>>> +#define CMU_UART3CLK (0x0068)
>>>> +#define CMU_UART4CLK (0x006C)
>>>> +#define CMU_UART5CLK (0x0070)
>>>> +#define CMU_UART6CLK (0x0074)
>>>> +#define CMU_PWM0CLK (0x0078)
>>>> +#define CMU_PWM1CLK (0x007C)
>>>> +#define CMU_PWM2CLK (0x0080)
>>>> +#define CMU_PWM3CLK (0x0084)
>>>> +#define CMU_PWM4CLK (0x0088)
>>>> +#define CMU_PWM5CLK (0x008C)
>>>> +#define CMU_GPU3DCLK (0x0090)
>>>> +#define CMU_CORECTL (0x009C)
>>>> +#define CMU_DEVCLKEN0 (0x00A0)
>>>> +#define CMU_DEVCLKEN1 (0x00A4)
>>>> +#define CMU_DEVRST0 (0x00A8)
>>>> +#define CMU_DEVRST1 (0x00AC)
>>>> +#define CMU_USBPLL (0x00B0)
>>>> +#define CMU_ETHERNETPLL (0x00B4)
>>>> +#define CMU_CVBSPLL (0x00B8)
>>>> +#define CMU_SSTSCLK (0x00C0)
>>>> +
>>>> +static struct clk_pll_table clk_audio_pll_table[] = {
>>>> + {0, 45158400}, {1, 49152000},
>>>> + {0, 0},
>>>> +};
>>>> +
>>>> +static struct clk_pll_table clk_cvbs_pll_table[] = {
>>>> + {27, 29*12000000}, {28, 30*12000000}, {29, 31*12000000},
>>> Please leave a space around *
>> will change it
>>
>>>> + {30, 32*12000000}, {31, 33*12000000}, {32, 34*12000000},
>>>> + {33, 35*12000000}, {34, 36*12000000}, {35, 37*12000000},
>>>> + {36, 38*12000000}, {37, 39*12000000}, {38, 40*12000000},
>>>> + {39, 41*12000000}, {40, 42*12000000}, {41, 43*12000000},
>>>> + {42, 44*12000000}, {43, 45*12000000}, {0, 0},
>>>> +};
>>>> +
>>>> +/* pll clocks */
>>>> +static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED);
>>>> +static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED);
>>>> +static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED);
>>>> +static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED);
>>>> +static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED);
>>>> +static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED);
>>>> +static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
>>>> +static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
>>>> +
>>>> +
>>> Remove extra new line
>> will remove
>>
>>>> +static const char *cpu_clk_mux_p[] = {"losc", "hosc", "core_pll", "noc1_clk_div"};
>>>> +static const char *dev_clk_p[] = { "hosc", "dev_pll"};
>>>> +static const char *noc_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"};
>>>> +
>>>> +static const char *csi_clk_mux_p[] = { "display_pll", "dev_clk"};
>>>> +static const char *de_clk_mux_p[] = { "display_pll", "dev_clk"};
>>>> +static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"};
>>>> +static const char *nand_clk_mux_p[] = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"};
>>>> +static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll", };
>>>> +static const char *uart_clk_mux_p[] = { "hosc", "dev_pll"};
>>>> +static const char *pwm_clk_mux_p[] = { "losc", "hosc"};
>>>> +static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"};
>>>> +static const char *lcd_clk_mux_p[] = { "display_pll", "dev_clk" };
>>>> +static const char *i2s_clk_mux_p[] = { "audio_pll" };
>>>> +static const char *sensor_clk_mux_p[] = { "hosc", "si"};
>>>> +
>>>> +
>>> Remove extra new line
>> will remove
>>
>>>> +/* mux clocks */
>>>> +static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
>>>> +static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
>>>> +static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT);
>>> Keep the spacing consistent.
>> will remove extra space
>>
>>>> +static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT);
>>> ditto
>>>
>>>> +static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
>>>> +
>>>> +static struct clk_factor_table sd_factor_table[] = {
>>>> + /* bit0 ~ 4 */
>>>> + {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
>>>> + {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
>>>> + {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
>>>> + {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16},
>>>> + {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20},
>>>> + {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24},
>>>> + {24, 1, 25}, {25, 1, 26},
>>>> +
>>>> + /* bit8: /128 */
>>>> + {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128},
>>>> + {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128},
>>>> + {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128},
>>>> + {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128},
>>>> + {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128},
>>>> + {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
>>>> + {280, 1, 25 * 128}, {281, 1, 26 * 128},
>>>> +
>>>> + {0, 0},
>>>> +};
>>>> +
>>>> +static struct clk_factor_table lcd_factor_table[] = {
>>>> + /* bit0 ~ 3 */
>>>> + {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
>>>> + {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
>>>> + {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
>>>> +
>>>> + /* bit8: /7 */
>>>> + {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
>>>> + {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
>>>> + {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
>>>> + {0, 0},
>>>> +};
>>>> +
>>>> +
>>> Remove extra new line
>> sure
>>
>>>> +static struct clk_div_table hdmia_div_table[] = {
>>>> + {0, 1}, {1, 2}, {2, 3}, {3, 4},
>>>> + {4, 6}, {5, 8}, {6, 12}, {7, 16},
>>>> + {8, 24},
>>>> + {0, 0},
>>>> +};
>>>> +
>>>> +static struct clk_div_table rmii_div_table[] = {
>>>> + {0, 4}, {1, 10},
>>>> +};
>>>> +
>>>> +
>>> Remove extra new line
>> sure
>>
>>
>>>> +/* divider clocks */
>>>> +static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0);
>>>> +static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0);
>>>> +static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0);
>>>> +static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
>>>> +static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
>>>> +static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
>>>> +static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0);
>>>> +static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0);
>>>> +static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0);
>>>> +
>>>> +static struct clk_factor_table de_factor_table[] = {
>>>> + {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
>>>> + {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
>>>> + {8, 1, 12}, {0, 0, 0},
>>>> +};
>>>> +
>>>> +static struct clk_factor_table hde_factor_table[] = {
>>>> + {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
>>>> + {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
>>>> + {0, 0, 0},
>>>> +};
>>>> +
>>>> +/* gate clocks */
>>>> +static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0);
>>>> +static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0);
>>>> +static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
>>> Timer clk enable bit should be 22 according to the datasheet I have.
>> Thanks for pointing out, I have refered datasheet and will correct it
>>
>>>> +static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0);
>>>> +static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0);
>>>> +static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0);
>>>> +static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0);
>>>> +static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
>>>> +static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0);
>>>> +static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0);
>>>> +static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0);
>>>> +static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0);
>>>> +static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0);
>>>> +
>>>> +/* composite clocks */
>>>> +
>>>> +static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_CSICLK, 4, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
>>>> + OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_SICLK, 4, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
>>>> + OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_DECLK, 12, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
>>>> + OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_HDECLK, 4, 2),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
>>>> + OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_VDECLK, 4, 2),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
>>>> + OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_VCECLK, 4, 2),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
>>>> + OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
>>>> + OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
>>>> + CLK_SET_RATE_PARENT);
>>>> +
>>>> +static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_SD0CLK, 9, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
>>>> + OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_SD1CLK, 9, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
>>>> + OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_SD2CLK, 9, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0),
>>>> + OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
>>>> +#ifdef CONFIG_MMC_OWL_CLK_NANDPLL
>>> From where this define comes from?
>> Will add this options in the kconfig
>>
>>
>>>> + CLK_SET_RATE_PARENT);
>>>> +#else
>>>> + 0);
>>>> +#endif
>>>> +
>>>> +static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_UART0CLK, 16, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
>>>> + OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_UART1CLK, 16, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0),
>>>> + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_UART2CLK, 16, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0),
>>>> + OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_UART3CLK, 16, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0),
>>>> + OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_UART4CLK, 16, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0),
>>>> + OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_UART5CLK, 16, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0),
>>>> + OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_UART6CLK, 16, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
>>>> + OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0),
>>>> + OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
>>>> + CLK_IGNORE_UNUSED);
>>>> +
>>>> +static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
>>>> + OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
>>>> + OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
>>>> + OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
>>>> + OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
>>>> + OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p,
>>> Please keep spacing consistent
>>>
>>>> + OWL_MUX_HW(CMU_GPU3DCLK, 4, 3),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
>>>> + OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p,
>>> ditto
>>>
>>>> + OWL_MUX_HW(CMU_LCDCLK, 12, 2),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0),
>>>> + OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),/*CMU_AUDIOPLL 24,1 unused*/
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0),
>>>> + OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0),
>>>> + OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p,
>>>> + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
>>>> + OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
>>>> + 0);
>>>> +
>>>> +/* for bluetooth pcm communication */
>>>> +static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll",
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
>>>> + 1, 2, 0);
>>>> +
>>>> +static OWL_COMP_DIV(clk_senor_src, "sensor_src", sensor_clk_mux_p,
>>> Should be clk_sensor_src.
>> Will correct the typo
>>
>>> Thanks,
>>> Mani
>>>
>>>> + OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
>>>> + {0},
>>>> + OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
>>>> + 0);
>>>> +
>>>> +static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll",
>>>> + OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
>>>> + 1, 20, 0);
>>>> +
>>>> +static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc",
>>>> + OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0),
>>>> + OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),
>>>> + 0);
>>>> +
>>>> +static struct owl_clk_common *s700_clks[] = {
>>>> + &clk_core_pll.common,
>>>> + &clk_dev_pll.common,
>>>> + &clk_ddr_pll.common,
>>>> + &clk_nand_pll.common,
>>>> + &clk_display_pll.common,
>>>> + &clk_cvbs_pll .common,
>>>> + &clk_audio_pll.common,
>>>> + &clk_ethernet_pll.common,
>>>> + &clk_cpu.common,
>>>> + &clk_dev.common,
>>>> + &clk_ahb.common,
>>>> + &clk_apb.common,
>>>> + &clk_dmac.common,
>>>> + &clk_noc0_clk_mux.common,
>>>> + &clk_noc1_clk_mux.common,
>>>> + &clk_hp_clk_mux.common,
>>>> + &clk_hp_clk_div.common,
>>>> + &clk_noc1_clk_div.common,
>>>> + &clk_noc0.common,
>>>> + &clk_noc1.common,
>>>> + &clk_senor_src.common,
>>>> + &clk_gpio.common,
>>>> + &clk_timer.common,
>>>> + &clk_dsi.common,
>>>> + &clk_csi.common,
>>>> + &clk_si.common,
>>>> + &clk_de.common,
>>>> + &clk_hde.common,
>>>> + &clk_vde.common,
>>>> + &clk_vce.common,
>>>> + &clk_nand.common,
>>>> + &clk_sd0.common,
>>>> + &clk_sd1.common,
>>>> + &clk_sd2.common,
>>>> + &clk_uart0.common,
>>>> + &clk_uart1.common,
>>>> + &clk_uart2.common,
>>>> + &clk_uart3.common,
>>>> + &clk_uart4.common,
>>>> + &clk_uart5.common,
>>>> + &clk_uart6.common,
>>>> + &clk_pwm0.common,
>>>> + &clk_pwm1.common,
>>>> + &clk_pwm2.common,
>>>> + &clk_pwm3.common,
>>>> + &clk_pwm4.common,
>>>> + &clk_pwm5.common,
>>>> + &clk_gpu3d.common,
>>>> + &clk_i2c0.common,
>>>> + &clk_i2c1.common,
>>>> + &clk_i2c2.common,
>>>> + &clk_i2c3.common,
>>>> + &clk_spi0.common,
>>>> + &clk_spi1.common,
>>>> + &clk_spi2.common,
>>>> + &clk_spi3.common,
>>>> + &clk_usb3_480mpll0.common,
>>>> + &clk_usb3_480mphy0.common,
>>>> + &clk_usb3_5gphy.common,
>>>> + &clk_usb3_cce.common,
>>>> + &clk_lcd.common,
>>>> + &clk_hdmi_audio.common,
>>>> + &clk_i2srx.common,
>>>> + &clk_i2stx.common,
>>>> + &clk_sensor0.common,
>>>> + &clk_sensor1.common,
>>>> + &clk_hdmi_dev.common,
>>>> + &clk_ethernet.common,
>>>> + &clk_rmii_ref.common,
>>>> + &clk_usb2h0_pllen.common,
>>>> + &clk_usb2h0_phy.common,
>>>> + &clk_usb2h0_cce.common,
>>>> + &clk_usb2h1_pllen.common,
>>>> + &clk_usb2h1_phy.common,
>>>> + &clk_usb2h1_cce.common,
>>>> + &clk_tvout.common,
>>>> + &clk_thermal_sensor.common,
>>>> + &clk_irc_switch.common,
>>>> + &clk_pcm1.common,
>>>> +};
>>>> +
>>>> +static struct clk_hw_onecell_data s700_hw_clks = {
>>>> + .hws = {
>>>> + [CLK_CORE_PLL] = &clk_core_pll.common.hw,
>>>> + [CLK_DEV_PLL] = &clk_dev_pll.common.hw,
>>>> + [CLK_DDR_PLL] = &clk_ddr_pll.common.hw,
>>>> + [CLK_NAND_PLL] = &clk_nand_pll.common.hw,
>>>> + [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw,
>>>> + [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw,
>>>> + [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw,
>>>> + [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw,
>>>> + [CLK_CPU] = &clk_cpu.common.hw,
>>>> + [CLK_DEV] = &clk_dev.common.hw,
>>>> + [CLK_AHB] = &clk_ahb.common.hw,
>>>> + [CLK_APB] = &clk_apb.common.hw,
>>>> + [CLK_DMAC] = &clk_dmac.common.hw,
>>>> + [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw,
>>>> + [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw,
>>>> + [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw,
>>>> + [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw,
>>>> + [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw,
>>>> + [CLK_NOC0] = &clk_noc0.common.hw,
>>>> + [CLK_NOC1] = &clk_noc1.common.hw,
>>>> + [CLK_SENOR_SRC] = &clk_senor_src.common.hw,
>>>> + [CLK_GPIO] = &clk_gpio.common.hw,
>>>> + [CLK_TIMER] = &clk_timer.common.hw,
>>>> + [CLK_DSI] = &clk_dsi.common.hw,
>>>> + [CLK_CSI] = &clk_csi.common.hw,
>>>> + [CLK_SI] = &clk_si.common.hw,
>>>> + [CLK_DE] = &clk_de.common.hw,
>>>> + [CLK_HDE] = &clk_hde.common.hw,
>>>> + [CLK_VDE] = &clk_vde.common.hw,
>>>> + [CLK_VCE] = &clk_vce.common.hw,
>>>> + [CLK_NAND] = &clk_nand.common.hw,
>>>> + [CLK_SD0] = &clk_sd0.common.hw,
>>>> + [CLK_SD1] = &clk_sd1.common.hw,
>>>> + [CLK_SD2] = &clk_sd2.common.hw,
>>>> + [CLK_UART0] = &clk_uart0.common.hw,
>>>> + [CLK_UART1] = &clk_uart1.common.hw,
>>>> + [CLK_UART2] = &clk_uart2.common.hw,
>>>> + [CLK_UART3] = &clk_uart3.common.hw,
>>>> + [CLK_UART4] = &clk_uart4.common.hw,
>>>> + [CLK_UART5] = &clk_uart5.common.hw,
>>>> + [CLK_UART6] = &clk_uart6.common.hw,
>>>> + [CLK_PWM0] = &clk_pwm0.common.hw,
>>>> + [CLK_PWM1] = &clk_pwm1.common.hw,
>>>> + [CLK_PWM2] = &clk_pwm2.common.hw,
>>>> + [CLK_PWM3] = &clk_pwm3.common.hw,
>>>> + [CLK_PWM4] = &clk_pwm4.common.hw,
>>>> + [CLK_PWM5] = &clk_pwm5.common.hw,
>>>> + [CLK_GPU3D] = &clk_gpu3d.common.hw,
>>>> + [CLK_I2C0] = &clk_i2c0.common.hw,
>>>> + [CLK_I2C1] = &clk_i2c1.common.hw,
>>>> + [CLK_I2C2] = &clk_i2c2.common.hw,
>>>> + [CLK_I2C3] = &clk_i2c3.common.hw,
>>>> + [CLK_SPI0] = &clk_spi0.common.hw,
>>>> + [CLK_SPI1] = &clk_spi1.common.hw,
>>>> + [CLK_SPI2] = &clk_spi2.common.hw,
>>>> + [CLK_SPI3] = &clk_spi3.common.hw,
>>>> + [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw,
>>>> + [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw,
>>>> + [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw,
>>>> + [CLK_USB3_CCE] = &clk_usb3_cce.common.hw,
>>>> + [CLK_LCD] = &clk_lcd.common.hw,
>>>> + [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw,
>>>> + [CLK_I2SRX] = &clk_i2srx.common.hw,
>>>> + [CLK_I2STX] = &clk_i2stx.common.hw,
>>>> + [CLK_SENSOR0] = &clk_sensor0.common.hw,
>>>> + [CLK_SENSOR1] = &clk_sensor1.common.hw,
>>>> + [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw,
>>>> + [CLK_ETHERNET] = &clk_ethernet.common.hw,
>>>> + [CLK_RMII_REF] = &clk_rmii_ref.common.hw,
>>>> + [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw,
>>>> + [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw,
>>>> + [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw,
>>>> + [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw,
>>>> + [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw,
>>>> + [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw,
>>>> + [CLK_TVOUT] = &clk_tvout.common.hw,
>>>> + [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw,
>>>> + [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw,
>>>> + [CLK_PCM1] = &clk_pcm1.common.hw,
>>>> + },
>>>> + .num = CLK_NR_CLKS,
>>>> +};
>>>> +
>>>> +static const struct owl_clk_desc s700_clk_desc = {
>>>> + .clks = s700_clks,
>>>> + .num_clks = ARRAY_SIZE(s700_clks),
>>>> +
>>>> + .hw_clks = &s700_hw_clks,
>>>> +};
>>>> +
>>>> +static int s700_clk_probe(struct platform_device *pdev)
>>>> +{
>>>> + const struct owl_clk_desc *desc;
>>>> +
>>>> + desc = &s700_clk_desc;
>>>> + owl_clk_regmap_init(pdev, desc);
>>>> +
>>>> + return owl_clk_probe(&pdev->dev, desc->hw_clks);
>>>> +}
>>>> +
>>>> +static const struct of_device_id s700_clk_of_match[] = {
>>>> + { .compatible = "actions,s700-cmu", },
>>>> + { /* sentinel */ }
>>>> +};
>>>> +
>>>> +static struct platform_driver s700_clk_driver = {
>>>> + .probe = s700_clk_probe,
>>>> + .driver = {
>>>> + .name = "s700-cmu",
>>>> + .of_match_table = s700_clk_of_match
>>>> + },
>>>> +};
>>>> +
>>>> +static int __init s700_clk_init(void)
>>>> +{
>>>> + return platform_driver_register(&s700_clk_driver);
>>>> +}
>>>> +core_initcall(s700_clk_init);
>>>> --
>>>> 2.18.0
>>>>

2018-07-01 17:55:55

by saravanan sekar

[permalink] [raw]

Subject: Re: [PATCH v2 3/3] dt-bindings: clock: Modify Actions Soc clock bindings

Hi Mani,

On 07/01/18 19:37, Manivannan Sadhasivam wrote:
> On Sun, Jul 01, 2018 at 07:26:20PM +0200, Saravanan Sekar wrote:
>> Hi Mani
>>
>>
>> On 06/30/18 11:32, Manivannan Sadhasivam wrote:
>>> Hi Saravanan,
>>>
>>> I agree with modifying the existing binding to accomodate other
>>> SoC's of the same family. But the binding should be
>>> "actions,owl-cmu.txt" since it reflects the family name.
>> Agree, will modify the name
>>
>>> Andreas, what do you think?
>>>
>>> On Thu, Jun 28, 2018 at 09:18:05PM +0200, Saravanan Sekar wrote:
>>>> Modify clock bindings common Actions Semi Soc family S700/S900.
>>>>
>>>> Signed-off-by: Parthiban Nallathambi <[email protected]>
>>>> Signed-off-by: Saravanan Sekar <[email protected]>
>>>> ---
>>>> ...tions,s900-cmu.txt => actions,sx00-cmu.txt} | 18 ++++++++++--------
>>>> 1 file changed, 10 insertions(+), 8 deletions(-)
>>>> rename Documentation/devicetree/bindings/clock/{actions,s900-cmu.txt => actions,sx00-cmu.txt} (71%)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
>>>> similarity index 71%
>>>> rename from Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
>>>> rename to Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
>>>> index 93e4fb827cd6..8dc7edb4d198 100644
>>>> --- a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
>>>> +++ b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
>>>> @@ -1,12 +1,14 @@
>>>> -* Actions S900 Clock Management Unit (CMU)
>>>> +* Actions S900/S700 Clock Management Unit (CMU)
>>> Same as above. Should be Actions OWL SoC's Clock Management Unit (CMU).
>> sure
>>
> During the review of I2C controller driver, Andreas pointed out that
> we should use Owl instead of OWL in all places and also Actions should
> be replaced by Actions Semiconductor. So, please change it in relevant
> places. For this binding, title should be:
>
> Actions Semiconductor Owl SoC's Clock Management Unit (CMU).

Ok will change as mentioned above.

> Thanks,
> Mani
>
>>>> -The Actions S900 clock management unit generates and supplies clock to various
>>>> -controllers within the SoC. The clock binding described here is applicable to
>>>> -S900 SoC.
>>>> +The Actions S900/S700 clock management unit generates and supplies clock to
>>>> +various controllers within the SoC. The clock binding described here is
>>>> +applicable to S900/S700 SoC.
>>>> Required Properties:
>>>> -- compatible: should be "actions,s900-cmu"
>>>> +- compatible: should be one of this
>>> Change to: compatible: should be one of the following:
>> sure
>>
>>> Thanks,
>>> Mani
>>>
>>>> + "actions,s900-cmu"
>>>> + "actions,s700-cmu"
>>>> - reg: physical base address of the controller and length of memory mapped
>>>> region.
>>>> - clocks: Reference to the parent clocks ("hosc", "losc")
>>>> @@ -15,9 +17,9 @@ Required Properties:
>>>> Each clock is assigned an identifier, and client nodes can use this identifier
>>>> to specify the clock which they consume.
>>>> -All available clocks are defined as preprocessor macros in
>>>> -dt-bindings/clock/actions,s900-cmu.h header and can be used in device
>>>> -tree sources.
>>>> +All available clocks are defined as preprocessor macros in corresponding
>>>> +dt-bindings/clock/actions,s900-cmu.h or s700-cmu.h header and can be used in
>>>> +device tree sources.
>>>> External clocks:
>>>> --
>>>> 2.18.0
>>>>
>> Thanks,
>> Saravanan

2018-07-01 17:59:15

by Andreas Färber

[permalink] [raw]

Subject: Re: [PATCH v2 3/3] dt-bindings: clock: Modify Actions Soc clock bindings

Hi,

Am 01.07.2018 um 19:37 schrieb Manivannan Sadhasivam:
> On Sun, Jul 01, 2018 at 07:26:20PM +0200, Saravanan Sekar wrote:
>> Hi Mani
>>
>>
>> On 06/30/18 11:32, Manivannan Sadhasivam wrote:
>>> Hi Saravanan,
>>>
>>> I agree with modifying the existing binding to accomodate other
>>> SoC's of the same family. But the binding should be
>>> "actions,owl-cmu.txt" since it reflects the family name.
>>
>> Agree, will modify the name
>>
>>> Andreas, what do you think?

I concur that sx00 is insufficient. Older models were called ATMxxxx.
Unfortunately with owl- it then no longer matches the compatible, but I
wouldn't mind.

>>> On Thu, Jun 28, 2018 at 09:18:05PM +0200, Saravanan Sekar wrote:
>>>> Modify clock bindings common Actions Semi Soc family S700/S900.
>>>>
>>>> Signed-off-by: Parthiban Nallathambi <[email protected]>
>>>> Signed-off-by: Saravanan Sekar <[email protected]>
>>>> ---
>>>> ...tions,s900-cmu.txt => actions,sx00-cmu.txt} | 18 ++++++++++--------
>>>> 1 file changed, 10 insertions(+), 8 deletions(-)
>>>> rename Documentation/devicetree/bindings/clock/{actions,s900-cmu.txt => actions,sx00-cmu.txt} (71%)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
>>>> similarity index 71%
>>>> rename from Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
>>>> rename to Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
>>>> index 93e4fb827cd6..8dc7edb4d198 100644
>>>> --- a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
>>>> +++ b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
>>>> @@ -1,12 +1,14 @@
>>>> -* Actions S900 Clock Management Unit (CMU)
>>>> +* Actions S900/S700 Clock Management Unit (CMU)
>>> Same as above. Should be Actions OWL SoC's Clock Management Unit (CMU).
>>
>> sure
>>
>
> During the review of I2C controller driver, Andreas pointed out that
> we should use Owl instead of OWL in all places and also Actions should
> be replaced by Actions Semiconductor.

Actually I was just asking to include the company name and not just say
Owl. Whether it's Actions, Actions Semi or Actions Semiconductor is not
that important to me - that would be for the Actions Semi colleagues to
comment - which I see are not in CC... Please fix that! You don't need
mp-cs I think, but the others please.

> So, please change it in relevant
> places. For this binding, title should be:
>
> Actions Semiconductor Owl SoC's Clock Management Unit (CMU).

"SoC's" looks weird there, do we have such precedence to add it?
"Actions Owl Clock Management Unit (CMU)" might do?

Saravanan, please compare other patch titles and adapt your subjects
accordingly: "modify bindings" is not very meaningful, since a patch
always modifies something and the prefix already indicates dt-bindings
as target. "Soc" is misspelled. The time-saving information to put there
would be addition of S700.

>>>> -The Actions S900 clock management unit generates and supplies clock to various
>>>> -controllers within the SoC. The clock binding described here is applicable to
>>>> -S900 SoC.
>>>> +The Actions S900/S700 clock management unit generates and supplies clock to
>>>> +various controllers within the SoC. The clock binding described here is
>>>> +applicable to S900/S700 SoC.

"S900 and S700 SoCs"? (keep the slash above)

>>>> Required Properties:
>>>> -- compatible: should be "actions,s900-cmu"
>>>> +- compatible: should be one of this
>>> Change to: compatible: should be one of the following:
>>
>> sure
>>
>>> Thanks,
>>> Mani
>>>
>>>> + "actions,s900-cmu"
>>>> + "actions,s700-cmu"

Mani, should we order alphabetically? I.e., will S500 go before S900, or
will people just always append at the end now? Not saying we have to,
but keeping it consistent across Actions bindings would be desirable.

>>>> - reg: physical base address of the controller and length of memory mapped
>>>> region.
>>>> - clocks: Reference to the parent clocks ("hosc", "losc")
>>>> @@ -15,9 +17,9 @@ Required Properties:
>>>> Each clock is assigned an identifier, and client nodes can use this identifier
>>>> to specify the clock which they consume.
>>>> -All available clocks are defined as preprocessor macros in
>>>> -dt-bindings/clock/actions,s900-cmu.h header and can be used in device
>>>> -tree sources.
>>>> +All available clocks are defined as preprocessor macros in corresponding
>>>> +dt-bindings/clock/actions,s900-cmu.h or s700-cmu.h header and can be used in

actions,s700-cmu.h for humans please or at least ...,s700-cmu.h.

>>>> +device tree sources.
>>>> External clocks:

Thanks,
Andreas

--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

2018-07-01 18:08:09

by Andreas Färber

[permalink] [raw]

Subject: Re: [PATCH v2 0/3] Add clock driver for Actions S700 SoC

Hi Saravannan,

Am 28.06.2018 um 21:18 schrieb Saravanan Sekar:
> Changelog v2:
> Fixed 0 day compilation warning
> Modified existing dts Actions S900 clock bindings common to Actions
> Soc family

Please post v3 without --in-reply-to. It's becoming messy to read.

> This patchset adds clock support for Actions Semi OWL series S700 SoC
> with relevant clock bindings and device tree info.
>
> Changed the UART clock using CMU instance and changes are tested in
> cubieboard7

Did you find any better way of testing than my "reboot bootloader" from
preinstalled Android?

In addition to missing Actions Semi you may want to CC Cubietech.

Thanks,
Andreas

--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

2018-07-01 18:27:16

by Parthiban Nallathambi

[permalink] [raw]

Subject: Re: [PATCH v2 0/3] Add clock driver for Actions S700 SoC

Hello Andreas,

On 07/01/2018 08:05 PM, Andreas Färber wrote:
> Hi Saravannan,
>
> Am 28.06.2018 um 21:18 schrieb Saravanan Sekar:
>> Changelog v2:
>> Fixed 0 day compilation warning
>> Modified existing dts Actions S900 clock bindings common to Actions
>> Soc family
>
> Please post v3 without --in-reply-to. It's becoming messy to read.
>
>> This patchset adds clock support for Actions Semi OWL series S700 SoC
>> with relevant clock bindings and device tree info.
>>
>> Changed the UART clock using CMU instance and changes are tested in
>> cubieboard7
>
> Did you find any better way of testing than my "reboot bootloader" from
> preinstalled Android?

Flashing bootloader.bin and u-boot-dtb.img at below offset trigger the
automatic boot from SD. But ADFU needs to long pressed before connecting
the power.

sudo dd if=bootloader.bin of=/dev/sdX bs=512 seek=4097
sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1024 seek=3072

With this is place, u-boot expects GPT layout by default. I am able to boot
the kernel from FAT/ext by updating the bootcmd/u-boot env accordingly.

I haven't tried flashing/replacing u-boot in eMMC still.

>
> In addition to missing Actions Semi you may want to CC Cubietech.

+Added cubitech linux group.

>
> Thanks,
> Andreas
>

--
Thanks,
Parthiban N

2018-07-02 02:46:24

by Manivannan Sadhasivam

[permalink] [raw]

Subject: Re: [PATCH v2 3/3] dt-bindings: clock: Modify Actions Soc clock bindings

Hi Andreas,

On Sun, Jul 01, 2018 at 07:58:15PM +0200, Andreas F?rber wrote:
> Hi,
>
> Am 01.07.2018 um 19:37 schrieb Manivannan Sadhasivam:
> > On Sun, Jul 01, 2018 at 07:26:20PM +0200, Saravanan Sekar wrote:
> >> Hi Mani
> >>
> >>
> >> On 06/30/18 11:32, Manivannan Sadhasivam wrote:
> >>> Hi Saravanan,
> >>>
> >>> I agree with modifying the existing binding to accomodate other
> >>> SoC's of the same family. But the binding should be
> >>> "actions,owl-cmu.txt" since it reflects the family name.
> >>
> >> Agree, will modify the name
> >>
> >>> Andreas, what do you think?
>
> I concur that sx00 is insufficient. Older models were called ATMxxxx.
> Unfortunately with owl- it then no longer matches the compatible, but I
> wouldn't mind.
>
> >>> On Thu, Jun 28, 2018 at 09:18:05PM +0200, Saravanan Sekar wrote:
> >>>> Modify clock bindings common Actions Semi Soc family S700/S900.
> >>>>
> >>>> Signed-off-by: Parthiban Nallathambi <[email protected]>
> >>>> Signed-off-by: Saravanan Sekar <[email protected]>
> >>>> ---
> >>>> ...tions,s900-cmu.txt => actions,sx00-cmu.txt} | 18 ++++++++++--------
> >>>> 1 file changed, 10 insertions(+), 8 deletions(-)
> >>>> rename Documentation/devicetree/bindings/clock/{actions,s900-cmu.txt => actions,sx00-cmu.txt} (71%)
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
> >>>> similarity index 71%
> >>>> rename from Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
> >>>> rename to Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
> >>>> index 93e4fb827cd6..8dc7edb4d198 100644
> >>>> --- a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
> >>>> +++ b/Documentation/devicetree/bindings/clock/actions,sx00-cmu.txt
> >>>> @@ -1,12 +1,14 @@
> >>>> -* Actions S900 Clock Management Unit (CMU)
> >>>> +* Actions S900/S700 Clock Management Unit (CMU)
> >>> Same as above. Should be Actions OWL SoC's Clock Management Unit (CMU).
> >>
> >> sure
> >>
> >
> > During the review of I2C controller driver, Andreas pointed out that
> > we should use Owl instead of OWL in all places and also Actions should
> > be replaced by Actions Semiconductor.
>
> Actually I was just asking to include the company name and not just say
> Owl. Whether it's Actions, Actions Semi or Actions Semiconductor is not
> that important to me - that would be for the Actions Semi colleagues to
> comment - which I see are not in CC... Please fix that! You don't need
> mp-cs I think, but the others please.
>

Okay, cool.

> > So, please change it in relevant
> > places. For this binding, title should be:
> >
> > Actions Semiconductor Owl SoC's Clock Management Unit (CMU).
>
> "SoC's" looks weird there, do we have such precedence to add it?
> "Actions Owl Clock Management Unit (CMU)" might do?
>

Let's keep 'Actions Semi' everywhere unless Actions Semi people say
differently.

> Saravanan, please compare other patch titles and adapt your subjects
> accordingly: "modify bindings" is not very meaningful, since a patch
> always modifies something and the prefix already indicates dt-bindings
> as target. "Soc" is misspelled. The time-saving information to put there
> would be addition of S700.
>
> >>>> -The Actions S900 clock management unit generates and supplies clock to various
> >>>> -controllers within the SoC. The clock binding described here is applicable to
> >>>> -S900 SoC.
> >>>> +The Actions S900/S700 clock management unit generates and supplies clock to
> >>>> +various controllers within the SoC. The clock binding described here is
> >>>> +applicable to S900/S700 SoC.
>
> "S900 and S700 SoCs"? (keep the slash above)
>

Agree.

> >>>> Required Properties:
> >>>> -- compatible: should be "actions,s900-cmu"
> >>>> +- compatible: should be one of this
> >>> Change to: compatible: should be one of the following:
> >>
> >> sure
> >>
> >>> Thanks,
> >>> Mani
> >>>
> >>>> + "actions,s900-cmu"
> >>>> + "actions,s700-cmu"
>
> Mani, should we order alphabetically? I.e., will S500 go before S900, or
> will people just always append at the end now? Not saying we have to,
> but keeping it consistent across Actions bindings would be desirable.
>

Yes, we should order alphabetically IMO. That way it looks good!

> >>>> - reg: physical base address of the controller and length of memory mapped
> >>>> region.
> >>>> - clocks: Reference to the parent clocks ("hosc", "losc")
> >>>> @@ -15,9 +17,9 @@ Required Properties:
> >>>> Each clock is assigned an identifier, and client nodes can use this identifier
> >>>> to specify the clock which they consume.
> >>>> -All available clocks are defined as preprocessor macros in
> >>>> -dt-bindings/clock/actions,s900-cmu.h header and can be used in device
> >>>> -tree sources.
> >>>> +All available clocks are defined as preprocessor macros in corresponding
> >>>> +dt-bindings/clock/actions,s900-cmu.h or s700-cmu.h header and can be used in
>
> actions,s700-cmu.h for humans please or at least ...,s700-cmu.h.
>

actions,s700-cmu.h looks good to me.

Thanks,
Mani

> >>>> +device tree sources.
> >>>> External clocks:
>
> Thanks,
> Andreas
>
> --
> SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
> GF: Felix Imend?rffer, Jane Smithard, Graham Norton
> HRB 21284 (AG N?rnberg)

2018-07-02 02:52:58

by Manivannan Sadhasivam

[permalink] [raw]

Subject: Re: [PATCH v2 1/3] arm64: dts: actions: Enable clock controller for S700

Hi,

On Sun, Jul 01, 2018 at 07:50:01PM +0200, Saravanan Sekar wrote:
> Hi Mani,
>
>
> On 06/30/18 11:42, Manivannan Sadhasivam wrote:
> > On Thu, Jun 28, 2018 at 09:18:03PM +0200, Saravanan Sekar wrote:
> > > Added clock management controller for S700
> > >
> > > Signed-off-by: Parthiban Nallathambi <[email protected]>
> > > Signed-off-by: Saravanan Sekar <[email protected]>
> > > ---
> > > .../boot/dts/actions/s700-cubieboard7.dts | 7 -
> > > arch/arm64/boot/dts/actions/s700.dtsi | 8 ++
> > > include/dt-bindings/clock/actions,s700-cmu.h | 128 ++++++++++++++++++
> > > 3 files changed, 136 insertions(+), 7 deletions(-)
> > > create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h
> > >
> > > diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
> > > index ef79d7905f44..28f3f4a0f7f0 100644
> > > --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
> > > +++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
> > > @@ -28,12 +28,6 @@
> > > device_type = "memory";
> > > reg = <0x1 0xe0000000 0x0 0x0>;
> > > };
> > > -
> > > - uart3_clk: uart3-clk {
> > > - compatible = "fixed-clock";
> > > - clock-frequency = <921600>;
> > > - #clock-cells = <0>;
> > > - };
> > Sourcing CMU clock for UART should be in a separate patch.
>
> sure
>
> > > };
> > > &timer {
> > > @@ -42,5 +36,4 @@
> > > &uart3 {
> > > status = "okay";
> > > - clocks = <&uart3_clk>;
> > > };
> > > diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
> > > index 66dd5309f0a2..3530b705df90 100644
> > > --- a/arch/arm64/boot/dts/actions/s700.dtsi
> > > +++ b/arch/arm64/boot/dts/actions/s700.dtsi
> > > @@ -4,6 +4,7 @@
> > > */
> > > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +#include <dt-bindings/clock/actions,s700-cmu.h>
> > > / {
> > > compatible = "actions,s700";
> > > @@ -44,6 +45,12 @@
> > > };
> > > };
> > > + clock: clock-controller@e0168000 {
> > > + compatible = "actions,s700-cmu";
> > > + reg = <0 0xe0168000 0 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> > There is no fixed rate clock like losc?
>
> losc is 32k, I will add it
>
> > > reserved-memory {
> > > #address-cells = <2>;
> > > #size-cells = <2>;
> > > @@ -129,6 +136,7 @@
> > > compatible = "actions,s900-uart", "actions,owl-uart";
> > > reg = <0x0 0xe0126000 0x0 0x2000>;
> > > interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clock CLK_UART3>;
> > > status = "disabled";
> > > };
> > > diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
> > > new file mode 100644
> > > index 000000000000..e5b4ea130953
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/actions,s700-cmu.h
> > > @@ -0,0 +1,128 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Actions S700 clock driver
> > > + *
> > > + * Copyright (c) 2014 Actions Semi Inc.
> > > + * Author: David Liu <[email protected]>
> > > + *
> > > + * Author: Pathiban Nallathambi <[email protected]>
> > > + * Author: Saravanan Sekar <[email protected]>
> > > + */
> > > +
> > > +#ifndef __DT_BINDINGS_CLOCK_S700_H
> > > +#define __DT_BINDINGS_CLOCK_S700_H
> > > +
> > > +#define CLK_NONE 0
> > > +
> > > +/* fixed rate clocks */
> > > +#define CLK_LOSC 1
> > > +#define CLK_HOSC 2
> > > +
> > > +/* pll clocks */
> > > +#define CLK_CORE_PLL 3
> > > +#define CLK_DEV_PLL 4
> > > +#define CLK_DDR_PLL 5
> > > +#define CLK_NAND_PLL 6
> > > +#define CLK_DISPLAY_PLL 7
> > > +#define CLK_TVOUT_PLL 8
> > > +#define CLK_CVBS_PLL 9
> > > +#define CLK_AUDIO_PLL 10
> > > +#define CLK_ETHERNET_PLL 11
> > > +
> > Remove extra new line please.
> >
> > > +
> > > +/* system clock */
> > > +#define CLK_SYS_BASE 12
> > > +#define CLK_CPU CLK_SYS_BASE
> > > +#define CLK_DEV (CLK_SYS_BASE+1)
> > > +#define CLK_AHB (CLK_SYS_BASE+2)
> > > +#define CLK_APB (CLK_SYS_BASE+3)
> > > +#define CLK_DMAC (CLK_SYS_BASE+4)
> > > +#define CLK_NOC0_CLK_MUX (CLK_SYS_BASE+5)
> > > +#define CLK_NOC1_CLK_MUX (CLK_SYS_BASE+6)
> > > +#define CLK_HP_CLK_MUX (CLK_SYS_BASE+7)
> > > +#define CLK_HP_CLK_DIV (CLK_SYS_BASE+8)
> > > +#define CLK_NOC1_CLK_DIV (CLK_SYS_BASE+9)
> > > +#define CLK_NOC0 (CLK_SYS_BASE+10)
> > > +#define CLK_NOC1 (CLK_SYS_BASE+11)
> > > +#define CLK_SENOR_SRC (CLK_SYS_BASE+12)
> > > +
> > > +/* peripheral device clock */
> > > +#define CLK_PERIP_BASE 25
> > > +#define CLK_GPIO (CLK_PERIP_BASE)
> > > +#define CLK_TIMER (CLK_PERIP_BASE+1)
> > > +#define CLK_DSI (CLK_PERIP_BASE+2)
> > > +#define CLK_CSI (CLK_PERIP_BASE+3)
> > > +#define CLK_SI (CLK_PERIP_BASE+4)
> > > +#define CLK_DE (CLK_PERIP_BASE+5)
> > > +#define CLK_HDE (CLK_PERIP_BASE+6)
> > > +#define CLK_VDE (CLK_PERIP_BASE+7)
> > > +#define CLK_VCE (CLK_PERIP_BASE+8)
> > > +#define CLK_NAND (CLK_PERIP_BASE+9)
> > > +#define CLK_SD0 (CLK_PERIP_BASE+10)
> > > +#define CLK_SD1 (CLK_PERIP_BASE+11)
> > > +#define CLK_SD2 (CLK_PERIP_BASE+12)
> > > +
> > > +#define CLK_UART0 (CLK_PERIP_BASE+13)
> > > +#define CLK_UART1 (CLK_PERIP_BASE+14)
> > > +#define CLK_UART2 (CLK_PERIP_BASE+15)
> > > +#define CLK_UART3 (CLK_PERIP_BASE+16)
> > > +#define CLK_UART4 (CLK_PERIP_BASE+17)
> > > +#define CLK_UART5 (CLK_PERIP_BASE+18)
> > > +#define CLK_UART6 (CLK_PERIP_BASE+19)
> > > +
> > > +#define CLK_PWM0 (CLK_PERIP_BASE+20)
> > > +#define CLK_PWM1 (CLK_PERIP_BASE+21)
> > > +#define CLK_PWM2 (CLK_PERIP_BASE+22)
> > > +#define CLK_PWM3 (CLK_PERIP_BASE+23)
> > > +#define CLK_PWM4 (CLK_PERIP_BASE+24)
> > > +#define CLK_PWM5 (CLK_PERIP_BASE+25)
> > > +#define CLK_GPU3D (CLK_PERIP_BASE+26)
> > > +
> > > +#define CLK_I2C0 (CLK_PERIP_BASE+27)
> > > +#define CLK_I2C1 (CLK_PERIP_BASE+28)
> > > +#define CLK_I2C2 (CLK_PERIP_BASE+29)
> > > +#define CLK_I2C3 (CLK_PERIP_BASE+30)
> > > +
> > > +
> > > +#define CLK_SPI0 (CLK_PERIP_BASE+31)
> > > +#define CLK_SPI1 (CLK_PERIP_BASE+32)
> > > +#define CLK_SPI2 (CLK_PERIP_BASE+33)
> > > +#define CLK_SPI3 (CLK_PERIP_BASE+34)
> > > +
> > > +#define CLK_USB3_480MPLL0 (CLK_PERIP_BASE+35)
> > > +#define CLK_USB3_480MPHY0 (CLK_PERIP_BASE+36)
> > > +#define CLK_USB3_5GPHY (CLK_PERIP_BASE+37)
> > > +#define CLK_USB3_CCE (CLK_PERIP_BASE+48)
> > > +#define CLK_USB3_MAC (CLK_PERIP_BASE+49)
> > > +
> > > +
> > > +#define CLK_LCD (CLK_PERIP_BASE+50)
> > > +#define CLK_HDMI_AUDIO (CLK_PERIP_BASE+51)
> > > +#define CLK_I2SRX (CLK_PERIP_BASE+52)
> > > +#define CLK_I2STX (CLK_PERIP_BASE+53)
> > > +
> > > +#define CLK_SENSOR0 (CLK_PERIP_BASE+54)
> > > +#define CLK_SENSOR1 (CLK_PERIP_BASE+55)
> > > +
> > > +#define CLK_HDMI_DEV (CLK_PERIP_BASE+56)
> > > +
> > > +#define CLK_ETHERNET (CLK_PERIP_BASE+59)
> > > +#define CLK_RMII_REF (CLK_PERIP_BASE+60)
> > > +
> > > +#define CLK_USB2H0_PLLEN (CLK_PERIP_BASE+61)
> > > +#define CLK_USB2H0_PHY (CLK_PERIP_BASE+62)
> > > +#define CLK_USB2H0_CCE (CLK_PERIP_BASE+63)
> > > +#define CLK_USB2H1_PLLEN (CLK_PERIP_BASE+64)
> > > +#define CLK_USB2H1_PHY (CLK_PERIP_BASE+65)
> > > +#define CLK_USB2H1_CCE (CLK_PERIP_BASE+66)
> > > +
> > > +
> > > +#define CLK_TVOUT (CLK_PERIP_BASE+67)
> > > +
> > > +#define CLK_THERMAL_SENSOR (CLK_PERIP_BASE+68)
> > > +
> > > +#define CLK_IRC_SWITCH (CLK_PERIP_BASE+69)
> > > +#define CLK_PCM1 (CLK_PERIP_BASE+70)
> > > +#define CLK_NR_CLKS (CLK_PCM1) /* update on adding new clk */
> > > +
> > Since the index starts from 0, CLK_NR_CLKS should be CLK_PCM1 + 1
>
> 0 is for CLK_NONE, so actual clock starts from 1
>

yes, but the clk register only happens till (CLK_NR_CLKS - 1). Please see
[1] the associated code. With your logic, CLK_PCM1 will never get
registered.

Thanks,
Mani

[1] https://github.com/torvalds/linux/blob/master/drivers/clk/actions/owl-common.c#L69

> > Thanks,
> > Mani
> >
> > > +#endif /* __DT_BINDINGS_CLOCK_S700_H */
> > > --
> > > 2.18.0
> > >
>