2018-07-20 16:35:49

by Marcel Ziswiler

Subject: [PATCH 1/2] ARM: dts: tegra20: restore address order

From: Marcel Ziswiler <[email protected]>

Commit 6c468f109884 ("ARM: dts: tegra: add Tegra20 NAND flash
controller node") introduced the nand-controller node. However, it got
added at the wrong spot not honoring the address order. Fix this.

Signed-off-by: Marcel Ziswiler <[email protected]>

---

arch/arm/boot/dts/tegra20.dtsi | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 979f38293fe5..a22c6a8f8f83 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -419,19 +419,6 @@
status = "disabled";
};

- gmi@70009000 {
- compatible = "nvidia,tegra20-gmi";
- reg = <0x70009000 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0xd0000000 0xfffffff>;
- clocks = <&tegra_car TEGRA20_CLK_NOR>;
- clock-names = "gmi";
- resets = <&tegra_car 42>;
- reset-names = "gmi";
- status = "disabled";
- };
-
nand-controller@70008000 {
compatible = "nvidia,tegra20-nand";
reg = <0x70008000 0x100>;
@@ -447,6 +434,19 @@
status = "disabled";
};

+ gmi@70009000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd0000000 0xfffffff>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ status = "disabled";
+ };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
--
2.14.4

2018-07-20 16:35:41

by Marcel Ziswiler

Subject: [PATCH 2/2] ARM: dts: tegra20/tegra30: add pmu interrupt-affinity

From: Marcel Ziswiler <[email protected]>

This is similar to tegra124 and avoids the following being reported
upon boot:

hw perfevents: no interrupt-affinity property for /pmu, guessing.

Signed-off-by: Marcel Ziswiler <[email protected]>

---

arch/arm/boot/dts/tegra20.dtsi | 2 ++
arch/arm/boot/dts/tegra30.dtsi | 4 ++++
2 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index a22c6a8f8f83..dcad6d6128cf 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -867,5 +867,7 @@
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&{/cpus/cpu@0}>,
+ <&{/cpus/cpu@1}>;
};
};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index a6781f653310..1de10f0d1da7 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1013,5 +1013,9 @@
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&{/cpus/cpu@0}>,
+ <&{/cpus/cpu@1}>,
+ <&{/cpus/cpu@2}>,
+ <&{/cpus/cpu@3}>;
};
};
--
2.14.4

2018-07-26 08:39:34

by Stefan Agner

Subject: Re: [PATCH 1/2] ARM: dts: tegra20: restore address order

On 20.07.2018 18:34, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <[email protected]>
>
> Commit 6c468f109884 ("ARM: dts: tegra: add Tegra20 NAND flash
> controller node") introduced the nand-controller node. However, it got
> added at the wrong spot not honoring the address order. Fix this.
>
> Signed-off-by: Marcel Ziswiler <[email protected]>

Reviewed-by: Stefan Agner <[email protected]>

>
> ---
>
> arch/arm/boot/dts/tegra20.dtsi | 26 +++++++++++++-------------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> index 979f38293fe5..a22c6a8f8f83 100644
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ b/arch/arm/boot/dts/tegra20.dtsi
> @@ -419,19 +419,6 @@
> status = "disabled";
> };
>
> - gmi@70009000 {
> - compatible = "nvidia,tegra20-gmi";
> - reg = <0x70009000 0x1000>;
> - #address-cells = <2>;
> - #size-cells = <1>;
> - ranges = <0 0 0xd0000000 0xfffffff>;
> - clocks = <&tegra_car TEGRA20_CLK_NOR>;
> - clock-names = "gmi";
> - resets = <&tegra_car 42>;
> - reset-names = "gmi";
> - status = "disabled";
> - };
> -
> nand-controller@70008000 {
> compatible = "nvidia,tegra20-nand";
> reg = <0x70008000 0x100>;
> @@ -447,6 +434,19 @@
> status = "disabled";
> };
>
> + gmi@70009000 {
> + compatible = "nvidia,tegra20-gmi";
> + reg = <0x70009000 0x1000>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0 0xd0000000 0xfffffff>;
> + clocks = <&tegra_car TEGRA20_CLK_NOR>;
> + clock-names = "gmi";
> + resets = <&tegra_car 42>;
> + reset-names = "gmi";
> + status = "disabled";
> + };
> +
> pwm: pwm@7000a000 {
> compatible = "nvidia,tegra20-pwm";
> reg = <0x7000a000 0x100>;

2018-07-26 08:43:18

by Stefan Agner

Subject: Re: [PATCH 2/2] ARM: dts: tegra20/tegra30: add pmu interrupt-affinity

On 20.07.2018 18:34, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <[email protected]>
>
> This is similar to tegra124 and avoids the following being reported
> upon boot:
>
> hw perfevents: no interrupt-affinity property for /pmu, guessing.
>
> Signed-off-by: Marcel Ziswiler <[email protected]>

Reviewed-by: Stefan Agner <[email protected]>

>
> ---
>
> arch/arm/boot/dts/tegra20.dtsi | 2 ++
> arch/arm/boot/dts/tegra30.dtsi | 4 ++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> index a22c6a8f8f83..dcad6d6128cf 100644
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ b/arch/arm/boot/dts/tegra20.dtsi
> @@ -867,5 +867,7 @@
> compatible = "arm,cortex-a9-pmu";
> interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&{/cpus/cpu@0}>,
> + <&{/cpus/cpu@1}>;
> };
> };
> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> index a6781f653310..1de10f0d1da7 100644
> --- a/arch/arm/boot/dts/tegra30.dtsi
> +++ b/arch/arm/boot/dts/tegra30.dtsi
> @@ -1013,5 +1013,9 @@
> <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&{/cpus/cpu@0}>,
> + <&{/cpus/cpu@1}>,
> + <&{/cpus/cpu@2}>,
> + <&{/cpus/cpu@3}>;
> };
> };