Remove Reset operation in fsl_lpspi_config(). This RST may cause both CLK
and CS pins go from high to low level under cs-gpio mode.
Add fsl_lpspi_reset() function after one message transfer to clear all
flags in use.
Signed-off-by: Clark Wang <[email protected]>
Reviewed-by: Fugang Duan <[email protected]>
---
drivers/spi/spi-fsl-lpspi.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index f32a2e0d7ae1..a7d01b79827b 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -279,10 +279,6 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
u32 temp;
int ret;
- temp = CR_RST;
- writel(temp, fsl_lpspi->base + IMX7ULP_CR);
- writel(0, fsl_lpspi->base + IMX7ULP_CR);
-
if (!fsl_lpspi->is_slave) {
ret = fsl_lpspi_set_bitrate(fsl_lpspi);
if (ret)
@@ -373,6 +369,24 @@ static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
return 0;
}
+static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
+{
+ u32 temp;
+
+ /* Disable all interrupt */
+ fsl_lpspi_intctrl(fsl_lpspi, 0);
+
+ /* W1C for all flags in SR */
+ temp = 0x3F << 8;
+ writel(temp, fsl_lpspi->base + IMX7ULP_SR);
+
+ /* Clear FIFO and disable module */
+ temp = CR_RRF | CR_RTF;
+ writel(temp, fsl_lpspi->base + IMX7ULP_CR);
+
+ return 0;
+}
+
static int fsl_lpspi_transfer_one(struct spi_controller *controller,
struct spi_device *spi,
struct spi_transfer *t)
@@ -394,6 +408,8 @@ static int fsl_lpspi_transfer_one(struct spi_controller *controller,
if (ret)
return ret;
+ fsl_lpspi_reset(fsl_lpspi);
+
return 0;
}
--
2.17.1
On Tue, Dec 04, 2018 at 06:23:19AM +0000, Clark Wang wrote:
> Remove Reset operation in fsl_lpspi_config(). This RST may cause both CLK
> and CS pins go from high to low level under cs-gpio mode.
> Add fsl_lpspi_reset() function after one message transfer to clear all
> flags in use.
This doesn't apply against current code, please check and resend.
Hi Mark,
These five patches are based on patch series spi: lpspi: Add Slave Mode support for LPSPI. For the patch series make a big change, should I hold these five patches until the patch series are applied in your git branch?
Thanks for your patience.
Regards,
Clark Wang
> -----Original Message-----
> From: Mark Brown <[email protected]>
> Sent: Tuesday, December 11, 2018 22:30
> To: Clark Wang <[email protected]>
> Cc: [email protected]; [email protected]
> Subject: Re: [PATCH] spi: lpspi: Fix CLK pin becomes low before one transfer
>
> On Tue, Dec 04, 2018 at 06:23:19AM +0000, Clark Wang wrote:
> > Remove Reset operation in fsl_lpspi_config(). This RST may cause both
> > CLK and CS pins go from high to low level under cs-gpio mode.
> > Add fsl_lpspi_reset() function after one message transfer to clear all
> > flags in use.
>
> This doesn't apply against current code, please check and resend.
On Wed, Dec 12, 2018 at 02:10:46AM +0000, Clark Wang wrote:
> These five patches are based on patch series spi: lpspi: Add Slave Mode support for LPSPI. For the patch series make a big change, should I hold these five patches until the patch series are applied in your git branch?
OK, if you're sending patches that depend on other things that are still
in review it's important to call that out in the cover letter for the
series or after the --- for single patches, that way it's clear what's
going on. Please resend these as a series with a note pointing at the
other series.
Please don't top post, reply in line with needed context. This allows
readers to readily follow the flow of conversation and understand what
you are talking about and also helps ensure that everything in the
discussion is being addressed.
Please fix your mail client to word wrap within paragraphs at something
substantially less than 80 columns. Doing this makes your messages much
easier to read and reply to.