2019-01-10 10:13:49

by Peng Ma

Subject: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support

Lx2160a is a new introduced soc which supports ATA3.0 and
Clean up some code

Signed-off-by: Peng Ma <[email protected]>
---
drivers/ata/ahci_qoriq.c | 44 ++++++++++++--------------------------------
1 files changed, 12 insertions(+), 32 deletions(-)

diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index ce59253..1994bf2 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -57,7 +57,7 @@ enum ahci_qoriq_type {
AHCI_LS2080A,
AHCI_LS1046A,
AHCI_LS1088A,
- AHCI_LS2088A,
+ AHCI_LX2160A,
};

struct ahci_qoriq_priv {
@@ -73,7 +73,7 @@ struct ahci_qoriq_priv {
{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
- { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
@@ -174,12 +174,10 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG,
- reg_base + LS1021A_AXICC_ADDR);
break;

case AHCI_LS1043A:
+ case AHCI_LS1046A:
if (!qpriv->ecc_addr)
return -EINVAL;
writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
@@ -188,8 +186,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;

case AHCI_LS2080A:
@@ -197,24 +193,10 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
- break;
-
- case AHCI_LS1046A:
- if (!qpriv->ecc_addr)
- return -EINVAL;
- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
- qpriv->ecc_addr);
- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;

case AHCI_LS1088A:
+ case AHCI_LX2160A:
if (!qpriv->ecc_addr)
return -EINVAL;
writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
@@ -223,18 +205,16 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
+ }

- case AHCI_LS2088A:
- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- if (qpriv->is_dmacoherent)
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
- break;
+ if (qpriv->is_dmacoherent) {
+ if (qpriv->type == AHCI_LS1021A)
+ writel(AHCI_PORT_AXICC_CFG,
+ reg_base + LS1021A_AXICC_ADDR);
+ else
+ writel(AHCI_PORT_AXICC_CFG,
+ reg_base + PORT_AXICC);
}

return 0;
--
1.7.1

2019-01-10 10:33:40

by Peng Ma

Subject: RE: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support

Hi Jens??

I send the sata patchs to the upstream patchwork with ./scripts/get_maintainer.pl, but I find my patch on http://patchwork.ozlabs.org/project/linux-ide/list/ , I saw the MAINTAINERS, the driver/ata/* should be on https://patchwork.kernel.org/project/linux-block/list/ . could you please help me what the patchwork is right.
Thanks a lot.

Best Regards,
Peng

>-----Original Message-----
>From: Peng Ma <[email protected]>
>Sent: 2019??1??10?? 18:06
>To: [email protected]; [email protected]
>Cc: Leo Li <[email protected]>; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; Peng Ma <[email protected]>
>Subject: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
>
>Lx2160a is a new introduced soc which supports ATA3.0 and Clean up some
>code
>
>Signed-off-by: Peng Ma <[email protected]>
>---
> drivers/ata/ahci_qoriq.c | 44 ++++++++++++--------------------------------
> 1 files changed, 12 insertions(+), 32 deletions(-)
>
>diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index
>ce59253..1994bf2 100644
>--- a/drivers/ata/ahci_qoriq.c
>+++ b/drivers/ata/ahci_qoriq.c
>@@ -57,7 +57,7 @@ enum ahci_qoriq_type {
> AHCI_LS2080A,
> AHCI_LS1046A,
> AHCI_LS1088A,
>- AHCI_LS2088A,
>+ AHCI_LX2160A,
> };
>
> struct ahci_qoriq_priv {
>@@ -73,7 +73,7 @@ struct ahci_qoriq_priv {
> { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
> { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
> { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
>- { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
>+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
> {},
> };
> MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match); @@ -174,12 +174,10
>@@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
> writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG,
>- reg_base + LS1021A_AXICC_ADDR);
> break;
>
> case AHCI_LS1043A:
>+ case AHCI_LS1046A:
> if (!qpriv->ecc_addr)
> return -EINVAL;
> writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, @@ -188,8
>+186,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
>
> case AHCI_LS2080A:
>@@ -197,24 +193,10 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
>*hpriv)
> writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
>- break;
>-
>- case AHCI_LS1046A:
>- if (!qpriv->ecc_addr)
>- return -EINVAL;
>- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
>- qpriv->ecc_addr);
>- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
>- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
>- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
>- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
>
> case AHCI_LS1088A:
>+ case AHCI_LX2160A:
> if (!qpriv->ecc_addr)
> return -EINVAL;
> writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A, @@ -223,18
>+205,16 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
>+ }
>
>- case AHCI_LS2088A:
>- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
>- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
>- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
>- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>- if (qpriv->is_dmacoherent)
>- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
>- break;
>+ if (qpriv->is_dmacoherent) {
>+ if (qpriv->type == AHCI_LS1021A)
>+ writel(AHCI_PORT_AXICC_CFG,
>+ reg_base + LS1021A_AXICC_ADDR);
>+ else
>+ writel(AHCI_PORT_AXICC_CFG,
>+ reg_base + PORT_AXICC);
> }
>
> return 0;
>--
>1.7.1

2019-01-10 10:52:53

by Peng Ma

Subject: [PATCH 2/2] arm64: dts: lx2160a: add sata node support

Add sata node support and Enable sata support

Signed-off-by: Peng Ma <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++++++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 44 +++++++++++++++++++++
2 files changed, 60 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f..aacca27 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -117,3 +117,19 @@
&usb1 {
status = "okay";
};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1..e857a14 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -762,5 +762,49 @@
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
+
+ sata0: sata@3200000 {
+ status = "disabled";
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ };
+
+ sata1: sata@3210000 {
+ status = "disabled";
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x3210000 0x0 0x10000>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ };
+
+ sata2: sata@3220000 {
+ status = "disabled";
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x3220000 0x0 0x10000>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ };
+
+ sata3: sata@3230000 {
+ status = "disabled";
+ compatible = "fsl,lx2160a-ahci";
+ reg = <0x0 0x3230000 0x0 0x10000>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>;
+ dma-coherent;
+ };
};
};
--
1.7.1

2019-01-10 21:20:34

by Leo Li

Subject: RE: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support

> -----Original Message-----
> From: Peng Ma
> Sent: Thursday, January 10, 2019 4:32 AM
> To: Peng Ma <[email protected]>; [email protected];
> [email protected]
> Cc: Leo Li <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; Andy Tang <[email protected]>
> Subject: RE: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
>
> Hi Jens??
>
> I send the sata patchs to the upstream patchwork
> with ./scripts/get_maintainer.pl, but I find my patch on
> http://patchwork.ozlabs.org/project/linux-ide/list/ , I saw the MAINTAINERS,
> the driver/ata/* should be on https://patchwork.kernel.org/project/linux-
> block/list/ . could you please help me what the patchwork is right.

Peng,

The patchwork used is related to the mailing list which you send the patch to not the maintainer's git tree used. Since the MAINTAINERS file says drivers/ata should use linux-ide mailing list, patches will appear in linux-ide patchwork.

Regards,
Leo

> Thanks a lot.
>
> Best Regards,
> Peng
>
> >-----Original Message-----
> >From: Peng Ma <[email protected]>
> >Sent: 2019??1??10?? 18:06
> >To: [email protected]; [email protected]
> >Cc: Leo Li <[email protected]>; [email protected];
> >[email protected]; [email protected];
> >[email protected]; [email protected];
> >[email protected]; Peng Ma <[email protected]>
> >Subject: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
> >
> >Lx2160a is a new introduced soc which supports ATA3.0 and Clean up some
> >code
> >
> >Signed-off-by: Peng Ma <[email protected]>
> >---
> > drivers/ata/ahci_qoriq.c | 44 ++++++++++++--------------------------------
> > 1 files changed, 12 insertions(+), 32 deletions(-)
> >
> >diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index
> >ce59253..1994bf2 100644
> >--- a/drivers/ata/ahci_qoriq.c
> >+++ b/drivers/ata/ahci_qoriq.c
> >@@ -57,7 +57,7 @@ enum ahci_qoriq_type {
> > AHCI_LS2080A,
> > AHCI_LS1046A,
> > AHCI_LS1088A,
> >- AHCI_LS2088A,
> >+ AHCI_LX2160A,
> > };
> >
> > struct ahci_qoriq_priv {
> >@@ -73,7 +73,7 @@ struct ahci_qoriq_priv {
> > { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
> > { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
> > { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
> >- { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
> >+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
> > {},
> > };
> > MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match); @@ -174,12 +174,10
> @@
> >static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> > writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
> > writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
> > writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> >- if (qpriv->is_dmacoherent)
> >- writel(AHCI_PORT_AXICC_CFG,
> >- reg_base + LS1021A_AXICC_ADDR);
> > break;
> >
> > case AHCI_LS1043A:
> >+ case AHCI_LS1046A:
> > if (!qpriv->ecc_addr)
> > return -EINVAL;
> > writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, @@ -
> 188,8
> >+186,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> > writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> > writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> > writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> >- if (qpriv->is_dmacoherent)
> >- writel(AHCI_PORT_AXICC_CFG, reg_base +
> PORT_AXICC);
> > break;
> >
> > case AHCI_LS2080A:
> >@@ -197,24 +193,10 @@ static int ahci_qoriq_phy_init(struct
> >ahci_host_priv
> >*hpriv)
> > writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> > writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> > writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> >- if (qpriv->is_dmacoherent)
> >- writel(AHCI_PORT_AXICC_CFG, reg_base +
> PORT_AXICC);
> >- break;
> >-
> >- case AHCI_LS1046A:
> >- if (!qpriv->ecc_addr)
> >- return -EINVAL;
> >- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
> >- qpriv->ecc_addr);
> >- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> >- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> >- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> >- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> >- if (qpriv->is_dmacoherent)
> >- writel(AHCI_PORT_AXICC_CFG, reg_base +
> PORT_AXICC);
> > break;
> >
> > case AHCI_LS1088A:
> >+ case AHCI_LX2160A:
> > if (!qpriv->ecc_addr)
> > return -EINVAL;
> > writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A, @@ -
> 223,18
> >+205,16 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> > writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> > writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> > writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> >- if (qpriv->is_dmacoherent)
> >- writel(AHCI_PORT_AXICC_CFG, reg_base +
> PORT_AXICC);
> > break;
> >+ }
> >
> >- case AHCI_LS2088A:
> >- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> >- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
> >- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
> >- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> >- if (qpriv->is_dmacoherent)
> >- writel(AHCI_PORT_AXICC_CFG, reg_base +
> PORT_AXICC);
> >- break;
> >+ if (qpriv->is_dmacoherent) {
> >+ if (qpriv->type == AHCI_LS1021A)
> >+ writel(AHCI_PORT_AXICC_CFG,
> >+ reg_base + LS1021A_AXICC_ADDR);
> >+ else
> >+ writel(AHCI_PORT_AXICC_CFG,
> >+ reg_base + PORT_AXICC);
> > }
> >
> > return 0;
> >--
> >1.7.1

2019-01-11 07:54:02

by Peng Ma

Subject: RE: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support

>-----Original Message-----
>From: Leo Li
>Sent: 2019??1??11?? 4:30
>To: Peng Ma <[email protected]>; [email protected]; [email protected]
>Cc: [email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected]; Andy Tang
><[email protected]>
>Subject: RE: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
>
>
>
>> -----Original Message-----
>> From: Peng Ma
>> Sent: Thursday, January 10, 2019 4:32 AM
>> To: Peng Ma <[email protected]>; [email protected]; [email protected]
>> Cc: Leo Li <[email protected]>; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected]; linux-
>> [email protected]; Andy Tang <[email protected]>
>> Subject: RE: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
>>
>> Hi Jens??
>>
>> I send the sata patchs to the upstream patchwork with
>> ./scripts/get_maintainer.pl, but I find my patch on
>> http://patchwork.ozlabs.org/project/linux-ide/list/ , I saw the
>> MAINTAINERS, the driver/ata/* should be on
>> https://patchwork.kernel.org/project/linux-
>> block/list/ . could you please help me what the patchwork is right.
>
>Peng,
>
>The patchwork used is related to the mailing list which you send the patch to
>not the maintainer's git tree used. Since the MAINTAINERS file says
>drivers/ata should use linux-ide mailing list, patches will appear in linux-ide
>patchwork.
>
>Regards,
>Leo
>
[Peng Ma] got it, thanks.
Best Regards,
Peng
>> Thanks a lot.
>>
>> Best Regards,
>> Peng
>>
>> >-----Original Message-----
>> >From: Peng Ma <[email protected]>
>> >Sent: 2019??1??10?? 18:06
>> >To: [email protected]; [email protected]
>> >Cc: Leo Li <[email protected]>; [email protected];
>> >[email protected]; [email protected];
>> >[email protected]; [email protected];
>> >[email protected]; Peng Ma <[email protected]>
>> >Subject: [PATCH 1/2] ahci: qoriq: add lx2160 platforms support
>> >
>> >Lx2160a is a new introduced soc which supports ATA3.0 and Clean up
>> >some code
>> >
>> >Signed-off-by: Peng Ma <[email protected]>
>> >---
>> > drivers/ata/ahci_qoriq.c | 44 ++++++++++++--------------------------------
>> > 1 files changed, 12 insertions(+), 32 deletions(-)
>> >
>> >diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
>> >index
>> >ce59253..1994bf2 100644
>> >--- a/drivers/ata/ahci_qoriq.c
>> >+++ b/drivers/ata/ahci_qoriq.c
>> >@@ -57,7 +57,7 @@ enum ahci_qoriq_type {
>> > AHCI_LS2080A,
>> > AHCI_LS1046A,
>> > AHCI_LS1088A,
>> >- AHCI_LS2088A,
>> >+ AHCI_LX2160A,
>> > };
>> >
>> > struct ahci_qoriq_priv {
>> >@@ -73,7 +73,7 @@ struct ahci_qoriq_priv {
>> > { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
>> > { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
>> > { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
>> >- { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
>> >+ { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
>> > {},
>> > };
>> > MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match); @@ -174,12 +174,10
>> @@
>> >static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
>> > writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
>> > writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
>> > writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>> >- if (qpriv->is_dmacoherent)
>> >- writel(AHCI_PORT_AXICC_CFG,
>> >- reg_base + LS1021A_AXICC_ADDR);
>> > break;
>> >
>> > case AHCI_LS1043A:
>> >+ case AHCI_LS1046A:
>> > if (!qpriv->ecc_addr)
>> > return -EINVAL;
>> > writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, @@ -
>> 188,8
>> >+186,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
>> >+*hpriv)
>> > writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
>> > writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
>> > writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>> >- if (qpriv->is_dmacoherent)
>> >- writel(AHCI_PORT_AXICC_CFG, reg_base +
>> PORT_AXICC);
>> > break;
>> >
>> > case AHCI_LS2080A:
>> >@@ -197,24 +193,10 @@ static int ahci_qoriq_phy_init(struct
>> >ahci_host_priv
>> >*hpriv)
>> > writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
>> > writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
>> > writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>> >- if (qpriv->is_dmacoherent)
>> >- writel(AHCI_PORT_AXICC_CFG, reg_base +
>> PORT_AXICC);
>> >- break;
>> >-
>> >- case AHCI_LS1046A:
>> >- if (!qpriv->ecc_addr)
>> >- return -EINVAL;
>> >- writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
>> >- qpriv->ecc_addr);
>> >- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
>> >- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
>> >- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
>> >- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>> >- if (qpriv->is_dmacoherent)
>> >- writel(AHCI_PORT_AXICC_CFG, reg_base +
>> PORT_AXICC);
>> > break;
>> >
>> > case AHCI_LS1088A:
>> >+ case AHCI_LX2160A:
>> > if (!qpriv->ecc_addr)
>> > return -EINVAL;
>> > writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A, @@ -
>> 223,18
>> >+205,16 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
>> >+*hpriv)
>> > writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
>> > writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
>> > writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>> >- if (qpriv->is_dmacoherent)
>> >- writel(AHCI_PORT_AXICC_CFG, reg_base +
>> PORT_AXICC);
>> > break;
>> >+ }
>> >
>> >- case AHCI_LS2088A:
>> >- writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
>> >- writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
>> >- writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
>> >- writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
>> >- if (qpriv->is_dmacoherent)
>> >- writel(AHCI_PORT_AXICC_CFG, reg_base +
>> PORT_AXICC);
>> >- break;
>> >+ if (qpriv->is_dmacoherent) {
>> >+ if (qpriv->type == AHCI_LS1021A)
>> >+ writel(AHCI_PORT_AXICC_CFG,
>> >+ reg_base + LS1021A_AXICC_ADDR);
>> >+ else
>> >+ writel(AHCI_PORT_AXICC_CFG,
>> >+ reg_base + PORT_AXICC);
>> > }
>> >
>> > return 0;
>> >--
>> >1.7.1

2019-01-13 04:51:52

by Shawn Guo

Subject: Re: [PATCH 2/2] arm64: dts: lx2160a: add sata node support

On Thu, Jan 10, 2019 at 06:05:33PM +0800, Peng Ma wrote:
> Add sata node support and Enable sata support
>
> Signed-off-by: Peng Ma <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++++++
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 44 +++++++++++++++++++++
> 2 files changed, 60 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> index 6481e5f..aacca27 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> @@ -117,3 +117,19 @@
> &usb1 {
> status = "okay";
> };
> +
> +&sata0 {
> + status = "okay";
> +};
> +
> +&sata1 {
> + status = "okay";
> +};
> +
> +&sata2 {
> + status = "okay";
> +};
> +
> +&sata3 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index a79f5c1..e857a14 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -762,5 +762,49 @@
> <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
> dma-coherent;
> };
> +
> + sata0: sata@3200000 {
> + status = "disabled";

We usually have 'status' at the end of property list.

Shawn

> + compatible = "fsl,lx2160a-ahci";
> + reg = <0x0 0x3200000 0x0 0x10000>,
> + <0x7 0x100520 0x0 0x4>;
> + reg-names = "ahci", "sata-ecc";
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 3>;
> + dma-coherent;
> + };
> +
> + sata1: sata@3210000 {
> + status = "disabled";
> + compatible = "fsl,lx2160a-ahci";
> + reg = <0x0 0x3210000 0x0 0x10000>,
> + <0x7 0x100520 0x0 0x4>;
> + reg-names = "ahci", "sata-ecc";
> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 3>;
> + dma-coherent;
> + };
> +
> + sata2: sata@3220000 {
> + status = "disabled";
> + compatible = "fsl,lx2160a-ahci";
> + reg = <0x0 0x3220000 0x0 0x10000>,
> + <0x7 0x100520 0x0 0x4>;
> + reg-names = "ahci", "sata-ecc";
> + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 3>;
> + dma-coherent;
> + };
> +
> + sata3: sata@3230000 {
> + status = "disabled";
> + compatible = "fsl,lx2160a-ahci";
> + reg = <0x0 0x3230000 0x0 0x10000>,
> + <0x7 0x100520 0x0 0x4>;
> + reg-names = "ahci", "sata-ecc";
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 3>;
> + dma-coherent;
> + };
> };
> };
> --
> 1.7.1
>

2019-01-14 09:54:20

by Peng Ma

Subject: RE: [PATCH 2/2] arm64: dts: lx2160a: add sata node support

>-----Original Message-----
>From: Shawn Guo <[email protected]>
>Sent: 2019??1??13?? 12:06
>To: Peng Ma <[email protected]>
>Cc: [email protected]; Leo Li <[email protected]>; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]
>Subject: Re: [PATCH 2/2] arm64: dts: lx2160a: add sata node support
>
>On Thu, Jan 10, 2019 at 06:05:33PM +0800, Peng Ma wrote:
>> Add sata node support and Enable sata support
>>
>> Signed-off-by: Peng Ma <[email protected]>
>> ---
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 16 +++++++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 44
>+++++++++++++++++++++
>> 2 files changed, 60 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> index 6481e5f..aacca27 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>> @@ -117,3 +117,19 @@
>> &usb1 {
>> status = "okay";
>> };
>> +
>> +&sata0 {
>> + status = "okay";
>> +};
>> +
>> +&sata1 {
>> + status = "okay";
>> +};
>> +
>> +&sata2 {
>> + status = "okay";
>> +};
>> +
>> +&sata3 {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> index a79f5c1..e857a14 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> @@ -762,5 +762,49 @@
>> <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
>> dma-coherent;
>> };
>> +
>> + sata0: sata@3200000 {
>> + status = "disabled";
>
>We usually have 'status' at the end of property list.
>
>Shawn
[Peng Ma]
Ok, got it, thanks yure quick reply.
Regards,
Peng
>
>> + compatible = "fsl,lx2160a-ahci";
>> + reg = <0x0 0x3200000 0x0 0x10000>,
>> + <0x7 0x100520 0x0 0x4>;
>> + reg-names = "ahci", "sata-ecc";
>> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clockgen 4 3>;
>> + dma-coherent;
>> + };
>> +
>> + sata1: sata@3210000 {
>> + status = "disabled";
>> + compatible = "fsl,lx2160a-ahci";
>> + reg = <0x0 0x3210000 0x0 0x10000>,
>> + <0x7 0x100520 0x0 0x4>;
>> + reg-names = "ahci", "sata-ecc";
>> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clockgen 4 3>;
>> + dma-coherent;
>> + };
>> +
>> + sata2: sata@3220000 {
>> + status = "disabled";
>> + compatible = "fsl,lx2160a-ahci";
>> + reg = <0x0 0x3220000 0x0 0x10000>,
>> + <0x7 0x100520 0x0 0x4>;
>> + reg-names = "ahci", "sata-ecc";
>> + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clockgen 4 3>;
>> + dma-coherent;
>> + };
>> +
>> + sata3: sata@3230000 {
>> + status = "disabled";
>> + compatible = "fsl,lx2160a-ahci";
>> + reg = <0x0 0x3230000 0x0 0x10000>,
>> + <0x7 0x100520 0x0 0x4>;
>> + reg-names = "ahci", "sata-ecc";
>> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clockgen 4 3>;
>> + dma-coherent;
>> + };
>> };
>> };
>> --
>> 1.7.1
>>