Add i.MX8QXP CPU opp table to support cpufreq.
Signed-off-by: Anson Huang <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
---
No changes since V6.
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 4c3dd95..41bf0ce 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -34,6 +34,9 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_A35_CLK>;
+ operating-points-v2 = <&a35_0_opp_table>;
+ #cooling-cells = <2>;
};
A35_1: cpu@1 {
@@ -42,6 +45,9 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_A35_CLK>;
+ operating-points-v2 = <&a35_0_opp_table>;
+ #cooling-cells = <2>;
};
A35_2: cpu@2 {
@@ -50,6 +56,9 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_A35_CLK>;
+ operating-points-v2 = <&a35_0_opp_table>;
+ #cooling-cells = <2>;
};
A35_3: cpu@3 {
@@ -58,6 +67,9 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_A35_CLK>;
+ operating-points-v2 = <&a35_0_opp_table>;
+ #cooling-cells = <2>;
};
A35_L2: l2-cache0 {
@@ -65,6 +77,24 @@
};
};
+ a35_0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
--
2.7.4
On NXP's i.MX SoCs with system controller inside, CPU frequency
scaling can ONLY be done by system controller firmware, and it
can ONLY be requested from secure mode, so Linux kernel has to
call ARM SMC to trap to ARM-Trusted-Firmware to request system
controller firmware to do CPU frequency scaling.
This patch adds i.MX system controller CPU frequency scaling support,
it reuses cpufreq-dt driver and implement the CPU frequency scaling
inside SCU clock driver.
Signed-off-by: Anson Huang <[email protected]>
---
Changes since V6:
- add return fail to clk_scu_atf_set_cpu_rate() when the resource ID
is NOT expected, this is to avoid warning of uninitialized data usage.
---
drivers/clk/imx/clk-scu.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
index f460526..fbef740 100644
--- a/drivers/clk/imx/clk-scu.c
+++ b/drivers/clk/imx/clk-scu.c
@@ -4,12 +4,17 @@
* Dong Aisheng <[email protected]>
*/
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <linux/arm-smccc.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/slab.h>
#include "clk-scu.h"
+#define IMX_SIP_CPUFREQ 0xC2000001
+#define IMX_SIP_SET_CPUFREQ 0x00
+
static struct imx_sc_ipc *ccm_ipc_handle;
/*
@@ -180,6 +185,25 @@ static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate,
return rate;
}
+static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_scu *clk = to_clk_scu(hw);
+ struct arm_smccc_res res;
+ unsigned long cluster_id;
+
+ if (clk->rsrc_id == IMX_SC_R_A35)
+ cluster_id = 0;
+ else
+ return -EINVAL;
+
+ /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */
+ arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ,
+ cluster_id, rate, 0, 0, 0, 0, &res);
+
+ return 0;
+}
+
/*
* clk_scu_set_rate - Set rate for a SCU clock
* @hw: clock to change rate for
@@ -312,6 +336,14 @@ static const struct clk_ops clk_scu_ops = {
.unprepare = clk_scu_unprepare,
};
+static const struct clk_ops clk_scu_cpu_ops = {
+ .recalc_rate = clk_scu_recalc_rate,
+ .round_rate = clk_scu_round_rate,
+ .set_rate = clk_scu_atf_set_cpu_rate,
+ .prepare = clk_scu_prepare,
+ .unprepare = clk_scu_unprepare,
+};
+
struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
int num_parents, u32 rsrc_id, u8 clk_type)
{
@@ -329,6 +361,10 @@ struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
init.name = name;
init.ops = &clk_scu_ops;
+ if (rsrc_id == IMX_SC_R_A35)
+ init.ops = &clk_scu_cpu_ops;
+ else
+ init.ops = &clk_scu_ops;
init.parent_names = parents;
init.num_parents = num_parents;
--
2.7.4
Quoting Anson Huang (2019-02-25 21:17:36)
> On NXP's i.MX SoCs with system controller inside, CPU frequency
> scaling can ONLY be done by system controller firmware, and it
> can ONLY be requested from secure mode, so Linux kernel has to
> call ARM SMC to trap to ARM-Trusted-Firmware to request system
> controller firmware to do CPU frequency scaling.
>
> This patch adds i.MX system controller CPU frequency scaling support,
> it reuses cpufreq-dt driver and implement the CPU frequency scaling
> inside SCU clock driver.
>
> Signed-off-by: Anson Huang <[email protected]>
> ---
Applied to clk-next
On Tue, Feb 26, 2019 at 05:17:31AM +0000, Anson Huang wrote:
> Add i.MX8QXP CPU opp table to support cpufreq.
>
> Signed-off-by: Anson Huang <[email protected]>
> Acked-by: Viresh Kumar <[email protected]>
Prefix 'arm64: dts: imx8qxp: ' would already be clear enough. I dropped
'freescale' from there and applied patch.
> ---
> No changes since V6.
> ---
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 4c3dd95..41bf0ce 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -34,6 +34,9 @@
> reg = <0x0 0x0>;
> enable-method = "psci";
> next-level-cache = <&A35_L2>;
> + clocks = <&clk IMX_A35_CLK>;
> + operating-points-v2 = <&a35_0_opp_table>;
> + #cooling-cells = <2>;
> };
>
> A35_1: cpu@1 {
> @@ -42,6 +45,9 @@
> reg = <0x0 0x1>;
> enable-method = "psci";
> next-level-cache = <&A35_L2>;
> + clocks = <&clk IMX_A35_CLK>;
> + operating-points-v2 = <&a35_0_opp_table>;
> + #cooling-cells = <2>;
> };
>
> A35_2: cpu@2 {
> @@ -50,6 +56,9 @@
> reg = <0x0 0x2>;
> enable-method = "psci";
> next-level-cache = <&A35_L2>;
> + clocks = <&clk IMX_A35_CLK>;
> + operating-points-v2 = <&a35_0_opp_table>;
> + #cooling-cells = <2>;
> };
>
> A35_3: cpu@3 {
> @@ -58,6 +67,9 @@
> reg = <0x0 0x3>;
> enable-method = "psci";
> next-level-cache = <&A35_L2>;
> + clocks = <&clk IMX_A35_CLK>;
> + operating-points-v2 = <&a35_0_opp_table>;
> + #cooling-cells = <2>;
> };
>
> A35_L2: l2-cache0 {
> @@ -65,6 +77,24 @@
> };
> };
>
> + a35_0_opp_table: opp-table {
What does the '0' in the label mean?
Shawn
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-900000000 {
> + opp-hz = /bits/ 64 <900000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <150000>;
> + };
> +
> + opp-1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <150000>;
> + opp-suspend;
> + };
> + };
> +
> gic: interrupt-controller@51a00000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi, Shawn
Best Regards!
Anson Huang
> -----Original Message-----
> From: Shawn Guo [mailto:[email protected]]
> Sent: 2019??2??28?? 11:19
> To: Anson Huang <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; Aisheng Dong <[email protected]>; Daniel Baluta
> <[email protected]>; [email protected]; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; dl-linux-imx <[email protected]>
> Subject: Re: [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp
> table
>
> On Tue, Feb 26, 2019 at 05:17:31AM +0000, Anson Huang wrote:
> > Add i.MX8QXP CPU opp table to support cpufreq.
> >
> > Signed-off-by: Anson Huang <[email protected]>
> > Acked-by: Viresh Kumar <[email protected]>
>
> Prefix 'arm64: dts: imx8qxp: ' would already be clear enough. I dropped
> 'freescale' from there and applied patch.
>
> > ---
> > No changes since V6.
> > ---
> > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30
> > ++++++++++++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > index 4c3dd95..41bf0ce 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > @@ -34,6 +34,9 @@
> > reg = <0x0 0x0>;
> > enable-method = "psci";
> > next-level-cache = <&A35_L2>;
> > + clocks = <&clk IMX_A35_CLK>;
> > + operating-points-v2 = <&a35_0_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > A35_1: cpu@1 {
> > @@ -42,6 +45,9 @@
> > reg = <0x0 0x1>;
> > enable-method = "psci";
> > next-level-cache = <&A35_L2>;
> > + clocks = <&clk IMX_A35_CLK>;
> > + operating-points-v2 = <&a35_0_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > A35_2: cpu@2 {
> > @@ -50,6 +56,9 @@
> > reg = <0x0 0x2>;
> > enable-method = "psci";
> > next-level-cache = <&A35_L2>;
> > + clocks = <&clk IMX_A35_CLK>;
> > + operating-points-v2 = <&a35_0_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > A35_3: cpu@3 {
> > @@ -58,6 +67,9 @@
> > reg = <0x0 0x3>;
> > enable-method = "psci";
> > next-level-cache = <&A35_L2>;
> > + clocks = <&clk IMX_A35_CLK>;
> > + operating-points-v2 = <&a35_0_opp_table>;
> > + #cooling-cells = <2>;
> > };
> >
> > A35_L2: l2-cache0 {
> > @@ -65,6 +77,24 @@
> > };
> > };
> >
> > + a35_0_opp_table: opp-table {
>
> What does the '0' in the label mean?
Looks like the '0' in the label is NOT necessary, we can just use 'a35_opp_table',
do you want me resend the patch to remove '0'?
Anson.
>
> Shawn
>
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-900000000 {
> > + opp-hz = /bits/ 64 <900000000>;
> > + opp-microvolt = <1000000>;
> > + clock-latency-ns = <150000>;
> > + };
> > +
> > + opp-1200000000 {
> > + opp-hz = /bits/ 64 <1200000000>;
> > + opp-microvolt = <1100000>;
> > + clock-latency-ns = <150000>;
> > + opp-suspend;
> > + };
> > + };
> > +
> > gic: interrupt-controller@51a00000 {
> > compatible = "arm,gic-v3";
> > reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> > --
> > 2.7.4
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > [email protected]
> > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flist
> > s.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-
> kernel&data=02%7C
> >
> 01%7Canson.huang%40nxp.com%7Cfe4ff92a639e4739c2a108d69d2b8e12%7
> C686ea1
> >
> d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636869207728398808&sd
> ata=oz%2
> > FPyAki6fkfQZqaSYkjWfo3m8S48sCzpDf2lxDIjKs%3D&reserved=0
On Thu, Feb 28, 2019 at 06:18:30AM +0000, Anson Huang wrote:
> Hi, Shawn
>
> Best Regards!
> Anson Huang
>
> > -----Original Message-----
> > From: Shawn Guo [mailto:[email protected]]
> > Sent: 2019年2月28日 11:19
> > To: Anson Huang <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; Aisheng Dong <[email protected]>; Daniel Baluta
> > <[email protected]>; [email protected]; linux-arm-
> > [email protected]; [email protected]; linux-
> > [email protected]; dl-linux-imx <[email protected]>
> > Subject: Re: [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp
> > table
> >
> > On Tue, Feb 26, 2019 at 05:17:31AM +0000, Anson Huang wrote:
> > > Add i.MX8QXP CPU opp table to support cpufreq.
> > >
> > > Signed-off-by: Anson Huang <[email protected]>
> > > Acked-by: Viresh Kumar <[email protected]>
> >
> > Prefix 'arm64: dts: imx8qxp: ' would already be clear enough. I dropped
> > 'freescale' from there and applied patch.
> >
> > > ---
> > > No changes since V6.
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30
> > > ++++++++++++++++++++++++++++++
> > > 1 file changed, 30 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > index 4c3dd95..41bf0ce 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > @@ -34,6 +34,9 @@
> > > reg = <0x0 0x0>;
> > > enable-method = "psci";
> > > next-level-cache = <&A35_L2>;
> > > + clocks = <&clk IMX_A35_CLK>;
> > > + operating-points-v2 = <&a35_0_opp_table>;
> > > + #cooling-cells = <2>;
> > > };
> > >
> > > A35_1: cpu@1 {
> > > @@ -42,6 +45,9 @@
> > > reg = <0x0 0x1>;
> > > enable-method = "psci";
> > > next-level-cache = <&A35_L2>;
> > > + clocks = <&clk IMX_A35_CLK>;
> > > + operating-points-v2 = <&a35_0_opp_table>;
> > > + #cooling-cells = <2>;
> > > };
> > >
> > > A35_2: cpu@2 {
> > > @@ -50,6 +56,9 @@
> > > reg = <0x0 0x2>;
> > > enable-method = "psci";
> > > next-level-cache = <&A35_L2>;
> > > + clocks = <&clk IMX_A35_CLK>;
> > > + operating-points-v2 = <&a35_0_opp_table>;
> > > + #cooling-cells = <2>;
> > > };
> > >
> > > A35_3: cpu@3 {
> > > @@ -58,6 +67,9 @@
> > > reg = <0x0 0x3>;
> > > enable-method = "psci";
> > > next-level-cache = <&A35_L2>;
> > > + clocks = <&clk IMX_A35_CLK>;
> > > + operating-points-v2 = <&a35_0_opp_table>;
> > > + #cooling-cells = <2>;
> > > };
> > >
> > > A35_L2: l2-cache0 {
> > > @@ -65,6 +77,24 @@
> > > };
> > > };
> > >
> > > + a35_0_opp_table: opp-table {
> >
> > What does the '0' in the label mean?
>
> Looks like the '0' in the label is NOT necessary, we can just use 'a35_opp_table',
> do you want me resend the patch to remove '0'?
No. I just fixed it up and applied the patch.
Shawn