Freescale MMDC (Multi Mode DDR Controller) driver is supported
since i.MX6Q, but not yet documented, this patch adds binding
doc for MMDC module driver.
Signed-off-by: Anson Huang <[email protected]>
---
Changes since V3:
- add i.MX6QP compatible name.
---
.../bindings/memory-controllers/fsl/mmdc.txt | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
new file mode 100644
index 0000000..e4e0b50
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
@@ -0,0 +1,33 @@
+Freescale Multi Mode DDR controller (MMDC)
+
+Required properties :
+- compatible : should be one of following:
+ for i.MX6Q/i.MX6DL:
+ - "fsl,imx6q-mmdc";
+ for i.MX6QP:
+ - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
+ for i.MX6SL:
+ - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
+ for i.MX6SLL:
+ - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
+ for i.MX6SX:
+ - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
+ for i.MX6UL/i.MX6ULL/i.MX6ULZ:
+ - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
+ for i.MX7ULP:
+ - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
+- reg : address and size of MMDC DDR controller registers
+
+Optional properties :
+- clocks : the clock provided by the SoC to access the MMDC registers
+
+Example :
+ mmdc0: memory-controller@21b0000 { /* MMDC0 */
+ compatible = "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
+ };
+
+ mmdc1: memory-controller@21b4000 { /* MMDC1 */
+ reg = <0x021b4000 0x4000>;
+ };
--
2.7.4
i.MX7ULP has a MMDC module to control DDR, it reuses
i.MX6Q's MMDC module, add support for it.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
---
No change since V3.
---
arch/arm/boot/dts/imx7ulp.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index fca6e50..eb349fd 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -286,6 +286,12 @@
status = "disabled";
};
+ memory-controller@40ab0000 {
+ compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x40ab0000 0x1000>;
+ clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
+ };
+
iomuxc1: pinctrl@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
--
2.7.4
On Thu, Feb 28, 2019 at 10:24 PM Anson Huang <[email protected]> wrote:
>
> Freescale MMDC (Multi Mode DDR Controller) driver is supported
> since i.MX6Q, but not yet documented, this patch adds binding
> doc for MMDC module driver.
>
> Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Node name should be generic, so use "memory-controller"
instead of "mmdc" for MMDC node name, also remove "mmdc"
label for platforms with single MMDC node.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
---
No changes since V3.
---
arch/arm/boot/dts/imx6qdl.dtsi | 4 ++--
arch/arm/boot/dts/imx6sl.dtsi | 2 +-
arch/arm/boot/dts/imx6sx.dtsi | 2 +-
arch/arm/boot/dts/imx6ul.dtsi | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index fe17a34..4c7278b 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1129,13 +1129,13 @@
reg = <0x021ac000 0x4000>;
};
- mmdc0: mmdc@21b0000 { /* MMDC0 */
+ mmdc0: memory-controller@21b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
};
- mmdc1: mmdc@21b4000 { /* MMDC1 */
+ mmdc1: memory-controller@21b4000 { /* MMDC1 */
reg = <0x021b4000 0x4000>;
};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 4b4813f..733ea50 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -922,7 +922,7 @@
status = "disabled";
};
- mmdc: mmdc@21b0000 {
+ memory-controller@21b0000 {
compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 5b16e65..df0c595 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -1017,7 +1017,7 @@
status = "disabled";
};
- mmdc: mmdc@21b0000 {
+ memory-controller@21b0000 {
compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 62ed30c..a77bbca 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -914,7 +914,7 @@
status = "disabled";
};
- mmdc: mmdc@21b0000 {
+ memory-controller@21b0000 {
compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
--
2.7.4
On Fri, Mar 01, 2019 at 01:24:18AM +0000, Anson Huang wrote:
> Freescale MMDC (Multi Mode DDR Controller) driver is supported
> since i.MX6Q, but not yet documented, this patch adds binding
> doc for MMDC module driver.
>
> Signed-off-by: Anson Huang <[email protected]>
> ---
> Changes since V3:
> - add i.MX6QP compatible name.
> ---
> .../bindings/memory-controllers/fsl/mmdc.txt | 33 ++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
> new file mode 100644
> index 0000000..e4e0b50
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
> @@ -0,0 +1,33 @@
> +Freescale Multi Mode DDR controller (MMDC)
> +
> +Required properties :
> +- compatible : should be one of following:
> + for i.MX6Q/i.MX6DL:
> + - "fsl,imx6q-mmdc";
> + for i.MX6QP:
> + - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
> + for i.MX6SL:
> + - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
> + for i.MX6SLL:
> + - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
> + for i.MX6SX:
> + - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
> + for i.MX6UL/i.MX6ULL/i.MX6ULZ:
> + - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
> + for i.MX7ULP:
> + - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
> +- reg : address and size of MMDC DDR controller registers
> +
> +Optional properties :
> +- clocks : the clock provided by the SoC to access the MMDC registers
> +
> +Example :
> + mmdc0: memory-controller@21b0000 { /* MMDC0 */
> + compatible = "fsl,imx6q-mmdc";
> + reg = <0x021b0000 0x4000>;
> + clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
> + }
> +
> + mmdc1: memory-controller@21b4000 { /* MMDC1 */
> + reg = <0x021b4000 0x4000>;
What is this node? No compatible here should be considered invalid.
Seems like maybe the 1st node should have 2 register ranges if you want
a single device.
Rob
Hi, Rob
Best Regards!
Anson Huang
> -----Original Message-----
> From: Rob Herring [mailto:[email protected]]
> Sent: 2019??3??12?? 6:53
> To: Anson Huang <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; dl-linux-imx <[email protected]>
> Subject: Re: [PATCH V4 1/3] dt-bindings: memory-controllers: freescale: add
> MMDC binding doc
>
> On Fri, Mar 01, 2019 at 01:24:18AM +0000, Anson Huang wrote:
> > Freescale MMDC (Multi Mode DDR Controller) driver is supported since
> > i.MX6Q, but not yet documented, this patch adds binding doc for MMDC
> > module driver.
> >
> > Signed-off-by: Anson Huang <[email protected]>
> > ---
> > Changes since V3:
> > - add i.MX6QP compatible name.
> > ---
> > .../bindings/memory-controllers/fsl/mmdc.txt | 33
> ++++++++++++++++++++++
> > 1 file changed, 33 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
> > b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt
> > new file mode 100644
> > index 0000000..e4e0b50
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-
> controllers/fsl/mmdc.tx
> > +++ t
> > @@ -0,0 +1,33 @@
> > +Freescale Multi Mode DDR controller (MMDC)
> > +
> > +Required properties :
> > +- compatible : should be one of following:
> > + for i.MX6Q/i.MX6DL:
> > + - "fsl,imx6q-mmdc";
> > + for i.MX6QP:
> > + - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
> > + for i.MX6SL:
> > + - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
> > + for i.MX6SLL:
> > + - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
> > + for i.MX6SX:
> > + - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
> > + for i.MX6UL/i.MX6ULL/i.MX6ULZ:
> > + - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
> > + for i.MX7ULP:
> > + - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
> > +- reg : address and size of MMDC DDR controller registers
> > +
> > +Optional properties :
> > +- clocks : the clock provided by the SoC to access the MMDC registers
> > +
> > +Example :
> > + mmdc0: memory-controller@21b0000 { /* MMDC0 */
> > + compatible = "fsl,imx6q-mmdc";
> > + reg = <0x021b0000 0x4000>;
> > + clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
> > + }
> > +
> > + mmdc1: memory-controller@21b4000 { /* MMDC1 */
> > + reg = <0x021b4000 0x4000>;
>
> What is this node? No compatible here should be considered invalid.
>
> Seems like maybe the 1st node should have 2 register ranges if you want a
> single device.
I think mmdc1's compatible is missed from beginning, I will add a separate patch for it
and make its status as disabled by default, since most of i.MX6 platforms ONLY uses
mmdc0, ONLY very few special platforms use dual channels.
Thanks,
Anson.
>
> Rob