Hi,
A64 IR support series[1] pointed out that an A31 bindings should be
introduced.
This series introduce the A31 compatible bindings, then switch it on
the already existing board.
Finally introduce A64 and H6 support.
I didn't enable the IR on other H6 boards as Ondrej reported an issue
on his board[2].
Regards,
Clément
[1] https://lore.kernel.org/patchwork/patch/1031390/#1221464
[2] https://lkml.org/lkml/2019/5/27/321
Changes since v2:
- Disable IR for other H6 boards
- Split DTS patch for H3/H5
- Introduce IR quirks
Changes since v1:
- Document reset lines as required since A31
- Explain the memory mapping difference in commit log
- Fix misspelling "Allwiner" to "Allwinner"
Clément Péron (10):
dt-bindings: media: sunxi-ir: add A31 compatible
media: rc: Introduce sunxi_ir_quirks
media: rc: sunxi: Add A31 compatible
ARM: dts: sunxi: Prefer A31 bindings for IR
ARM: dts: sunxi: Prefer A31 bindings for IR
dt-bindings: media: sunxi-ir: Add A64 compatible
dt-bindings: media: sunxi-ir: Add H6 compatible
arm64: dts: allwinner: h6: Add IR receiver node
arm64: dts: allwinner: h6: Enable IR on Beelink GS1
arm64: defconfig: enable IR SUNXI option
Igors Makejevs (1):
arm64: dts: allwinner: a64: Add IR node
Jernej Skrabec (1):
arm64: dts: allwinner: a64: Enable IR on Orange Pi Win
.../devicetree/bindings/media/sunxi-ir.txt | 11 ++-
arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
.../dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 +++++
.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++
arch/arm64/configs/defconfig | 1 +
drivers/media/rc/sunxi-cir.c | 70 +++++++++++++++----
11 files changed, 115 insertions(+), 20 deletions(-)
--
2.20.1
From: Jernej Skrabec <[email protected]>
OrangePi Win board contains IR receiver. Enable it.
Signed-off-by: Jernej Skrabec <[email protected]>
Signed-off-by: Clément Péron <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index 510f661229dc..e05191b71adf 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -180,6 +180,10 @@
status = "okay";
};
+&r_ir {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
--
2.20.1
Allwinner H6 IR is similar to A31 and can use same driver.
Add support for it.
Signed-off-by: Clément Péron <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 16c5c3d0fd81..649cbdfe452e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -647,6 +647,25 @@
pins = "PL0", "PL1";
function = "s_i2c";
};
+
+ r_ir_rx_pin: r-ir-rx-pin {
+ pins = "PL9";
+ function = "s_cir_rx";
+ };
+ };
+
+ r_ir: ir@7040000 {
+ compatible = "allwinner,sun50i-h6-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x07040000 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_IR>,
+ <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_R_APB1_IR>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
};
r_i2c: i2c@7081400 {
--
2.20.1
Since A31, memory mapping of the IR driver has changed.
Prefer the A31 bindings instead of A13.
Signed-off-by: Clément Péron <[email protected]>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 84977d4eb97a..f0f5ba349c1b 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -822,7 +822,7 @@
};
ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;
--
2.20.1
Since A31, memory mapping of the IR driver has changed.
Prefer the A31 bindings instead of A13.
Signed-off-by: Clément Péron <[email protected]>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index c04efad81bbc..110622b30796 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -1351,7 +1351,7 @@
};
ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
clocks = <&apb0_gates 1>, <&ir_clk>;
clock-names = "apb", "ir";
resets = <&apb0_rst 1>;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 392b0cabbf0d..8d603f3309f2 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1067,7 +1067,7 @@
r_cir: ir@1f02000 {
compatible = "allwinner,sun8i-a83t-ir",
- "allwinner,sun5i-a13-ir";
+ "allwinner,sun6i-a31-ir";
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 0c1eec9000e3..310cd972ee5b 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -1167,7 +1167,7 @@
};
r_ir: ir@8002000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&r_ir_pins>;
--
2.20.1
There are some minor differences between A31 and A64 driver.
But A31 IR driver is compatible with A64.
Signed-off-by: Clément Péron <[email protected]>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 2e59a32a7e33..1dd287a4ab3a 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -5,6 +5,7 @@ Required properties:
"allwinner,sun4i-a10-ir"
"allwinner,sun5i-a13-ir"
"allwinner,sun6i-a31-ir"
+ "allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir"
- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;
--
2.20.1
This driver is used in various Allwinner SoC with different configuration.
Introduce a quirks struct to know the fifo size and if a reset is required.
Signed-off-by: Clément Péron <[email protected]>
---
drivers/media/rc/sunxi-cir.c | 61 +++++++++++++++++++++++++++---------
1 file changed, 47 insertions(+), 14 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 307e44714ea0..d02dcb6fd0a5 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -81,6 +81,17 @@
/* Time after which device stops sending data in ms */
#define SUNXI_IR_TIMEOUT 120
+/**
+ * struct sunxi_ir_quirks - Differences between SoC variants.
+ *
+ * @has_reset: SoC needs reset deasserted.
+ * @fifo_size: size of the fifo.
+ */
+struct sunxi_ir_quirks {
+ bool has_reset;
+ int fifo_size;
+};
+
struct sunxi_ir {
spinlock_t ir_lock;
struct rc_dev *rc;
@@ -143,6 +154,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *dn = dev->of_node;
+ const struct sunxi_ir_quirks *quirks;
struct resource *res;
struct sunxi_ir *ir;
u32 b_clk_freq = SUNXI_IR_BASE_CLK;
@@ -151,12 +163,15 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (!ir)
return -ENOMEM;
+ quirks = of_device_get_match_data(&pdev->dev);
+ if (quirks == NULL) {
+ dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
+ return -ENODEV;
+ }
+
spin_lock_init(&ir->ir_lock);
- if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
- ir->fifo_size = 64;
- else
- ir->fifo_size = 16;
+ ir->fifo_size = quirks->fifo_size;
/* Clock */
ir->apb_clk = devm_clk_get(dev, "apb");
@@ -173,13 +188,15 @@ static int sunxi_ir_probe(struct platform_device *pdev)
/* Base clock frequency (optional) */
of_property_read_u32(dn, "clock-frequency", &b_clk_freq);
- /* Reset (optional) */
- ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
- if (IS_ERR(ir->rst))
- return PTR_ERR(ir->rst);
- ret = reset_control_deassert(ir->rst);
- if (ret)
- return ret;
+ /* Reset */
+ if (quirks->has_reset) {
+ ir->rst = devm_reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(ir->rst))
+ return PTR_ERR(ir->rst);
+ ret = reset_control_deassert(ir->rst);
+ if (ret)
+ return ret;
+ }
ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
@@ -316,10 +333,26 @@ static int sunxi_ir_remove(struct platform_device *pdev)
return 0;
}
+static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = {
+ .has_reset = false,
+ .fifo_size = 16,
+};
+
+static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
+ .has_reset = false,
+ .fifo_size = 64,
+};
+
static const struct of_device_id sunxi_ir_match[] = {
- { .compatible = "allwinner,sun4i-a10-ir", },
- { .compatible = "allwinner,sun5i-a13-ir", },
- {},
+ {
+ .compatible = "allwinner,sun4i-a10-ir",
+ .data = &sun4i_a10_ir_quirks,
+ },
+ {
+ .compatible = "allwinner,sun5i-a13-ir",
+ .data = &sun5i_a13_ir_quirks,
+ },
+ {}
};
MODULE_DEVICE_TABLE(of, sunxi_ir_match);
--
2.20.1
Allwinner A31 has introduced a new memory mapping and a
reset line.
The difference in memory mapping are :
- In the configure register there is a new sample bit
and Allwinner has introduced the active threshold feature.
- In the status register a new STAT bit is present.
Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
and on new SoCs like A64/H6.
This is actually not an issue as these bits are togglable and new
SoCs have a dedicated bindings.
Introduce this bindings to make a difference since this generation.
And declare the reset line required since A31.
Signed-off-by: Clément Péron <[email protected]>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 278098987edb..2e59a32a7e33 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -1,16 +1,21 @@
Device-Tree bindings for SUNXI IR controller found in sunXi SoC family
Required properties:
-- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
+- compatible :
+ "allwinner,sun4i-a10-ir"
+ "allwinner,sun5i-a13-ir"
+ "allwinner,sun6i-a31-ir"
- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;
- interrupts : should contain IR IRQ number;
- reg : should contain IO map address for IR.
+Required properties since A31:
+- resets : phandle + reset specifier pair
+
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
-- resets : phandle + reset specifier pair
- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
if missing.
--
2.20.1
On Tue, May 28, 2019 at 06:14:28PM +0200, Cl?ment P?ron wrote:
> Hi,
>
> A64 IR support series[1] pointed out that an A31 bindings should be
> introduced.
>
> This series introduce the A31 compatible bindings, then switch it on
> the already existing board.
>
> Finally introduce A64 and H6 support.
>
> I didn't enable the IR on other H6 boards as Ondrej reported an issue
> on his board[2].
For the whole series:
Acked-by: Sean Young <[email protected]>
>
> Regards,
> Cl?ment
>
> [1] https://lore.kernel.org/patchwork/patch/1031390/#1221464
> [2] https://lkml.org/lkml/2019/5/27/321
>
> Changes since v2:
> - Disable IR for other H6 boards
> - Split DTS patch for H3/H5
> - Introduce IR quirks
>
> Changes since v1:
> - Document reset lines as required since A31
> - Explain the memory mapping difference in commit log
> - Fix misspelling "Allwiner" to "Allwinner"
>
> Cl?ment P?ron (10):
> dt-bindings: media: sunxi-ir: add A31 compatible
> media: rc: Introduce sunxi_ir_quirks
> media: rc: sunxi: Add A31 compatible
> ARM: dts: sunxi: Prefer A31 bindings for IR
> ARM: dts: sunxi: Prefer A31 bindings for IR
> dt-bindings: media: sunxi-ir: Add A64 compatible
> dt-bindings: media: sunxi-ir: Add H6 compatible
> arm64: dts: allwinner: h6: Add IR receiver node
> arm64: dts: allwinner: h6: Enable IR on Beelink GS1
> arm64: defconfig: enable IR SUNXI option
>
> Igors Makejevs (1):
> arm64: dts: allwinner: a64: Add IR node
>
> Jernej Skrabec (1):
> arm64: dts: allwinner: a64: Enable IR on Orange Pi Win
>
> .../devicetree/bindings/media/sunxi-ir.txt | 11 ++-
> arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
> arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
> arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
> .../dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 +++++
> .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++
> arch/arm64/configs/defconfig | 1 +
> drivers/media/rc/sunxi-cir.c | 70 +++++++++++++++----
> 11 files changed, 115 insertions(+), 20 deletions(-)
>
> --
> 2.20.1
Hello Cl?ment,
On Tue, May 28, 2019 at 06:14:38PM +0200, Cl?ment P?ron wrote:
> Allwinner H6 IR is similar to A31 and can use same driver.
>
> Add support for it.
>
> Signed-off-by: Cl?ment P?ron <[email protected]>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 16c5c3d0fd81..649cbdfe452e 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -647,6 +647,25 @@
> pins = "PL0", "PL1";
> function = "s_i2c";
> };
> +
> + r_ir_rx_pin: r-ir-rx-pin {
> + pins = "PL9";
> + function = "s_cir_rx";
> + };
> + };
> +
> + r_ir: ir@7040000 {
> + compatible = "allwinner,sun50i-h6-ir",
> + "allwinner,sun6i-a31-ir";
> + reg = <0x07040000 0x400>;
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB1_IR>,
> + <&r_ccu CLK_IR>;
> + clock-names = "apb", "ir";
> + resets = <&r_ccu RST_R_APB1_IR>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_ir_rx_pin>;
> + status = "disabled";
> };
Please make a comment here, that this is known broken on some boards and may
result IRQ flood if enabled. Otherwise noone will know.
thanks,
o.
> r_i2c: i2c@7081400 {
> --
> 2.20.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Ondrej,
On Thu, 30 May 2019 at 16:55, Ondřej Jirman <[email protected]> wrote:
>
> Hello Clément,
>
> On Tue, May 28, 2019 at 06:14:38PM +0200, Clément Péron wrote:
> > Allwinner H6 IR is similar to A31 and can use same driver.
> >
> > Add support for it.
> >
> > Signed-off-by: Clément Péron <[email protected]>
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index 16c5c3d0fd81..649cbdfe452e 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -647,6 +647,25 @@
> > pins = "PL0", "PL1";
> > function = "s_i2c";
> > };
> > +
> > + r_ir_rx_pin: r-ir-rx-pin {
> > + pins = "PL9";
> > + function = "s_cir_rx";
> > + };
> > + };
> > +
> > + r_ir: ir@7040000 {
> > + compatible = "allwinner,sun50i-h6-ir",
> > + "allwinner,sun6i-a31-ir";
> > + reg = <0x07040000 0x400>;
> > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&r_ccu CLK_R_APB1_IR>,
> > + <&r_ccu CLK_IR>;
> > + clock-names = "apb", "ir";
> > + resets = <&r_ccu RST_R_APB1_IR>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&r_ir_rx_pin>;
> > + status = "disabled";
> > };
>
> Please make a comment here, that this is known broken on some boards and may
> result IRQ flood if enabled. Otherwise noone will know.
I'm planning to send a v4 next week with the IRQ_NONE return as Maxime
suggested it.
https://github.com/clementperon/linux/tree/h6_ir_v4
But maybe we could also use the bit 5 of the IRQ status.
Regards, Clement
>
> thanks,
> o.
>
> > r_i2c: i2c@7081400 {
> > --
> > 2.20.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hello Clément,
On Fri, May 31, 2019 at 12:25:32AM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Thu, 30 May 2019 at 16:55, Ondřej Jirman <[email protected]> wrote:
> >
> > Hello Clément,
> >
> > On Tue, May 28, 2019 at 06:14:38PM +0200, Clément Péron wrote:
> > > Allwinner H6 IR is similar to A31 and can use same driver.
> > >
> > > Add support for it.
> > >
> > > Signed-off-by: Clément Péron <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > index 16c5c3d0fd81..649cbdfe452e 100644
> > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > @@ -647,6 +647,25 @@
> > > pins = "PL0", "PL1";
> > > function = "s_i2c";
> > > };
> > > +
> > > + r_ir_rx_pin: r-ir-rx-pin {
> > > + pins = "PL9";
> > > + function = "s_cir_rx";
> > > + };
> > > + };
> > > +
> > > + r_ir: ir@7040000 {
> > > + compatible = "allwinner,sun50i-h6-ir",
> > > + "allwinner,sun6i-a31-ir";
> > > + reg = <0x07040000 0x400>;
> > > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&r_ccu CLK_R_APB1_IR>,
> > > + <&r_ccu CLK_IR>;
> > > + clock-names = "apb", "ir";
> > > + resets = <&r_ccu RST_R_APB1_IR>;
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&r_ir_rx_pin>;
> > > + status = "disabled";
> > > };
> >
> > Please make a comment here, that this is known broken on some boards and may
> > result IRQ flood if enabled. Otherwise noone will know.
>
> I'm planning to send a v4 next week with the IRQ_NONE return as Maxime
> suggested it.
> https://github.com/clementperon/linux/tree/h6_ir_v4
>
> But maybe we could also use the bit 5 of the IRQ status.
Thanks, that's nice, but that will not make the HW work. That will just disable
it. The comment is still necessary.
thank you,
o.
> Regards, Clement
>
> >
> > thanks,
> > o.
> >
> > > r_i2c: i2c@7081400 {
> > > --
> > > 2.20.1
> > >
> > >
> > > _______________________________________________
> > > linux-arm-kernel mailing list
> > > [email protected]
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to [email protected].
> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAJiuCce7nHSktVsDKcR8GLRpD3WrN5yP3Nb_Hbu_Q9NjUQbSMw%40mail.gmail.com.
> For more options, visit https://groups.google.com/d/optout.
Hi Ondrej,
On Fri, 31 May 2019 at 14:46, Ondřej Jirman <[email protected]> wrote:
>
> Hello Clément,
>
> On Fri, May 31, 2019 at 12:25:32AM +0200, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Thu, 30 May 2019 at 16:55, Ondřej Jirman <[email protected]> wrote:
> > >
> > > Hello Clément,
> > >
> > > On Tue, May 28, 2019 at 06:14:38PM +0200, Clément Péron wrote:
> > > > Allwinner H6 IR is similar to A31 and can use same driver.
> > > >
> > > > Add support for it.
> > > >
> > > > Signed-off-by: Clément Péron <[email protected]>
> > > > ---
> > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
> > > > 1 file changed, 19 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > index 16c5c3d0fd81..649cbdfe452e 100644
> > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > @@ -647,6 +647,25 @@
> > > > pins = "PL0", "PL1";
> > > > function = "s_i2c";
> > > > };
> > > > +
> > > > + r_ir_rx_pin: r-ir-rx-pin {
> > > > + pins = "PL9";
> > > > + function = "s_cir_rx";
> > > > + };
> > > > + };
> > > > +
> > > > + r_ir: ir@7040000 {
> > > > + compatible = "allwinner,sun50i-h6-ir",
> > > > + "allwinner,sun6i-a31-ir";
> > > > + reg = <0x07040000 0x400>;
> > > > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&r_ccu CLK_R_APB1_IR>,
> > > > + <&r_ccu CLK_IR>;
> > > > + clock-names = "apb", "ir";
> > > > + resets = <&r_ccu RST_R_APB1_IR>;
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&r_ir_rx_pin>;
> > > > + status = "disabled";
> > > > };
> > >
> > > Please make a comment here, that this is known broken on some boards and may
> > > result IRQ flood if enabled. Otherwise noone will know.
> >
> > I'm planning to send a v4 next week with the IRQ_NONE return as Maxime
> > suggested it.
> > https://github.com/clementperon/linux/tree/h6_ir_v4
> >
> > But maybe we could also use the bit 5 of the IRQ status.
>
> Thanks, that's nice, but that will not make the HW work. That will just disable
> it. The comment is still necessary.
I have pushed a new version on my github.
https://github.com/clementperon/linux/commits/h6_ir_v4
I will submit it, if you are ok with it.
Thanks,
Clément
>
> thank you,
> o.
>
> > Regards, Clement
> >
> > >
> > > thanks,
> > > o.
> > >
> > > > r_i2c: i2c@7081400 {
> > > > --
> > > > 2.20.1
> > > >
> > > >
> > > > _______________________________________________
> > > > linux-arm-kernel mailing list
> > > > [email protected]
> > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >
> > --
> > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an email to [email protected].
> > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAJiuCce7nHSktVsDKcR8GLRpD3WrN5yP3Nb_Hbu_Q9NjUQbSMw%40mail.gmail.com.
> > For more options, visit https://groups.google.com/d/optout.
Hi Clément,
On Mon, Jun 03, 2019 at 09:58:23PM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Fri, 31 May 2019 at 14:46, Ondřej Jirman <[email protected]> wrote:
> >
> > Hello Clément,
> >
> > On Fri, May 31, 2019 at 12:25:32AM +0200, Clément Péron wrote:
> > > Hi Ondrej,
> > >
> > > On Thu, 30 May 2019 at 16:55, Ondřej Jirman <[email protected]> wrote:
> > > >
> > > > Hello Clément,
> > > >
> > > > On Tue, May 28, 2019 at 06:14:38PM +0200, Clément Péron wrote:
> > > > > Allwinner H6 IR is similar to A31 and can use same driver.
> > > > >
> > > > > Add support for it.
> > > > >
> > > > > Signed-off-by: Clément Péron <[email protected]>
> > > > > ---
> > > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
> > > > > 1 file changed, 19 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > index 16c5c3d0fd81..649cbdfe452e 100644
> > > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > @@ -647,6 +647,25 @@
> > > > > pins = "PL0", "PL1";
> > > > > function = "s_i2c";
> > > > > };
> > > > > +
> > > > > + r_ir_rx_pin: r-ir-rx-pin {
> > > > > + pins = "PL9";
> > > > > + function = "s_cir_rx";
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + r_ir: ir@7040000 {
> > > > > + compatible = "allwinner,sun50i-h6-ir",
> > > > > + "allwinner,sun6i-a31-ir";
> > > > > + reg = <0x07040000 0x400>;
> > > > > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > > > > + clocks = <&r_ccu CLK_R_APB1_IR>,
> > > > > + <&r_ccu CLK_IR>;
> > > > > + clock-names = "apb", "ir";
> > > > > + resets = <&r_ccu RST_R_APB1_IR>;
> > > > > + pinctrl-names = "default";
> > > > > + pinctrl-0 = <&r_ir_rx_pin>;
> > > > > + status = "disabled";
> > > > > };
> > > >
> > > > Please make a comment here, that this is known broken on some boards and may
> > > > result IRQ flood if enabled. Otherwise noone will know.
> > >
> > > I'm planning to send a v4 next week with the IRQ_NONE return as Maxime
> > > suggested it.
> > > https://github.com/clementperon/linux/tree/h6_ir_v4
> > >
> > > But maybe we could also use the bit 5 of the IRQ status.
> >
> > Thanks, that's nice, but that will not make the HW work. That will just disable
> > it. The comment is still necessary.
> I have pushed a new version on my github.
> https://github.com/clementperon/linux/commits/h6_ir_v4
>
> I will submit it, if you are ok with it.
the changes make it worse. Console is flooded with "Temporarily disable IRQ"
and other symptoms are the same as I described before. Interrupts are not
disabled in a any reasonable time. (I've waited for more > 5mins already.)
You probably need to disable interrupts right away, not wait for 100k failures.
thank you and regards,
o.
> Thanks,
> Clément
>
> >
> > thank you,
> > o.
> >
> > > Regards, Clement
> > >
> > > >
> > > > thanks,
> > > > o.
> > > >
> > > > > r_i2c: i2c@7081400 {
> > > > > --
> > > > > 2.20.1
> > > > >
> > > > >
> > > > > _______________________________________________
> > > > > linux-arm-kernel mailing list
> > > > > [email protected]
> > > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > >
> > > --
> > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > > To unsubscribe from this group and stop receiving emails from it, send an email to [email protected].
> > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAJiuCce7nHSktVsDKcR8GLRpD3WrN5yP3Nb_Hbu_Q9NjUQbSMw%40mail.gmail.com.
> > > For more options, visit https://groups.google.com/d/optout.
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Clément,
On Tue, Jun 04, 2019 at 02:33:55PM +0200, verejna wrote:
> Hi Clément,
>
> On Mon, Jun 03, 2019 at 09:58:23PM +0200, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Fri, 31 May 2019 at 14:46, Ondřej Jirman <[email protected]> wrote:
> > >
> > > Hello Clément,
> > >
> > > On Fri, May 31, 2019 at 12:25:32AM +0200, Clément Péron wrote:
> > > > Hi Ondrej,
> > > >
> > > > On Thu, 30 May 2019 at 16:55, Ondřej Jirman <[email protected]> wrote:
> > > > >
> > > > > Hello Clément,
> > > > >
> > > > > On Tue, May 28, 2019 at 06:14:38PM +0200, Clément Péron wrote:
> > > > > > Allwinner H6 IR is similar to A31 and can use same driver.
> > > > > >
> > > > > > Add support for it.
> > > > > >
> > > > > > Signed-off-by: Clément Péron <[email protected]>
> > > > > > ---
> > > > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
> > > > > > 1 file changed, 19 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > index 16c5c3d0fd81..649cbdfe452e 100644
> > > > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > @@ -647,6 +647,25 @@
> > > > > > pins = "PL0", "PL1";
> > > > > > function = "s_i2c";
> > > > > > };
> > > > > > +
> > > > > > + r_ir_rx_pin: r-ir-rx-pin {
> > > > > > + pins = "PL9";
> > > > > > + function = "s_cir_rx";
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + r_ir: ir@7040000 {
> > > > > > + compatible = "allwinner,sun50i-h6-ir",
> > > > > > + "allwinner,sun6i-a31-ir";
> > > > > > + reg = <0x07040000 0x400>;
> > > > > > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&r_ccu CLK_R_APB1_IR>,
> > > > > > + <&r_ccu CLK_IR>;
> > > > > > + clock-names = "apb", "ir";
> > > > > > + resets = <&r_ccu RST_R_APB1_IR>;
> > > > > > + pinctrl-names = "default";
> > > > > > + pinctrl-0 = <&r_ir_rx_pin>;
> > > > > > + status = "disabled";
> > > > > > };
> > > > >
> > > > > Please make a comment here, that this is known broken on some boards and may
> > > > > result IRQ flood if enabled. Otherwise noone will know.
> > > >
> > > > I'm planning to send a v4 next week with the IRQ_NONE return as Maxime
> > > > suggested it.
> > > > https://github.com/clementperon/linux/tree/h6_ir_v4
> > > >
> > > > But maybe we could also use the bit 5 of the IRQ status.
> > >
> > > Thanks, that's nice, but that will not make the HW work. That will just disable
> > > it. The comment is still necessary.
> > I have pushed a new version on my github.
> > https://github.com/clementperon/linux/commits/h6_ir_v4
> >
> > I will submit it, if you are ok with it.
>
> the changes make it worse. Console is flooded with "Temporarily disable IRQ"
> and other symptoms are the same as I described before. Interrupts are not
> disabled in a any reasonable time. (I've waited for more > 5mins already.)
>
> You probably need to disable interrupts right away, not wait for 100k failures.
Hmm, this is what the registers look like post-probe:
R_CIR:
0x07040000 : 00000030
0x07040004 : 00000030
0x07040008 : 00000030
0x0704000c : 00000030
0x07040010 : 00000030
0x07040014 : 00000030
0x07040018 : 00000030
0x0704001c : 00000030
0x07040020 : 00000030
0x07040024 : 00000030
0x07040028 : 00000030
0x0704002c : 00000030
0x07040030 : 00000030
0x07040034 : 00000030
0x07040038 : 00000030
0x0704003c : 00000030
0x07040040 : 00000030
0x07040044 : 00000030
0x07040048 : 00000030
0x0704004c : 00000030
0x07040050 : 00000030
0x07040054 : 00000030
0x07040058 : 00000030
0x0704005c : 00000030
0x07040060 : 00000030
0x07040064 : 00000030
0x07040068 : 00000030
0x0704006c : 00000030
0x07040070 : 00000030
0x07040074 : 00000030
0x07040078 : 00000030
0x0704007c : 00000030
0x07040080 : 00000030
0x07040084 : 00000030
0x07040088 : 00000030
0x0704008c : 00000030
0x07040090 : 00000030
0x07040094 : 00000030
0x07040098 : 00000030
0x0704009c : 00000030
0x070400a0 : 00000030
0x070400a4 : 00000030
0x070400a8 : 00000030
0x070400ac : 00000030
0x070400b0 : 00000030
0x070400b4 : 00000030
0x070400b8 : 00000030
0x070400bc : 00000030
0x070400c0 : 00000030
0x070400c4 : 00000030
0x070400c8 : 00000030
0x070400cc : 00000030
0x070400d0 : 00000030
0x070400d4 : 00000030
0x070400d8 : 00000030
0x070400dc : 00000030
0x070400e0 : 00000030
0x070400e4 : 00000030
0x070400e8 : 00000030
0x070400ec : 00000030
0x070400f0 : 00000030
0x070400f4 : 00000030
0x070400f8 : 00000030
0x070400fc : 00000030
Clearly not right. It's just the R_CIR module, other modules have normal values.
I've checked:
0x070101c0 : 81000002
(IR clock config register)
0x070101cc : 00010000
(IR reset/bus clk gate reg)
static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
r_mod0_default_parents, 0x1c0,
0, 5, /* M */
8, 2, /* P */
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
0x1cc, BIT(0), 0);
[RST_R_APB1_IR] = { 0x1cc, BIT(16) },
So parent clock seems to be OK. But gate clock is not enabled, so the bus
is not working.
And look at this!!:
static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
0x1cc, BIT(0), 0);
So, it's wrong w1 gate config!
You can drop your changes, because I've probbably found the root cause.
regards,
o.
> thank you and regards,
> o.
>
> > Thanks,
> > Clément
> >
> > >
> > > thank you,
> > > o.
> > >
> > > > Regards, Clement
> > > >
> > > > >
> > > > > thanks,
> > > > > o.
> > > > >
> > > > > > r_i2c: i2c@7081400 {
> > > > > > --
> > > > > > 2.20.1
> > > > > >
> > > > > >
> > > > > > _______________________________________________
> > > > > > linux-arm-kernel mailing list
> > > > > > [email protected]
> > > > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > > >
> > > > --
> > > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > > > To unsubscribe from this group and stop receiving emails from it, send an email to [email protected].
> > > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAJiuCce7nHSktVsDKcR8GLRpD3WrN5yP3Nb_Hbu_Q9NjUQbSMw%40mail.gmail.com.
> > > > For more options, visit https://groups.google.com/d/optout.
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Ondrej,
On Tue, 4 Jun 2019 at 16:47, Ondřej Jirman <[email protected]> wrote:
>
> Hi Clément,
>
> On Tue, Jun 04, 2019 at 02:33:55PM +0200, verejna wrote:
> > Hi Clément,
> >
> > On Mon, Jun 03, 2019 at 09:58:23PM +0200, Clément Péron wrote:
> > > Hi Ondrej,
> > >
> > > On Fri, 31 May 2019 at 14:46, Ondřej Jirman <[email protected]> wrote:
> > > >
> > > > Hello Clément,
> > > >
> > > > On Fri, May 31, 2019 at 12:25:32AM +0200, Clément Péron wrote:
> > > > > Hi Ondrej,
> > > > >
> > > > > On Thu, 30 May 2019 at 16:55, Ondřej Jirman <[email protected]> wrote:
> > > > > >
> > > > > > Hello Clément,
> > > > > >
> > > > > > On Tue, May 28, 2019 at 06:14:38PM +0200, Clément Péron wrote:
> > > > > > > Allwinner H6 IR is similar to A31 and can use same driver.
> > > > > > >
> > > > > > > Add support for it.
> > > > > > >
> > > > > > > Signed-off-by: Clément Péron <[email protected]>
> > > > > > > ---
> > > > > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
> > > > > > > 1 file changed, 19 insertions(+)
> > > > > > >
> > > > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > index 16c5c3d0fd81..649cbdfe452e 100644
> > > > > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > @@ -647,6 +647,25 @@
> > > > > > > pins = "PL0", "PL1";
> > > > > > > function = "s_i2c";
> > > > > > > };
> > > > > > > +
> > > > > > > + r_ir_rx_pin: r-ir-rx-pin {
> > > > > > > + pins = "PL9";
> > > > > > > + function = "s_cir_rx";
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > + r_ir: ir@7040000 {
> > > > > > > + compatible = "allwinner,sun50i-h6-ir",
> > > > > > > + "allwinner,sun6i-a31-ir";
> > > > > > > + reg = <0x07040000 0x400>;
> > > > > > > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&r_ccu CLK_R_APB1_IR>,
> > > > > > > + <&r_ccu CLK_IR>;
> > > > > > > + clock-names = "apb", "ir";
> > > > > > > + resets = <&r_ccu RST_R_APB1_IR>;
> > > > > > > + pinctrl-names = "default";
> > > > > > > + pinctrl-0 = <&r_ir_rx_pin>;
> > > > > > > + status = "disabled";
> > > > > > > };
> > > > > >
> > > > > > Please make a comment here, that this is known broken on some boards and may
> > > > > > result IRQ flood if enabled. Otherwise noone will know.
> > > > >
> > > > > I'm planning to send a v4 next week with the IRQ_NONE return as Maxime
> > > > > suggested it.
> > > > > https://github.com/clementperon/linux/tree/h6_ir_v4
> > > > >
> > > > > But maybe we could also use the bit 5 of the IRQ status.
> > > >
> > > > Thanks, that's nice, but that will not make the HW work. That will just disable
> > > > it. The comment is still necessary.
> > > I have pushed a new version on my github.
> > > https://github.com/clementperon/linux/commits/h6_ir_v4
> > >
> > > I will submit it, if you are ok with it.
> >
> > the changes make it worse. Console is flooded with "Temporarily disable IRQ"
> > and other symptoms are the same as I described before. Interrupts are not
> > disabled in a any reasonable time. (I've waited for more > 5mins already.)
> >
> > You probably need to disable interrupts right away, not wait for 100k failures.
>
> Hmm, this is what the registers look like post-probe:
>
> R_CIR:
> 0x07040000 : 00000030
> 0x07040004 : 00000030
> 0x07040008 : 00000030
> 0x0704000c : 00000030
> 0x07040010 : 00000030
> 0x07040014 : 00000030
> 0x07040018 : 00000030
> 0x0704001c : 00000030
> 0x07040020 : 00000030
> 0x07040024 : 00000030
> 0x07040028 : 00000030
> 0x0704002c : 00000030
> 0x07040030 : 00000030
> 0x07040034 : 00000030
> 0x07040038 : 00000030
> 0x0704003c : 00000030
> 0x07040040 : 00000030
> 0x07040044 : 00000030
> 0x07040048 : 00000030
> 0x0704004c : 00000030
> 0x07040050 : 00000030
> 0x07040054 : 00000030
> 0x07040058 : 00000030
> 0x0704005c : 00000030
> 0x07040060 : 00000030
> 0x07040064 : 00000030
> 0x07040068 : 00000030
> 0x0704006c : 00000030
> 0x07040070 : 00000030
> 0x07040074 : 00000030
> 0x07040078 : 00000030
> 0x0704007c : 00000030
> 0x07040080 : 00000030
> 0x07040084 : 00000030
> 0x07040088 : 00000030
> 0x0704008c : 00000030
> 0x07040090 : 00000030
> 0x07040094 : 00000030
> 0x07040098 : 00000030
> 0x0704009c : 00000030
> 0x070400a0 : 00000030
> 0x070400a4 : 00000030
> 0x070400a8 : 00000030
> 0x070400ac : 00000030
> 0x070400b0 : 00000030
> 0x070400b4 : 00000030
> 0x070400b8 : 00000030
> 0x070400bc : 00000030
> 0x070400c0 : 00000030
> 0x070400c4 : 00000030
> 0x070400c8 : 00000030
> 0x070400cc : 00000030
> 0x070400d0 : 00000030
> 0x070400d4 : 00000030
> 0x070400d8 : 00000030
> 0x070400dc : 00000030
> 0x070400e0 : 00000030
> 0x070400e4 : 00000030
> 0x070400e8 : 00000030
> 0x070400ec : 00000030
> 0x070400f0 : 00000030
> 0x070400f4 : 00000030
> 0x070400f8 : 00000030
> 0x070400fc : 00000030
>
> Clearly not right. It's just the R_CIR module, other modules have normal values.
>
> I've checked:
> 0x070101c0 : 81000002
> (IR clock config register)
> 0x070101cc : 00010000
> (IR reset/bus clk gate reg)
>
> static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
> r_mod0_default_parents, 0x1c0,
> 0, 5, /* M */
> 8, 2, /* P */
> 24, 1, /* mux */
> BIT(31), /* gate */
> 0);
>
> static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> 0x1cc, BIT(0), 0);
>
> [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
>
> So parent clock seems to be OK. But gate clock is not enabled, so the bus
> is not working.
>
> And look at this!!:
>
> static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> 0x1cc, BIT(0), 0);
> static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> 0x1cc, BIT(0), 0);
>
> So, it's wrong w1 gate config!
>
> You can drop your changes, because I've probbably found the root cause.
Nice to see that you have found the issue, but I don't understand why
It's working on my board on not on yours.
Regards,
Clément
>
> regards,
> o.
>
> > thank you and regards,
> > o.
> >
> > > Thanks,
> > > Clément
> > >
> > > >
> > > > thank you,
> > > > o.
> > > >
> > > > > Regards, Clement
> > > > >
> > > > > >
> > > > > > thanks,
> > > > > > o.
> > > > > >
> > > > > > > r_i2c: i2c@7081400 {
> > > > > > > --
> > > > > > > 2.20.1
> > > > > > >
> > > > > > >
> > > > > > > _______________________________________________
> > > > > > > linux-arm-kernel mailing list
> > > > > > > [email protected]
> > > > > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > > > >
> > > > > --
> > > > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > > > > To unsubscribe from this group and stop receiving emails from it, send an email to [email protected].
> > > > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAJiuCce7nHSktVsDKcR8GLRpD3WrN5yP3Nb_Hbu_Q9NjUQbSMw%40mail.gmail.com.
> > > > > For more options, visit https://groups.google.com/d/optout.
> > >
> > > _______________________________________________
> > > linux-arm-kernel mailing list
> > > [email protected]
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Clément,
On Tue, Jun 04, 2019 at 05:04:07PM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Tue, 4 Jun 2019 at 16:47, Ondřej Jirman <[email protected]> wrote:
> >
> > Hi Clément,
> >
> > On Tue, Jun 04, 2019 at 02:33:55PM +0200, verejna wrote:
> > > Hi Clément,
> > >
> > > On Mon, Jun 03, 2019 at 09:58:23PM +0200, Clément Péron wrote:
> > > > Hi Ondrej,
> > > >
> > > > On Fri, 31 May 2019 at 14:46, Ondřej Jirman <[email protected]> wrote:
> > > > >
> > > > > Hello Clément,
> > > > >
> > > > > On Fri, May 31, 2019 at 12:25:32AM +0200, Clément Péron wrote:
> > > > > > Hi Ondrej,
> > > > > >
> > > > > > On Thu, 30 May 2019 at 16:55, Ondřej Jirman <[email protected]> wrote:
> > > > > > >
> > > > > > > Hello Clément,
> > > > > > >
> > > > > > > On Tue, May 28, 2019 at 06:14:38PM +0200, Clément Péron wrote:
> > > > > > > > Allwinner H6 IR is similar to A31 and can use same driver.
> > > > > > > >
> > > > > > > > Add support for it.
> > > > > > > >
> > > > > > > > Signed-off-by: Clément Péron <[email protected]>
> > > > > > > > ---
> > > > > > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
> > > > > > > > 1 file changed, 19 insertions(+)
> > > > > > > >
> > > > > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > > index 16c5c3d0fd81..649cbdfe452e 100644
> > > > > > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > > @@ -647,6 +647,25 @@
> > > > > > > > pins = "PL0", "PL1";
> > > > > > > > function = "s_i2c";
> > > > > > > > };
> > > > > > > > +
> > > > > > > > + r_ir_rx_pin: r-ir-rx-pin {
> > > > > > > > + pins = "PL9";
> > > > > > > > + function = "s_cir_rx";
> > > > > > > > + };
> > > > > > > > + };
> > > > > > > > +
> > > > > > > > + r_ir: ir@7040000 {
> > > > > > > > + compatible = "allwinner,sun50i-h6-ir",
> > > > > > > > + "allwinner,sun6i-a31-ir";
> > > > > > > > + reg = <0x07040000 0x400>;
> > > > > > > > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > > + clocks = <&r_ccu CLK_R_APB1_IR>,
> > > > > > > > + <&r_ccu CLK_IR>;
> > > > > > > > + clock-names = "apb", "ir";
> > > > > > > > + resets = <&r_ccu RST_R_APB1_IR>;
> > > > > > > > + pinctrl-names = "default";
> > > > > > > > + pinctrl-0 = <&r_ir_rx_pin>;
> > > > > > > > + status = "disabled";
> > > > > > > > };
> > > > > > >
> > > > > > > Please make a comment here, that this is known broken on some boards and may
> > > > > > > result IRQ flood if enabled. Otherwise noone will know.
> > > > > >
> > > > > > I'm planning to send a v4 next week with the IRQ_NONE return as Maxime
> > > > > > suggested it.
> > > > > > https://github.com/clementperon/linux/tree/h6_ir_v4
> > > > > >
> > > > > > But maybe we could also use the bit 5 of the IRQ status.
> > > > >
> > > > > Thanks, that's nice, but that will not make the HW work. That will just disable
> > > > > it. The comment is still necessary.
> > > > I have pushed a new version on my github.
> > > > https://github.com/clementperon/linux/commits/h6_ir_v4
> > > >
> > > > I will submit it, if you are ok with it.
> > >
> > > the changes make it worse. Console is flooded with "Temporarily disable IRQ"
> > > and other symptoms are the same as I described before. Interrupts are not
> > > disabled in a any reasonable time. (I've waited for more > 5mins already.)
> > >
> > > You probably need to disable interrupts right away, not wait for 100k failures.
> >
> > Hmm, this is what the registers look like post-probe:
> >
> > R_CIR:
> > 0x07040000 : 00000030
> > 0x07040004 : 00000030
> > 0x07040008 : 00000030
> > 0x0704000c : 00000030
> > 0x07040010 : 00000030
> > 0x07040014 : 00000030
> > 0x07040018 : 00000030
> > 0x0704001c : 00000030
> > 0x07040020 : 00000030
> > 0x07040024 : 00000030
> > 0x07040028 : 00000030
> > 0x0704002c : 00000030
> > 0x07040030 : 00000030
> > 0x07040034 : 00000030
> > 0x07040038 : 00000030
> > 0x0704003c : 00000030
> > 0x07040040 : 00000030
> > 0x07040044 : 00000030
> > 0x07040048 : 00000030
> > 0x0704004c : 00000030
> > 0x07040050 : 00000030
> > 0x07040054 : 00000030
> > 0x07040058 : 00000030
> > 0x0704005c : 00000030
> > 0x07040060 : 00000030
> > 0x07040064 : 00000030
> > 0x07040068 : 00000030
> > 0x0704006c : 00000030
> > 0x07040070 : 00000030
> > 0x07040074 : 00000030
> > 0x07040078 : 00000030
> > 0x0704007c : 00000030
> > 0x07040080 : 00000030
> > 0x07040084 : 00000030
> > 0x07040088 : 00000030
> > 0x0704008c : 00000030
> > 0x07040090 : 00000030
> > 0x07040094 : 00000030
> > 0x07040098 : 00000030
> > 0x0704009c : 00000030
> > 0x070400a0 : 00000030
> > 0x070400a4 : 00000030
> > 0x070400a8 : 00000030
> > 0x070400ac : 00000030
> > 0x070400b0 : 00000030
> > 0x070400b4 : 00000030
> > 0x070400b8 : 00000030
> > 0x070400bc : 00000030
> > 0x070400c0 : 00000030
> > 0x070400c4 : 00000030
> > 0x070400c8 : 00000030
> > 0x070400cc : 00000030
> > 0x070400d0 : 00000030
> > 0x070400d4 : 00000030
> > 0x070400d8 : 00000030
> > 0x070400dc : 00000030
> > 0x070400e0 : 00000030
> > 0x070400e4 : 00000030
> > 0x070400e8 : 00000030
> > 0x070400ec : 00000030
> > 0x070400f0 : 00000030
> > 0x070400f4 : 00000030
> > 0x070400f8 : 00000030
> > 0x070400fc : 00000030
> >
> > Clearly not right. It's just the R_CIR module, other modules have normal values.
> >
> > I've checked:
> > 0x070101c0 : 81000002
> > (IR clock config register)
> > 0x070101cc : 00010000
> > (IR reset/bus clk gate reg)
> >
> > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> > static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
> > r_mod0_default_parents, 0x1c0,
> > 0, 5, /* M */
> > 8, 2, /* P */
> > 24, 1, /* mux */
> > BIT(31), /* gate */
> > 0);
> >
> > static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> > 0x1cc, BIT(0), 0);
> >
> > [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
> >
> > So parent clock seems to be OK. But gate clock is not enabled, so the bus
> > is not working.
> >
> > And look at this!!:
> >
> > static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> > 0x1cc, BIT(0), 0);
> > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> > 0x1cc, BIT(0), 0);
> >
> > So, it's wrong w1 gate config!
> >
> > You can drop your changes, because I've probbably found the root cause.
>
> Nice to see that you have found the issue, but I don't understand why
> It's working on my board on not on yours.
Maybe you use modules? I have a builtin driver.
That may change initialization order. It would disable unused gates first, and
when you load the module later from userpsace then it would enable the gate.
If builtin, then it would enable IR gate first, and then disable the unused
gates (W1 in this case), later on when entering userspace.
Anyway, I can confirm that now, when I turn on the light in the room, I get
around 10 interrupts with empty FIFO and than it stops.
It doesn't cause the flood anymore.
regards,
o.
> Regards,
> Clément
>
> >
> > regards,
> > o.
> >
> > > thank you and regards,
> > > o.
> > >
> > > > Thanks,
> > > > Clément
> > > >
> > > > >
> > > > > thank you,
> > > > > o.
> > > > >
> > > > > > Regards, Clement
> > > > > >
> > > > > > >
> > > > > > > thanks,
> > > > > > > o.
> > > > > > >
> > > > > > > > r_i2c: i2c@7081400 {
> > > > > > > > --
> > > > > > > > 2.20.1
> > > > > > > >
> > > > > > > >
> > > > > > > > _______________________________________________
> > > > > > > > linux-arm-kernel mailing list
> > > > > > > > [email protected]
> > > > > > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > > > > >
> > > > > > --
> > > > > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > > > > > To unsubscribe from this group and stop receiving emails from it, send an email to [email protected].
> > > > > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAJiuCce7nHSktVsDKcR8GLRpD3WrN5yP3Nb_Hbu_Q9NjUQbSMw%40mail.gmail.com.
> > > > > > For more options, visit https://groups.google.com/d/optout.
> > > >
> > > > _______________________________________________
> > > > linux-arm-kernel mailing list
> > > > [email protected]
> > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > >
> > > _______________________________________________
> > > linux-arm-kernel mailing list
> > > [email protected]
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Ondrej,
On Tue, 4 Jun 2019 at 17:30, Ondřej Jirman <[email protected]> wrote:
>
> Hi Clément,
>
> On Tue, Jun 04, 2019 at 05:04:07PM +0200, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Tue, 4 Jun 2019 at 16:47, Ondřej Jirman <[email protected]> wrote:
> > >
> > > Hi Clément,
> > >
> > > On Tue, Jun 04, 2019 at 02:33:55PM +0200, verejna wrote:
> > > > Hi Clément,
> > > >
> > > > On Mon, Jun 03, 2019 at 09:58:23PM +0200, Clément Péron wrote:
> > > > > Hi Ondrej,
> > > > >
> > > > > On Fri, 31 May 2019 at 14:46, Ondřej Jirman <[email protected]> wrote:
> > > > > >
> > > > > > Hello Clément,
> > > > > >
> > > > > > On Fri, May 31, 2019 at 12:25:32AM +0200, Clément Péron wrote:
> > > > > > > Hi Ondrej,
> > > > > > >
> > > > > > > On Thu, 30 May 2019 at 16:55, Ondřej Jirman <[email protected]> wrote:
> > > > > > > >
> > > > > > > > Hello Clément,
> > > > > > > >
> > > > > > > > On Tue, May 28, 2019 at 06:14:38PM +0200, Clément Péron wrote:
> > > > > > > > > Allwinner H6 IR is similar to A31 and can use same driver.
> > > > > > > > >
> > > > > > > > > Add support for it.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Clément Péron <[email protected]>
> > > > > > > > > ---
> > > > > > > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
> > > > > > > > > 1 file changed, 19 insertions(+)
> > > > > > > > >
> > > > > > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > > > index 16c5c3d0fd81..649cbdfe452e 100644
> > > > > > > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > > > > > > > @@ -647,6 +647,25 @@
> > > > > > > > > pins = "PL0", "PL1";
> > > > > > > > > function = "s_i2c";
> > > > > > > > > };
> > > > > > > > > +
> > > > > > > > > + r_ir_rx_pin: r-ir-rx-pin {
> > > > > > > > > + pins = "PL9";
> > > > > > > > > + function = "s_cir_rx";
> > > > > > > > > + };
> > > > > > > > > + };
> > > > > > > > > +
> > > > > > > > > + r_ir: ir@7040000 {
> > > > > > > > > + compatible = "allwinner,sun50i-h6-ir",
> > > > > > > > > + "allwinner,sun6i-a31-ir";
> > > > > > > > > + reg = <0x07040000 0x400>;
> > > > > > > > > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > > > + clocks = <&r_ccu CLK_R_APB1_IR>,
> > > > > > > > > + <&r_ccu CLK_IR>;
> > > > > > > > > + clock-names = "apb", "ir";
> > > > > > > > > + resets = <&r_ccu RST_R_APB1_IR>;
> > > > > > > > > + pinctrl-names = "default";
> > > > > > > > > + pinctrl-0 = <&r_ir_rx_pin>;
> > > > > > > > > + status = "disabled";
> > > > > > > > > };
> > > > > > > >
> > > > > > > > Please make a comment here, that this is known broken on some boards and may
> > > > > > > > result IRQ flood if enabled. Otherwise noone will know.
> > > > > > >
> > > > > > > I'm planning to send a v4 next week with the IRQ_NONE return as Maxime
> > > > > > > suggested it.
> > > > > > > https://github.com/clementperon/linux/tree/h6_ir_v4
> > > > > > >
> > > > > > > But maybe we could also use the bit 5 of the IRQ status.
> > > > > >
> > > > > > Thanks, that's nice, but that will not make the HW work. That will just disable
> > > > > > it. The comment is still necessary.
> > > > > I have pushed a new version on my github.
> > > > > https://github.com/clementperon/linux/commits/h6_ir_v4
> > > > >
> > > > > I will submit it, if you are ok with it.
> > > >
> > > > the changes make it worse. Console is flooded with "Temporarily disable IRQ"
> > > > and other symptoms are the same as I described before. Interrupts are not
> > > > disabled in a any reasonable time. (I've waited for more > 5mins already.)
> > > >
> > > > You probably need to disable interrupts right away, not wait for 100k failures.
> > >
> > > Hmm, this is what the registers look like post-probe:
> > >
> > > R_CIR:
> > > 0x07040000 : 00000030
> > > 0x07040004 : 00000030
> > > 0x07040008 : 00000030
> > > 0x0704000c : 00000030
> > > 0x07040010 : 00000030
> > > 0x07040014 : 00000030
> > > 0x07040018 : 00000030
> > > 0x0704001c : 00000030
> > > 0x07040020 : 00000030
> > > 0x07040024 : 00000030
> > > 0x07040028 : 00000030
> > > 0x0704002c : 00000030
> > > 0x07040030 : 00000030
> > > 0x07040034 : 00000030
> > > 0x07040038 : 00000030
> > > 0x0704003c : 00000030
> > > 0x07040040 : 00000030
> > > 0x07040044 : 00000030
> > > 0x07040048 : 00000030
> > > 0x0704004c : 00000030
> > > 0x07040050 : 00000030
> > > 0x07040054 : 00000030
> > > 0x07040058 : 00000030
> > > 0x0704005c : 00000030
> > > 0x07040060 : 00000030
> > > 0x07040064 : 00000030
> > > 0x07040068 : 00000030
> > > 0x0704006c : 00000030
> > > 0x07040070 : 00000030
> > > 0x07040074 : 00000030
> > > 0x07040078 : 00000030
> > > 0x0704007c : 00000030
> > > 0x07040080 : 00000030
> > > 0x07040084 : 00000030
> > > 0x07040088 : 00000030
> > > 0x0704008c : 00000030
> > > 0x07040090 : 00000030
> > > 0x07040094 : 00000030
> > > 0x07040098 : 00000030
> > > 0x0704009c : 00000030
> > > 0x070400a0 : 00000030
> > > 0x070400a4 : 00000030
> > > 0x070400a8 : 00000030
> > > 0x070400ac : 00000030
> > > 0x070400b0 : 00000030
> > > 0x070400b4 : 00000030
> > > 0x070400b8 : 00000030
> > > 0x070400bc : 00000030
> > > 0x070400c0 : 00000030
> > > 0x070400c4 : 00000030
> > > 0x070400c8 : 00000030
> > > 0x070400cc : 00000030
> > > 0x070400d0 : 00000030
> > > 0x070400d4 : 00000030
> > > 0x070400d8 : 00000030
> > > 0x070400dc : 00000030
> > > 0x070400e0 : 00000030
> > > 0x070400e4 : 00000030
> > > 0x070400e8 : 00000030
> > > 0x070400ec : 00000030
> > > 0x070400f0 : 00000030
> > > 0x070400f4 : 00000030
> > > 0x070400f8 : 00000030
> > > 0x070400fc : 00000030
> > >
> > > Clearly not right. It's just the R_CIR module, other modules have normal values.
> > >
> > > I've checked:
> > > 0x070101c0 : 81000002
> > > (IR clock config register)
> > > 0x070101cc : 00010000
> > > (IR reset/bus clk gate reg)
> > >
> > > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> > > static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
> > > r_mod0_default_parents, 0x1c0,
> > > 0, 5, /* M */
> > > 8, 2, /* P */
> > > 24, 1, /* mux */
> > > BIT(31), /* gate */
> > > 0);
> > >
> > > static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> > > 0x1cc, BIT(0), 0);
> > >
> > > [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
> > >
> > > So parent clock seems to be OK. But gate clock is not enabled, so the bus
> > > is not working.
> > >
> > > And look at this!!:
> > >
> > > static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> > > 0x1cc, BIT(0), 0);
> > > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> > > 0x1cc, BIT(0), 0);
> > >
> > > So, it's wrong w1 gate config!
> > >
> > > You can drop your changes, because I've probbably found the root cause.
> >
> > Nice to see that you have found the issue, but I don't understand why
> > It's working on my board on not on yours.
>
> Maybe you use modules? I have a builtin driver.
Correct,
>
> That may change initialization order. It would disable unused gates first, and
> when you load the module later from userpsace then it would enable the gate.
>
> If builtin, then it would enable IR gate first, and then disable the unused
> gates (W1 in this case), later on when entering userspace.
Thanks for the explanation it makes sense.
>
> Anyway, I can confirm that now, when I turn on the light in the room, I get
> around 10 interrupts with empty FIFO and than it stops.
Ok I will push a V4 with just the introduction of the RXSTA.
Regards,
Clément
>
> It doesn't cause the flood anymore.
>
> regards,
> o.
>
> > Regards,
> > Clément
> >
> > >
> > > regards,
> > > o.
> > >
> > > > thank you and regards,
> > > > o.
> > > >
> > > > > Thanks,
> > > > > Clément
> > > > >
> > > > > >
> > > > > > thank you,
> > > > > > o.
> > > > > >
> > > > > > > Regards, Clement
> > > > > > >
> > > > > > > >
> > > > > > > > thanks,
> > > > > > > > o.
> > > > > > > >
> > > > > > > > > r_i2c: i2c@7081400 {
> > > > > > > > > --
> > > > > > > > > 2.20.1
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > _______________________________________________
> > > > > > > > > linux-arm-kernel mailing list
> > > > > > > > > [email protected]
> > > > > > > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > > > > > >
> > > > > > > --
> > > > > > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > > > > > > To unsubscribe from this group and stop receiving emails from it, send an email to [email protected].
> > > > > > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAJiuCce7nHSktVsDKcR8GLRpD3WrN5yP3Nb_Hbu_Q9NjUQbSMw%40mail.gmail.com.
> > > > > > > For more options, visit https://groups.google.com/d/optout.
> > > > >
> > > > > _______________________________________________
> > > > > linux-arm-kernel mailing list
> > > > > [email protected]
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> > > >
> > > > _______________________________________________
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> >
> > _______________________________________________
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> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Tue, 28 May 2019 18:14:29 +0200, =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= wrote:
> Allwinner A31 has introduced a new memory mapping and a
> reset line.
>
> The difference in memory mapping are :
>
> - In the configure register there is a new sample bit
> and Allwinner has introduced the active threshold feature.
>
> - In the status register a new STAT bit is present.
>
> Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
> and on new SoCs like A64/H6.
> This is actually not an issue as these bits are togglable and new
> SoCs have a dedicated bindings.
>
> Introduce this bindings to make a difference since this generation.
> And declare the reset line required since A31.
>
> Signed-off-by: Cl?ment P?ron <[email protected]>
> ---
> Documentation/devicetree/bindings/media/sunxi-ir.txt | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>