Move common code converting clock rate to an appropriate constant and
configuring SYS_PLLPARAM register into a separate routine and convert
the rest of the code to use it. No functional change intended.
Signed-off-by: Andrey Smirnov <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Cc: Archit Taneja <[email protected]>
Cc: Andrzej Hajda <[email protected]>
Cc: Laurent Pinchart <[email protected]>
Cc: Tomi Valkeinen <[email protected]>
Cc: Andrey Gusakov <[email protected]>
Cc: Philipp Zabel <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/gpu/drm/bridge/tc358767.c | 46 +++++++++++--------------------
1 file changed, 16 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 4bb9b15e1324..ac55b59249e3 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -581,35 +581,40 @@ static int tc_stream_clock_calc(struct tc_data *tc)
return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
}
-static int tc_aux_link_setup(struct tc_data *tc)
+static int tc_set_syspllparam(struct tc_data *tc)
{
unsigned long rate;
- u32 dp0_auxcfg1;
- u32 value;
- int ret;
+ u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
rate = clk_get_rate(tc->refclk);
switch (rate) {
case 38400000:
- value = REF_FREQ_38M4;
+ pllparam |= REF_FREQ_38M4;
break;
case 26000000:
- value = REF_FREQ_26M;
+ pllparam |= REF_FREQ_26M;
break;
case 19200000:
- value = REF_FREQ_19M2;
+ pllparam |= REF_FREQ_19M2;
break;
case 13000000:
- value = REF_FREQ_13M;
+ pllparam |= REF_FREQ_13M;
break;
default:
dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
return -EINVAL;
}
+ return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
+}
+
+static int tc_aux_link_setup(struct tc_data *tc)
+{
+ int ret;
+ u32 dp0_auxcfg1;
+
/* Setup DP-PHY / PLL */
- value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
- ret = regmap_write(tc->regmap, SYS_PLLPARAM, value);
+ ret = tc_set_syspllparam(tc);
if (ret)
goto err;
@@ -868,7 +873,6 @@ static int tc_main_link_enable(struct tc_data *tc)
{
struct drm_dp_aux *aux = &tc->aux;
struct device *dev = tc->dev;
- unsigned int rate;
u32 dp_phy_ctrl;
u32 value;
int ret;
@@ -896,25 +900,7 @@ static int tc_main_link_enable(struct tc_data *tc)
if (ret)
return ret;
- rate = clk_get_rate(tc->refclk);
- switch (rate) {
- case 38400000:
- value = REF_FREQ_38M4;
- break;
- case 26000000:
- value = REF_FREQ_26M;
- break;
- case 19200000:
- value = REF_FREQ_19M2;
- break;
- case 13000000:
- value = REF_FREQ_13M;
- break;
- default:
- return -EINVAL;
- }
- value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
- ret = regmap_write(tc->regmap, SYS_PLLPARAM, value);
+ ret = tc_set_syspllparam(tc);
if (ret)
return ret;
--
2.21.0
On 07.06.2019 06:45, Andrey Smirnov wrote:
> Move common code converting clock rate to an appropriate constant and
> configuring SYS_PLLPARAM register into a separate routine and convert
> the rest of the code to use it. No functional change intended.
>
> Signed-off-by: Andrey Smirnov <[email protected]>
> Reviewed-by: Laurent Pinchart <[email protected]>
Reviewed-by: Andrzej Hajda <[email protected]>
--
Regards
Andrzej
> Cc: Archit Taneja <[email protected]>
> Cc: Andrzej Hajda <[email protected]>
> Cc: Laurent Pinchart <[email protected]>
> Cc: Tomi Valkeinen <[email protected]>
> Cc: Andrey Gusakov <[email protected]>
> Cc: Philipp Zabel <[email protected]>
> Cc: Chris Healy <[email protected]>
> Cc: Cory Tusar <[email protected]>
> Cc: Lucas Stach <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> ---
> drivers/gpu/drm/bridge/tc358767.c | 46 +++++++++++--------------------
> 1 file changed, 16 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 4bb9b15e1324..ac55b59249e3 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -581,35 +581,40 @@ static int tc_stream_clock_calc(struct tc_data *tc)
> return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
> }
>
> -static int tc_aux_link_setup(struct tc_data *tc)
> +static int tc_set_syspllparam(struct tc_data *tc)
> {
> unsigned long rate;
> - u32 dp0_auxcfg1;
> - u32 value;
> - int ret;
> + u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
>
> rate = clk_get_rate(tc->refclk);
> switch (rate) {
> case 38400000:
> - value = REF_FREQ_38M4;
> + pllparam |= REF_FREQ_38M4;
> break;
> case 26000000:
> - value = REF_FREQ_26M;
> + pllparam |= REF_FREQ_26M;
> break;
> case 19200000:
> - value = REF_FREQ_19M2;
> + pllparam |= REF_FREQ_19M2;
> break;
> case 13000000:
> - value = REF_FREQ_13M;
> + pllparam |= REF_FREQ_13M;
> break;
> default:
> dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
> return -EINVAL;
> }
>
> + return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
> +}
> +
> +static int tc_aux_link_setup(struct tc_data *tc)
> +{
> + int ret;
> + u32 dp0_auxcfg1;
> +
> /* Setup DP-PHY / PLL */
> - value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
> - ret = regmap_write(tc->regmap, SYS_PLLPARAM, value);
> + ret = tc_set_syspllparam(tc);
> if (ret)
> goto err;
>
> @@ -868,7 +873,6 @@ static int tc_main_link_enable(struct tc_data *tc)
> {
> struct drm_dp_aux *aux = &tc->aux;
> struct device *dev = tc->dev;
> - unsigned int rate;
> u32 dp_phy_ctrl;
> u32 value;
> int ret;
> @@ -896,25 +900,7 @@ static int tc_main_link_enable(struct tc_data *tc)
> if (ret)
> return ret;
>
> - rate = clk_get_rate(tc->refclk);
> - switch (rate) {
> - case 38400000:
> - value = REF_FREQ_38M4;
> - break;
> - case 26000000:
> - value = REF_FREQ_26M;
> - break;
> - case 19200000:
> - value = REF_FREQ_19M2;
> - break;
> - case 13000000:
> - value = REF_FREQ_13M;
> - break;
> - default:
> - return -EINVAL;
> - }
> - value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
> - ret = regmap_write(tc->regmap, SYS_PLLPARAM, value);
> + ret = tc_set_syspllparam(tc);
> if (ret)
> return ret;
>