This patch series adds the needed clkctrl and ty-sysc nodes for CAL module.
It also adds support for the module in related dtsi and dts for DRA72,
DRA76 and AM654 SoC.
Changes since v2:
- Add non-standard clock node naming to commit message as per Tony's
comment
Changes since v1:
- Fix clock name to make it generic
- Updated the binding to use ti,camerrx-control instead of sycon_camerrx
- Split off the clk code into its own patch
- Add clk mailing list as requested
Benoit Parrot (10):
clk: ti: dra7: add cam clkctrl data
ARM: dts: dra7: add cam clkctrl node
ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only
ARM: dts: dra7-l4: Add ti-sysc node for CAM
ARM: dts: DRA72: Add CAL dtsi node
arm: dts: dra72-evm-common: Add entries for the CSI2 cameras
arm: dtsi: dra76x: Add CAL dtsi node
arm: dts: dra76-evm: Add CAL and OV5640 nodes
arm64: dts: k3-am65-main Add CAL node
arm64: dts: k3-am654-base-board: Add CSI2 OV5640 camera
arch/arm/boot/dts/dra7-l4.dtsi | 43 ++++++++++++++++---
arch/arm/boot/dts/dra72-evm-common.dtsi | 35 +++++++++++++++
arch/arm/boot/dts/dra72x.dtsi | 43 +++++++++++++++++++
arch/arm/boot/dts/dra76-evm.dts | 39 +++++++++++++++++
arch/arm/boot/dts/dra76x.dtsi | 43 +++++++++++++++++++
arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 ++++++
arch/arm/mach-omap2/clockdomains7xx_data.c | 2 +-
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 23 ++++++++++
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 36 ++++++++++++++++
drivers/clk/ti/clk-7xx.c | 19 ++++++++
include/dt-bindings/clock/dra7.h | 10 +++++
11 files changed, 300 insertions(+), 7 deletions(-)
--
2.17.1
Both CAL and VIP rely on this clock domain. But CAL DPHY require
LVDSRX_96M_GFCLK to be active. When this domain is set to HWSUP the
LVDSRX_96M_GFCLK is on;y active when VIP1 clock is also active. If only
CAL on DRA72x (which uses the VIP2 clkctrl) probes the CAM domain is
enabled but the LVDSRX_96M_GFCLK is left gated. Since LVDSRX_96M_GFCLK
is sourcing the input clock to the DPHY then actual frame capture cannot
start as the phy are inactive.
So we either have to also enabled VIP1 even if we don't intend on using
it or we need to set the CAM domain to use SWSUP only.
This patch implements the latter.
Signed-off-by: Benoit Parrot <[email protected]>
---
arch/arm/mach-omap2/clockdomains7xx_data.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
index 3068802824b7..27835c4d1aa9 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -606,7 +606,7 @@ static struct clockdomain cam_7xx_clkdm = {
.dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
.wkdep_srcs = cam_wkup_sleep_deps,
.sleepdep_srcs = cam_wkup_sleep_deps,
- .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4per_7xx_clkdm = {
--
2.17.1
Add the required dtsi node to support the Camera
Adaptation Layer (CAL) for the DRA76 family of devices.
Signed-off-by: Benoit Parrot <[email protected]>
---
arch/arm/boot/dts/dra76x.dtsi | 43 +++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
index cdcba3f561c4..2f58c709c081 100644
--- a/arch/arm/boot/dts/dra76x.dtsi
+++ b/arch/arm/boot/dts/dra76x.dtsi
@@ -41,6 +41,49 @@
};
+&l4_per3 {
+ target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x1b0000 0x4>,
+ <0x1b0010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1b0000 0x10000>;
+
+ cal: cal@0 {
+ compatible = "ti,dra76-cal";
+ reg = <0x0000 0x400>,
+ <0x0800 0x40>,
+ <0x0900 0x40>;
+ reg-names = "cal_top",
+ "cal_rx_core0",
+ "cal_rx_core1";
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ ti,camerrx-control = <&scm_conf 0x6dc>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi2_0: port@0 {
+ reg = <0>;
+ };
+ csi2_1: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
+};
+
/* MCAN interrupts are hard-wired to irqs 67, 68 */
&crossbar_mpu {
ti,irqs-skip = <10 67 68 133 139 140>;
--
2.17.1
Add support for the OV5640 CSI camera:
- add the OV5640 nodes
- add the CAL node linkage
- enable CAL node
Signed-off-by: Benoit Parrot <[email protected]>
---
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 1102b84f853d..73290c646334 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -53,6 +53,12 @@
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
};
};
+
+ clk_ov5640_fixed: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
};
&wkup_pmx0 {
@@ -184,6 +190,23 @@
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
+
+ ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2_phy0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
};
&main_i2c2 {
@@ -280,3 +303,16 @@
&pcie1_ep {
status = "disabled";
};
+
+&cal {
+ status = "okay";
+};
+
+&csi2_0 {
+ csi2_phy0: endpoint@0 {
+ remote-endpoint = <&csi2_cam0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+};
+
--
2.17.1
Add device nodes for CSI2 camera board OV5640.
Add the CAL port nodes with the necessary linkage to the ov5640 nodes.
Signed-off-by: Benoit Parrot <[email protected]>
---
arch/arm/boot/dts/dra72-evm-common.dtsi | 35 +++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 8641a3d7d8ad..608c7676c293 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -187,6 +187,12 @@
gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ clk_ov5640_fixed: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
};
&dra7_pmx_core {
@@ -269,6 +275,23 @@
line-name = "vin6_sel_s0";
};
};
+
+ ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2_phy0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
};
&uart1 {
@@ -580,3 +603,15 @@
&pcie1_rc {
status = "okay";
};
+
+&cal {
+ status = "okay";
+};
+
+&csi2_0 {
+ csi2_phy0: endpoint@0 {
+ remote-endpoint = <&csi2_cam0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+};
--
2.17.1
Add clkctrl data for CAM domain.
Signed-off-by: Benoit Parrot <[email protected]>
---
drivers/clk/ti/clk-7xx.c | 19 +++++++++++++++++++
include/dt-bindings/clock/dra7.h | 10 ++++++++++
2 files changed, 29 insertions(+)
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 5dd9cad07542..8f2204a36b51 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -151,6 +151,24 @@ static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst =
{ 0 },
};
+static const char * const dra7_cam_gfclk_mux_parents[] __initconst = {
+ "l3_iclk_div",
+ "core_iss_main_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_cam_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = {
+ { DRA7_CAM_VIP1_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_CAM_VIP2_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_CAM_VIP3_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { 0 },
+};
+
static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
{ DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
{ DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
@@ -783,6 +801,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
{ 0x4a008c00, dra7_atl_clkctrl_regs },
{ 0x4a008d20, dra7_l4cfg_clkctrl_regs },
{ 0x4a008e20, dra7_l3instr_clkctrl_regs },
+ { 0x4a009020, dra7_cam_clkctrl_regs },
{ 0x4a009120, dra7_dss_clkctrl_regs },
{ 0x4a009320, dra7_l3init_clkctrl_regs },
{ 0x4a0093b0, dra7_pcie_clkctrl_regs },
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h
index 2b765e579b2a..2c058a534bab 100644
--- a/include/dt-bindings/clock/dra7.h
+++ b/include/dt-bindings/clock/dra7.h
@@ -34,6 +34,11 @@
#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
+/* vip clocks */
+#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+
/* coreaon clocks */
#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
@@ -202,6 +207,11 @@
#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
#define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
+/* vip clocks */
+#define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+
/* coreaon clocks */
#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
--
2.17.1
This patch adds the required dtsi node to support the Camera
Adaptation Layer (CAL) for the DRA72 family of devices.
Signed-off-by: Benoit Parrot <[email protected]>
---
arch/arm/boot/dts/dra72x.dtsi | 43 +++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index f5762709c853..726e46ae887d 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -17,6 +17,49 @@
};
};
+&l4_per2 {
+ target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5b000 0x4>,
+ <0x5b010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+
+ cal: cal@0 {
+ compatible = "ti,dra72-cal";
+ reg = <0x0000 0x400>,
+ <0x0800 0x40>,
+ <0x0900 0x40>;
+ reg-names = "cal_top",
+ "cal_rx_core0",
+ "cal_rx_core1";
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ ti,camerrx-control = <&scm_conf 0xE94>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi2_0: port@0 {
+ reg = <0>;
+ };
+ csi2_1: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
+};
+
&dss {
reg = <0x58000000 0x80>,
<0x58004054 0x4>,
--
2.17.1
Add device nodes for CSI2 camera board OV5640.
Add the CAL port nodes with the necessary linkage to the ov5640 nodes.
Signed-off-by: Benoit Parrot <[email protected]>
---
arch/arm/boot/dts/dra76-evm.dts | 39 +++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index 1fb6f13fb5e2..a0a4bf0e1e30 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -116,6 +116,12 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
+ clk_ov5640_fixed: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
};
&i2c1 {
@@ -317,6 +323,27 @@
};
};
+&i2c5 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2_phy0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
&cpu0 {
vdd-supply = <&buck10_reg>;
};
@@ -447,3 +474,15 @@
max-bitrate = <5000000>;
};
};
+
+&cal {
+ status = "okay";
+};
+
+&csi2_0 {
+ csi2_phy0: endpoint@0 {
+ remote-endpoint = <&csi2_cam0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+};
--
2.17.1
Add CAM nodes as a child of l4 interconnect in order for it to probe
using ti-sysc.
Signed-off-by: Benoit Parrot <[email protected]>
---
arch/arm/boot/dts/dra7-l4.dtsi | 43 +++++++++++++++++++++++++++++-----
1 file changed, 37 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 0917231a20e2..8f5c26a4f7c8 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -4135,27 +4135,58 @@
};
target-module@170000 { /* 0x48970000, ap 21 0a.0 */
- compatible = "ti,sysc";
- status = "disabled";
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x170010 0x4>;
+ reg-names = "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x170000 0x10000>;
+ status = "disabled";
};
target-module@190000 { /* 0x48990000, ap 23 2e.0 */
- compatible = "ti,sysc";
- status = "disabled";
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x190010 0x4>;
+ reg-names = "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x190000 0x10000>;
+ status = "disabled";
};
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
- compatible = "ti,sysc";
- status = "disabled";
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x1b0000 0x4>,
+ <0x1b0010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1b0000 0x10000>;
+ status = "disabled";
};
target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
--
2.17.1
Add CAL dtsi node for AM654 device. Including proper power-domains and
clock properties.
Signed-off-by: Benoit Parrot <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 799c75fa7981..4c65ed445e8b 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -516,4 +516,27 @@
dma-coherent;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
};
+
+ cal: cal@6f03000 {
+ compatible = "ti,am654-cal";
+ reg = <0x0 0x06f03000 0x0 0x400>,
+ <0x0 0x06f03800 0x0 0x40>;
+ reg-names = "cal_top",
+ "cal_rx_core0";
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ ti,camerrx-control = <&scm_conf 0x40c0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 2 0>;
+ power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi2_0: port@0 {
+ reg = <0>;
+ };
+ };
+ };
};
--
2.17.1
Add clkctrl nodes for CAM domain.
Note that because of the current dts node name dependency for mapping to
clock domain, we must still use "cam-clkctrl@" naming instead of generic
"clock@" naming for the node. And because of this, it's probably best to
apply the dts node addition together along with the other clock changes.
Signed-off-by: Benoit Parrot <[email protected]>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d1c2406ec71c..199f8d483f75 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1734,6 +1734,20 @@
};
};
+ cam_cm: cam-cm@1000 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x100>;
+
+ cam_clkctrl: cam-clkctrl@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x2c>;
+ #clock-cells = <2>;
+ };
+ };
+
dss_cm: dss-cm@1100 {
compatible = "ti,omap4-cm";
reg = <0x1100 0x100>;
--
2.17.1
* Benoit Parrot <[email protected]> [191112 14:25]:
> Add clkctrl data for CAM domain.
Acked-by: Tony Lindgren <[email protected]>
* Benoit Parrot <[email protected]> [191112 14:25]:
> Both CAL and VIP rely on this clock domain. But CAL DPHY require
> LVDSRX_96M_GFCLK to be active. When this domain is set to HWSUP the
> LVDSRX_96M_GFCLK is on;y active when VIP1 clock is also active. If only
> CAL on DRA72x (which uses the VIP2 clkctrl) probes the CAM domain is
> enabled but the LVDSRX_96M_GFCLK is left gated. Since LVDSRX_96M_GFCLK
> is sourcing the input clock to the DPHY then actual frame capture cannot
> start as the phy are inactive.
>
> So we either have to also enabled VIP1 even if we don't intend on using
> it or we need to set the CAM domain to use SWSUP only.
>
> This patch implements the latter.
Best that Tero picks up this one too if OK:
Acked-by: Tony Lindgren <[email protected]>
* Benoit Parrot <[email protected]> [191112 14:25]:
> Add clkctrl nodes for CAM domain.
>
> Note that because of the current dts node name dependency for mapping to
> clock domain, we must still use "cam-clkctrl@" naming instead of generic
> "clock@" naming for the node. And because of this, it's probably best to
> apply the dts node addition together along with the other clock changes.
Thanks for updating this too.
Tero, for merging, you could create a separate clock dts changes branch
too on your clock changes if needed, up to you. Anyways best that you
queue all the clock changes and clock related dts changes:
Acked-by: Tony Lindgren <[email protected]>
* Benoit Parrot <[email protected]> [191112 14:25]:
> This patch adds the required dtsi node to support the Camera
> Adaptation Layer (CAL) for the DRA72 family of devices.
>
> Signed-off-by: Benoit Parrot <[email protected]>
> ---
> arch/arm/boot/dts/dra72x.dtsi | 43 +++++++++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
> index f5762709c853..726e46ae887d 100644
> --- a/arch/arm/boot/dts/dra72x.dtsi
> +++ b/arch/arm/boot/dts/dra72x.dtsi
> @@ -17,6 +17,49 @@
> };
> };
>
> +&l4_per2 {
> + target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
> + compatible = "ti,sysc-omap4", "ti,sysc";
> + reg = <0x5b000 0x4>,
> + <0x5b010 0x4>;
> + reg-names = "rev", "sysc";
> + ti,sysc-midle = <SYSC_IDLE_FORCE>,
> + <SYSC_IDLE_NO>;
> + ti,sysc-sidle = <SYSC_IDLE_FORCE>,
> + <SYSC_IDLE_NO>;
> + clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
> + clock-names = "fck";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x5b000 0x1000>;
> +
> + cal: cal@0 {
> + compatible = "ti,dra72-cal";
> + reg = <0x0000 0x400>,
> + <0x0800 0x40>,
> + <0x0900 0x40>;
> + reg-names = "cal_top",
> + "cal_rx_core0",
> + "cal_rx_core1";
> + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> + ti,camerrx-control = <&scm_conf 0xE94>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + csi2_0: port@0 {
> + reg = <0>;
> + };
> + csi2_1: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> + };
> +};
Just leave out the status = "disabled" here for the SoC specific dtsi
files. The SoC internal device is there for sure, even if not pinned
out. And the dts default value is status = "okay".
Regards,
Tony
* Benoit Parrot <[email protected]> [191112 14:25]:
> Add CAL dtsi node for AM654 device. Including proper power-domains and
> clock properties.
>
> Signed-off-by: Benoit Parrot <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 799c75fa7981..4c65ed445e8b 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -516,4 +516,27 @@
> dma-coherent;
> interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
> };
> +
> + cal: cal@6f03000 {
> + compatible = "ti,am654-cal";
> + reg = <0x0 0x06f03000 0x0 0x400>,
> + <0x0 0x06f03800 0x0 0x40>;
> + reg-names = "cal_top",
> + "cal_rx_core0";
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> + ti,camerrx-control = <&scm_conf 0x40c0>;
> + clock-names = "fck";
> + clocks = <&k3_clks 2 0>;
> + power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + csi2_0: port@0 {
> + reg = <0>;
> + };
> + };
> + };
> };
Here too just drop the status = "disabled" line. For reference, see commit
12afc0cf8121 ("ARM: dts: Drop pointless status changing for am3 musb")
in Linux next where we remove about 450 lines of pointless back and forth
noise from status = "disabled" to various board specific files setting
musb components back to status = "okay".
Regards,
Tony
On Tue, 12 Nov 2019 08:27:44 -0600, Benoit Parrot wrote:
> Add clkctrl data for CAM domain.
>
> Signed-off-by: Benoit Parrot <[email protected]>
> ---
> drivers/clk/ti/clk-7xx.c | 19 +++++++++++++++++++
> include/dt-bindings/clock/dra7.h | 10 ++++++++++
> 2 files changed, 29 insertions(+)
>
Acked-by: Rob Herring <[email protected]>