2020-02-25 09:04:04

by Heyi Guo

[permalink] [raw]
Subject: [PATCH] irq-gic-v3-its: fix access width for gicr_syncr

GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.

Signed-off-by: Heyi Guo <[email protected]>

---
Cc: Marc Zyngier <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Jason Cooper <[email protected]>
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 65a11257d220..5c6790e3bfbf 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)

static void wait_for_syncr(void __iomem *rdbase)
{
- while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
+ while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
cpu_relax();
}

--
2.19.1


2020-02-25 16:17:53

by Marc Zyngier

[permalink] [raw]
Subject: Re: [PATCH] irq-gic-v3-its: fix access width for gicr_syncr

On 2020-02-25 09:00, Heyi Guo wrote:
> GICR_SYNCR is a 32bit register, so it is better to access it with
> 32bit access width, though we have not seen any real problem.
>
> Signed-off-by: Heyi Guo <[email protected]>
>
> ---
> Cc: Marc Zyngier <[email protected]>
> Cc: Thomas Gleixner <[email protected]>
> Cc: Jason Cooper <[email protected]>
> ---
> drivers/irqchip/irq-gic-v3-its.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c
> b/drivers/irqchip/irq-gic-v3-its.c
> index 65a11257d220..5c6790e3bfbf 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d,
> u8 clr, u8 set)
>
> static void wait_for_syncr(void __iomem *rdbase)
> {
> - while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
> + while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
> cpu_relax();
> }

Yup, nice catch. Looks like no implementation really cares about it,
but still worth fixing.

I'll take it for 5.7.

Thanks,

M.
--
Jazz is not dead. It just smells funny...

Subject: [tip: irq/core] irqchip/gic-v3-its: Fix access width for gicr_syncr

The following commit has been merged into the irq/core branch of tip:

Commit-ID: 04d80dbe858d801efbecf3e5172b31b0a3757308
Gitweb: https://git.kernel.org/tip/04d80dbe858d801efbecf3e5172b31b0a3757308
Author: Heyi Guo <[email protected]>
AuthorDate: Tue, 25 Feb 2020 17:00:23 +08:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Sun, 08 Mar 2020 14:25:46

irqchip/gic-v3-its: Fix access width for gicr_syncr

GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.

Signed-off-by: Heyi Guo <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 83b1186..6bb2bea 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)

static void wait_for_syncr(void __iomem *rdbase)
{
- while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
+ while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
cpu_relax();
}