This series adds a few low hanging fruit that are purely DT changes to
keep the ball rolling while I work on series for more complicated things
like the interrupt controllers.
Summary of changes:
- Adds the IMI SRAM region and sets the right size for each family
- Adds the ARM PMU
- Adds a syscon for a lump of registers called "pmsleep"
- Uses the pmsleep syscon to enable reboot
Daniel Palmer (7):
ARM:mstar: Add IMI SRAM region
ARM:mstar: Adjust IMI size of infinity
ARM:mstar: Adjust IMI size for mercury5
ARM:mstar: Adjust IMI size for infinity3
ARM:mstar: Add PMU
ARM:mstar: Add syscon node for "pmsleep" area
ARM:mstar: Add reboot support
arch/arm/boot/dts/infinity.dtsi | 4 ++++
arch/arm/boot/dts/infinity3.dtsi | 4 ++++
arch/arm/boot/dts/mercury5.dtsi | 4 ++++
arch/arm/boot/dts/mstar-v7.dtsi | 26 +++++++++++++++++++++++++-
4 files changed, 37 insertions(+), 1 deletion(-)
--
2.27.0
All MStar v7 SoCs have an internal SRAM region that is between 64KB
(infinity2m) and 128KB(infinity3, mercury5).
The region is always at the same base address and is used for the
second stage loader (MStar IPL or u-boot SPL) and will be used for
the DDR self-refresh entry code within the kernel eventually.
This patch adds a 128KB region to the SoC and the minimum 64KB SRAM
region to the base dtsi. Families with more SRAM will override the
size in their family level dtsi.
Signed-off-by: Daniel Palmer <[email protected]>
---
arch/arm/boot/dts/mstar-v7.dtsi | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 3b99bb435bb5..6bc55fdbee04 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -45,7 +45,8 @@ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x16001000 0x16001000 0x00007000>,
- <0x1f000000 0x1f000000 0x00400000>;
+ <0x1f000000 0x1f000000 0x00400000>,
+ <0xa0000000 0xa0000000 0x20000>;
gic: interrupt-controller@16001000 {
compatible = "arm,cortex-a7-gic";
@@ -78,6 +79,11 @@ pm_uart: uart@221000 {
clock-frequency = <172000000>;
status = "disabled";
};
+ };
+
+ imi: sram@a0000000 {
+ compatible = "mmio-sram";
+ reg = <0xa0000000 0x10000>;
};
};
};
--
2.27.0
infinity3 has 128KB of SRAM at the IMI region.
Signed-off-by: Daniel Palmer <[email protected]>
---
arch/arm/boot/dts/infinity3.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/infinity3.dtsi b/arch/arm/boot/dts/infinity3.dtsi
index 2830d064c07d..9b918c802654 100644
--- a/arch/arm/boot/dts/infinity3.dtsi
+++ b/arch/arm/boot/dts/infinity3.dtsi
@@ -5,3 +5,7 @@
*/
#include "infinity.dtsi"
+
+&imi {
+ reg = <0xa0000000 0x20000>;
+};
--
2.27.0
MStar v7 SoCs contain a region of registers that are in the always on
domain that the vendor code calls the "pmsleep" area.
This area contains registers for a broad range of functionality and
needs to be shared between drivers.
This patch adds a syscon node for the pmsleep area so that other
drivers can access registers in the area.
Signed-off-by: Daniel Palmer <[email protected]>
---
arch/arm/boot/dts/mstar-v7.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index a73b1d162dfd..c8b192569d05 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -73,6 +73,11 @@ riu: bus@1f000000 {
#size-cells = <1>;
ranges = <0x0 0x1f000000 0x00400000>;
+ pmsleep: syscon@1c00 {
+ compatible = "syscon";
+ reg = <0x1c00 0x100>;
+ };
+
l3bridge: l3bridge@204400 {
compatible = "mstar,l3bridge";
reg = <0x204400 0x200>;
--
2.27.0
Adds the ARM PMU to the base MStar v7 dtsi.
Signed-off-by: Daniel Palmer <[email protected]>
---
arch/arm/boot/dts/mstar-v7.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 6bc55fdbee04..a73b1d162dfd 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -40,6 +40,12 @@ arch_timer {
clock-frequency = <6000000>;
};
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
--
2.27.0
mercury5 family chips have 128KB of SRAM in the IMI region.
Signed-off-by: Daniel Palmer <[email protected]>
---
arch/arm/boot/dts/mercury5.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/mercury5.dtsi b/arch/arm/boot/dts/mercury5.dtsi
index f68e6d59c328..a7d0dd9d6132 100644
--- a/arch/arm/boot/dts/mercury5.dtsi
+++ b/arch/arm/boot/dts/mercury5.dtsi
@@ -5,3 +5,7 @@
*/
#include "mstar-v7.dtsi"
+
+&imi {
+ reg = <0xa0000000 0x20000>;
+};
--
2.27.0
MStar v7 SoCs support reset by writing a magic value to a register
in the "pmsleep" area.
This adds a node for using the syscon reboot driver to trigger a reset.
Signed-off-by: Daniel Palmer <[email protected]>
---
arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index c8b192569d05..7ac7e649189f 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -78,6 +78,13 @@ pmsleep: syscon@1c00 {
reg = <0x1c00 0x100>;
};
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmsleep>;
+ offset = <0xb8>;
+ mask = <0x79>;
+ };
+
l3bridge: l3bridge@204400 {
compatible = "mstar,l3bridge";
reg = <0x204400 0x200>;
--
2.27.0
On Sun, Jul 26, 2020 at 6:40 AM Daniel Palmer <[email protected]> wrote:
>
> MStar v7 SoCs contain a region of registers that are in the always on
> domain that the vendor code calls the "pmsleep" area.
>
> This area contains registers for a broad range of functionality and
> needs to be shared between drivers.
>
> This patch adds a syscon node for the pmsleep area so that other
> drivers can access registers in the area.
>
> Signed-off-by: Daniel Palmer <[email protected]>
I think it would be better to add a more specific compatible string in
addition to the "syscon" one, to make it possible to later add a proper
driver for this area, in case there is a need for that.
Arnd
> ---
> arch/arm/boot/dts/mstar-v7.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
> index a73b1d162dfd..c8b192569d05 100644
> --- a/arch/arm/boot/dts/mstar-v7.dtsi
> +++ b/arch/arm/boot/dts/mstar-v7.dtsi
> @@ -73,6 +73,11 @@ riu: bus@1f000000 {
> #size-cells = <1>;
> ranges = <0x0 0x1f000000 0x00400000>;
>
> + pmsleep: syscon@1c00 {
> + compatible = "syscon";
> + reg = <0x1c00 0x100>;
> + };
> +
> l3bridge: l3bridge@204400 {
> compatible = "mstar,l3bridge";
> reg = <0x204400 0x200>;
> --
> 2.27.0
>
On Sun, Jul 26, 2020 at 6:39 AM Daniel Palmer <[email protected]> wrote:
>
> This series adds a few low hanging fruit that are purely DT changes to
> keep the ball rolling while I work on series for more complicated things
> like the interrupt controllers.
>
> Summary of changes:
>
> - Adds the IMI SRAM region and sets the right size for each family
> - Adds the ARM PMU
> - Adds a syscon for a lump of registers called "pmsleep"
> - Uses the pmsleep syscon to enable reboot
I had one comment for the last commit in this list and have therefore
not applied the series (yet).
I also noticed that the subject lines are slightly inconsistent, please
add a space between "ARM:" and "mstar:" as you did for the first
set of patches.
Arnd
Hi Arnd,
On Mon, 27 Jul 2020 at 21:33, Arnd Bergmann <[email protected]> wrote:
> I had one comment for the last commit in this list and have therefore
> not applied the series (yet).
I was going to wait for other comments before making a v2 but it seems like
it was just the pmsleep syscon that needs changes. I'll fix that up and send
a v2.
> I also noticed that the subject lines are slightly inconsistent, please
> add a space between "ARM:" and "mstar:" as you did for the first
> set of patches.
Oops sorry about that. Not sure why I did that. I'll fix for the next version.
Thanks,
Daniel