Add functionality to control the APLL clock on the AST2600. The APLL provides
the clock for the FSI master on the AST2600. Then add a devicetree property to
set the AST2600 FSI master bus frequency.
Eddie James (4):
dt-bindings: clock: Add AST2600 APLLdivN definition
clk: ast2600: Add functionality to the APLL clock
dt-bindings: fsi: Aspeed master: Add bus-frequency property
fsi: Aspeed master: Set bus frequency from devicetree
.../bindings/fsi/fsi-master-aspeed.txt | 1 +
drivers/clk/clk-ast2600.c | 177 ++++++++++++++++--
drivers/fsi/fsi-master-aspeed.c | 5 +
include/dt-bindings/clock/ast2600-clock.h | 1 +
4 files changed, 172 insertions(+), 12 deletions(-)
--
2.26.2
Add a new clock definition for the "APLLdivN" as described in the
AST2600 specification. This clock is simply the APLL divided by a
factor defined in the SCU registers. It is the input to the FSI
bus.
Signed-off-by: Eddie James <[email protected]>
---
include/dt-bindings/clock/ast2600-clock.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 62b9520a00fd..5a9ae0a1d574 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -87,6 +87,7 @@
#define ASPEED_CLK_MAC2RCLK 68
#define ASPEED_CLK_MAC3RCLK 69
#define ASPEED_CLK_MAC4RCLK 70
+#define ASPEED_CLK_APLLN 71
/* Only list resets here that are not part of a gate */
#define ASPEED_RESET_ADC 55
--
2.26.2
Set the FSI bus frequency based on the value encoded in the
devicetree. The default value is 166MHz, which is the highest
frequency some FSI slaves can accept.
Signed-off-by: Eddie James <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
---
drivers/fsi/fsi-master-aspeed.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c
index c006ec008a1a..be19fee0bece 100644
--- a/drivers/fsi/fsi-master-aspeed.c
+++ b/drivers/fsi/fsi-master-aspeed.c
@@ -515,6 +515,7 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)
struct fsi_master_aspeed *aspeed;
struct resource *res;
int rc, links, reg;
+ u32 bus_freq = 166666666;
__be32 raw;
rc = tacoma_cabled_fsi_fixup(&pdev->dev);
@@ -539,6 +540,10 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)
dev_err(aspeed->dev, "couldn't get clock\n");
return PTR_ERR(aspeed->clk);
}
+
+ of_property_read_u32(pdev->dev.of_node, "bus-frequency", &bus_freq);
+ clk_set_rate(aspeed->clk, bus_freq);
+
rc = clk_prepare_enable(aspeed->clk);
if (rc) {
dev_err(aspeed->dev, "couldn't enable clock\n");
--
2.26.2
On Thu, 10 Sep 2020 at 15:18, Eddie James <[email protected]> wrote:
>
> Add a new clock definition for the "APLLdivN" as described in the
> AST2600 specification. This clock is simply the APLL divided by a
> factor defined in the SCU registers. It is the input to the FSI
> bus.
Ah, that's where the name comes from. Would calling it APLL_DIV make more sense?
>
> Signed-off-by: Eddie James <[email protected]>
> ---
> include/dt-bindings/clock/ast2600-clock.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
> index 62b9520a00fd..5a9ae0a1d574 100644
> --- a/include/dt-bindings/clock/ast2600-clock.h
> +++ b/include/dt-bindings/clock/ast2600-clock.h
> @@ -87,6 +87,7 @@
> #define ASPEED_CLK_MAC2RCLK 68
> #define ASPEED_CLK_MAC3RCLK 69
> #define ASPEED_CLK_MAC4RCLK 70
> +#define ASPEED_CLK_APLLN 71
>
> /* Only list resets here that are not part of a gate */
> #define ASPEED_RESET_ADC 55
> --
> 2.26.2
>